20.7% HIGHEST EFFICIENCY

20.7% HIGHEST EFFICIENCY
CELL LARGE AREA (100.5cm2)HITTM
Hitoshi Sakata, Takuo Nakai, Toshiaki Baba, Mikio Taguchi, Sadaji Tsuge,Kenji Uchihashi and Seiichi Kiyama New Materials Research Center, Sanyo Electric Co., Ltd.
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0-7803-5772-8/00/$10.00 0 2000 IEEE
HIT structure
Figure 1 shows a drawing of the HIT cell. A very thin intrinsic a-Si:H layer and a p-type a-Si:H layer are deposited by plasma CVD on the front of a textured n-type c-Si wafer (solar grade CZ, 200 Hm, 1 acm). Another very thin intrinsic a-Si:H layer and n-type a-Si:H layer are deposited on the back of the wafer. A transparent conductive oxide (TCO) is formed on each side of the cell using a sputtering technique, and Ag electrodes are formed on the same two sides with silkscreen printing method. All the preceding processes are performed at low temperatures below 200 "C. There is no need for photomasking or multiple processing cycles at temperatures as high as 1,000 "C that cause thermal damage to the wafer, or for complex processes that result in higher cost in the so-called high efficiency solar cell processes. Since the HIT structure is able to avoid thermal stress and damage to the wafer because of the low-temperature processes and has a symmetrical construction, it can yield high conversion efficiency even with thinner (-200 pm) Si substrates. Besides, its symmetry also allows the rear of the cell to generate electricity as well.
Introduction
conversion efficiency through the realization of a back surface field with the HIT structure and the optimization of the fabrication conditions achieved a conversion efficiencyof 20.0% (JQA confirmed) for an aperture area of 1 cm'[3]. We then shifted our attention to developing a mass-production process based on the results of investigations on small-area cells and successfully launched the HIT module onto the market in 1997. The conversion efficiency at the mass-production level was 17.3% for a cell over 100 cm', and set a world record for solar cells in which the junction is fabricated at a low temperature below 200 "C. The present study was primarily concerned with raising the conversion efficiency while using mass production and solar grade materials. Our main interest was the surface passivation effect at a-SVc-Si heterointerface that most be a key issue for high
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Voltage (V)
Fig. 2. Dark I-V characteristics of HIT structure and p-n heterojunction. This suppression of backward current density suggests the better surface passivation at the a-Si/c-Si heterointerfacewith the HIT structure. Hence, we tried to investigate the effect of surface passivation directly with the carrier lifetime, which was measured by the p-PCD method [4]. According to the standard PCD theory for a homogeneously doped, defect-free wafer with a spatially uniform bulk carrier lifetime, the relationship between T~~ and 2 , is given by:
VOC in solar cell performance.
Amorphous silicon (a-Si) / crystalline silicon (c-Si) heterojunction solar cell was originally proposed for use with a-Si solar cell as the bottom cell of a stacked solar cell [l]. The features resulting from junction formation by forming film at low temperature are suitable for creating devices on thin substrates and thin-film polycrystalline silicon. We developed the HIT structure solar cell with a non-doped a-Si:H film sandwiched between p-type a-Si and n-type c-Si, and thereby achieved a significant improvement in the junction
Surface passivation effect of the a-Silayer
Figure 2 shows the dark I-V characteristics of both a p-n heterojunction and a HIT structure. With the HIT structure, the backward current density is reduced by 2 orders of magnitude and the forward current has a steep rise time. This indicates that the HIT structure offers a better junction performance with low carrier recombinationvelocity.
1-1 Dainichi-Higashimachi,Moriguchi, Osaka, 570-8502,Japan
Tel: +81-6-6900-3527,Fax: +81-6-6900-3528,E-mail: h-sakataQrd.sanvo.co.ir,
Abstract
characteristics [2].
Subsequent improvements in
A world record total area conversion efficiency of 20.7% and high open circuit voltage (VOC)of 719 mV were achieved on a solar cell with HIT (Heterojunction with Intrinsic Thin-layer) structures on both sides (wafer size: 100.5 cm', n-type solar-grade CZ-Si). This solar cell was fabricated with the same process as that used in our mass-production lines. The essence of this high performance is derived from the excellent passivation ability of the HIT structure on c-Si. This report discusses recent research forward excess of 20% efficiency HIT cell (-100 cm'), focusing on the a-Si passivation effect estimated from the carrier lifetime, and describes product development for the industrializationof HIT cells.