eda常用程序的参考程序

常用程序：
仅供参考，不得用于商业目的
【减法器】
1位减法器：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.all;
entity subber1 is
port(a,b,cin:in std_logic;
s:out std_logic;
cout: out std_logic);
end subber1;
architecture one of subber1 is
begin
s<= (a xor b) xor cin;
cout<= ((not a)nand b)nand(not(a xor b) nand cin); end one;
4位减法器：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE WORK.my_pkg.all;
entity subber4 is
port(a,b:in std_logic_vector(3 downto 0);
cin: in std_logic;
s:out std_logic_vector(3 downto 0);
cout: out std_logic);
end subber4;
architecture one of subber4 is
signal cout0,cout1,cout2: std_logic;
begin
u1: subber1 port map(a(0),b(0),cin,s(0),cout0); u2: subber1 port map(a(1),b(1),cout0,s(1),cout1); u3: subber1 port map(a(2),b(2),cout1,s(2),cout2); u4: subber1 port map(a(3),b(3),cout2,s(3),cout); end one;
程序包：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; PACKAGE my_pkg IS
Component subber1
port(a,b:in std_logic;
cin: in std_logic;
s:out std_logic;
cout: out std_logic);
END Component;
Component subber4
port(a,b:in std_logic_vector(3 downto 0);
cin: in std_logic;
s:out std_logic_vector(3 downto 0);
cout: out std_logic);
END Component;
end my_pkg;
16位减法器：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE WORK.my_pkg.all;
entity subber16 is
port( a,b:in std_logic_vector(15 downto 0);
cin: in std_logic;
s:out std_logic_vector(15 downto 0);
cout: out std_logic);
end subber16;
architecture one of subber16 is
signal cout0,cout1,cout2: std_logic;
begin
u1: subber4 port map(a(3 downto 0),b(3 downto 0),cin,s(3 downto 0),cout0);
u2: subber4 port map(a(7 downto 4),b(7 downto 4),cout0,s(7 downto 4),cout1);
u3: subber4 port map(a(11 downto 8),b(11 downto 8),cout1,s(11 downto 8),cout2);
u4: subber4 port map(a(15 downto 12),b(15 downto 12),cout2,s(15 downto 12),cout); end one;
【D触发器】
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; ENTITY dchufaqi IS
PORT(clk,d,clr:IN STD_LOGIC;
q:OUT STD_LOGIC);
END dchufaqi;
ARCHITECTURE example2 OF dchufaqi IS BEGIN
process( clk,d,clr)
begin
if (clr='0') then q<='0';
elsif (clk'event and clk='1') then
q<=d;
end if;
end process;
END example2;
【4位移位寄存器】
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY shifter IS
PORT(din,clk: IN bit;
dout : out bit); END shifter;
ARCHITECTURE a OF shifter IS
component dff
port(d,clk: in bit;
q: out bit);
end component dff;
signal d: bit_vector(0 to 4);
BEGIN
d(0)<=din;
u1:dff port map(d(0),clk,d(1));
u2:dff port map(d(1),clk,d(2));
u3:dff port map(d=>d(2),clk=>clk,q=>d(3));
u4:dff port map(d=>d(3),clk=>clk,q=>d(4));
dout<=d(4);
END a;
【8D锁存器】
（1）LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY latch1 IS --1位锁存器的设计
PORT ( d :IN STD_LOGIC;
ena :IN STD_LOGIC;
q :OUT STD_LOGIC);
END latch1;
ARCHITECTURE example4 OF latch1 IS
SIGNAL sig_save:STD_LOGIC:=…0‟;
BEGIN
PROCESS (d,ena)
BEGIN
IF ena='1' THEN
Sig_save<=D;
END IF;
Q<=sig_save;
END PROCESS;
END example4;
（2）LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
PACKAGE my_pkg IS
COMPONENT latch1 --latch1入程序包
PORT ( d :IN STD_LOGIC;
ena :IN STD_LOGIC;
q :OUT STD_LOGIC);
END COMPONENT;
END my_pkg;
（3）LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE WORK.my_pkg.ALL;
ENTITY ct74373 IS --8D锁存器的设计PORT (d: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
oen, g: IN STD_LOGIC;
q: OUT STD_LOGIC _VECTOR(7 DOWNTO 0));
END ct74373;
ARCHITECTURE one OF ct74373 IS
SIGNAL sigsave: STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
Gelatch: for n in 0 to 7 GENERATE
Latchx: latch1 port map(d(n),g,sigsave(n));
END GENERA TE;
Q<=sig save when oen=…0‟ else
“ZZZZZZZZ”;
END one;
【根据逻辑表达式编程等等，如F= ABC+(D+E)+GH】LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
entity cytest is
port(a,b,c,d,e,g,h: in std_logic;
f: out std_logic);
end cytest;
architecture one of cytest is
signal t1, t2,t3: std_logic;
begin
t1<= a and b and c;
t2<= d or e;
t3<= g and h;
f<= t1 or t2 or t3;
end one;
【六进制计数器】
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE. STD_LOGIC_UNSIGNED.ALL;
ENTITY CNT6 IS
PORT (CLK, CLRN, ENA, LDN: IN STD_LOGIC;
D: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
Q: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
COUT: OUT STD_LOGIC);
END CNT6;
ARCHITECTURE ONE OF CNT6 IS
SIGNAL CI: STD_LOGIC_VECTOR(3 DOWNTO 0):="0000"; BEGIN
PROCESS(CLK, CLRN, ENA, LDN,CI)
BEGIN
IF CLRN='0' THEN CI<="0000";
ELSIF CLK'EVENT AND CLK='1' THEN
IF LDN='0' THEN CI<=D;
ELSIF ENA='1' THEN
IF CI<5 THEN CI<=CI+1;
ELSE CI<="0000";
END IF;
END IF;
END IF;
Q<=CI;
END PROCESS;
COUT<= CI(0) AND CI(2);
END ONE;
【有单个四选一，设计双四选一数据选择器】
（1）LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY mux4_1 IS
PORT(a,b,c,d:IN STD_LOGIC;
s:IN STD_LOGIC_vector(1 downto 0);
z:OUT STD_LOGIC);
END mux4_1;
ARCHITECTURE example3 OF mux4_1 IS
BEGIN
PROCESS(a,b,c,d,s)
BEGIN
CASE s IS
WHEN "00" => z <= a;
WHEN "01" => z <= b;
WHEN "10" => z <= c;
WHEN "11" => z <= d;
WHEN OTHERS => z <= 'X';
END CASE;
END PROCESS;
END example3;
（2）LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
PACKAGE mypkg IS
COMPONENT mux4_1
PORT(a,b,c,d:IN STD_LOGIC;
s:IN STD_LOGIC_vector(1 downto 0);
z:OUT STD_LOGIC);
END COMPONENT;
END mypkg;
（3）LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE WORK.mypkg.ALL;
ENTITY doublemux41 IS
PORT(aa,bb,cc,dd:IN STD_LOGIC_VECTOR(1 DOWNTO 0);
sel:IN STD_LOGIC_VECTOR(1 DOWNTO 0);
q:OUT STD_LOGIC_VECTOR(1 DOWNTO 0));
END doublemux41;
ARCHITECTURE one OF doublemux41 IS
BEGIN
gemux41: for n in 0 to 1 generate
ux: mux4_1 port map(aa(n),bb(n),cc(n),dd(n),sel,q(n));
end generate;
end one;
updowncnt8
library ieee;
use ieee.std_logic_1164.all;
entity updowncnt8 is
port(clr,clk,ena,load,updown:in std_logic;
d: in integer range 0 to 255;
cout:out std_logic;
q:buffer integer range 0 to 255); end updowncnt8;
architecture one of updowncnt8 is
begin
process (clk,ena,clr,d,load,updown)
begin
if clr='0' then
q<= 0;
elsif clk'event and clk='1' then if load ='1' then
q<=d;
elsif ena='1' then
if updown='0'then q<=q-1;
if q = 0 then cout <='0'; end if;
else q<= q+1;
if q =255 then cout <='1';
else cout <='0'; end if ;
end if;
end if;
end if;
end process;
end one;。