max335
冷热源工程课程设计
《冷热源工程》课程设计计算书题目：姓名：学院：专业：班级：学号：指导教师：2011年7月日目录1.设计原始资料 (2)2.确定冷源方案 (3)2.1方案一 (3)2.2方案二 (4)2.3方案三 (5)2.4方案四 (6)2.5 技术性分析............................................................ . (7)2.6经济性分析 (8)3. 分水器和集水器的选择 (17)3.1分水器和集水器的构造和用途. (17)3.2分水器和集水器的尺寸 (17)3.2.1分水器的选型计算 (17)3.2.2集水器的选型计算 (18)4. 膨胀水箱配置与计算 (16)4.1膨胀水箱的容积计算 (16)4.2膨胀水箱的选型 (16)5.制冷机房水系统设计计算 (9)5.1 冷冻水系统选型和计算 (9)5.1.1冷冻水泵的选型和计算 (9)5.1.1.1水泵流量和扬程的确定 (9)5.1.1.2 水泵型号的确定 (11)5.2 冷却水系统的选型和计算 (12)5.2.1冷却塔的选型 (12)5.2.2冷却水泵的选型计算 (13)6.参考资料 (19)7.个人小结 (20)设计题目嘉兴市百联服饰城制冷机房设计二、原始资料1、空调冷负荷：为：0.8MW（空调总面积6500m2）2、当地可用的能源情况：电：价格：2.5元/度天然气：价格：2.5元/m3；热值：33.45MJ/m3；蒸汽：价格：80元/吨；蒸汽压力为：0.8MPa燃油：价格：6.76元/升；低位发热量均为：42840kJ/kg3、冷冻机房外冷冻水管网总阻力为：0.15 MPa4、土建资料制冷机房建筑平面图（见附图），其中水冷式冷水机组冷却塔高度为：10 m2、确定冷源方案制冷量：0.8 MW*1.2=0.96 MW=960 KW机组的报价按照活塞式7角l 螺杆和离心按照8角l 溴化锂按照九角l2.1方案一：采用30HR 系列水冷式半封闭式普通型活塞式冷水机组表1 30HR-195半封闭式活塞式冷水机组性能参数1）固定费用设备初投资：2⨯35=70（万元） 安装费用：25%⨯70=17.5 (万元) 系统总投资费用L=70+17.5=87.5 (万元) 银行年利率i =5.94% 使用年限n=15年1)1()1(1-++⨯=n ni i i L L =151.08万元 式中：1L —每年系统折旧费用L —系统总投资费用，包括设备初投资和安装费用i —银行年利率2）年度使用费用型号 30HR-195 制冷量(KW)580 台数 2 单价(万元） 35 电机功率（KW)150 冷冻水水量(M3/h) 100 压降(Kpa)36 冷却水水量(M3/h) 125 压降(Kpa)93设备额定供冷功率为150KW ，台数2台，电费2.5元/度，供冷月为6-9月份，按照每天24小时供冷计算年度运行费用=单台供冷功率⨯台数⨯时间⨯电费=150⨯2⨯122⨯24⨯2.5=219.6万元3)设备年度费用设备年度费用=固定费用+年度使用费用=151.08+219.6=370.68万元2.2方案二: 采用SXZ 系列双效蒸汽型溴化锂吸收式冷水机组表2 SXZ-60L.M.H 双效蒸汽型溴化锂吸收式冷水机组性能参数型号 SXZ-60L.M.H制冷量(KW) 580 台数 2 单价(万元） 45 蒸汽耗量（Kg/h) 780 冷冻水 水量(M3/h) 100 压降(Kpa) 80 接管直径（DN)125冷却水 水量(M3/h) 165 压降(Kpa)120接管直径（DN)1501）固定费用设备初投资：2⨯45=90（万元） 安装费用：25%⨯90=22.5 (万元) 系统总投资费用L=90+22.5=112.5 (万元) 银行年利率i =5.94% 使用年限n=15年1)1()1(1-++⨯=n ni i i L L =194.24万元2）年度使用费用单台设备蒸汽耗量为780kg/h，台数2台，蒸汽价格为80元/吨，供冷月为6-9月份，按照每天24小时供冷计算年度运行费用=蒸汽耗量⨯台数⨯时间⨯单价=0.78⨯2⨯80⨯122⨯24=36.54万元3）设备年度费用设备年度费用=固定费用+年度使用费用=36.54+194.24=230.78万元2.3方案三：采用BZ-VI系列燃油型溴化锂吸收式冷水机组表3 BZ-VI50燃油型溴化锂冷水机组性能参数型号BZ-VI50制冷量(KW) 581台数 2单价(万元）45.07轻油耗量（Kg/h) 45低位热值（KJ/Kg) 43054冷冻水水量(M3/h) 100 压降(Kpa) 120 接管直径（DN) 125冷却水水量(M3/h) 163 压降(Kpa) 120 接管直径（DN) 1501）固定费用设备初投资：2⨯45.07=90.14（万元）安装费用：25%⨯90.14=22.54(万元)系统总投资费用L=90.14+22.54=112.68 (万元) 银行年利率i=5.94%使用年限n=15年1)1()1(1-++⨯=nni i i L L =194.55万元 2）年度使用费用单台设备轻油耗量为45kg/h ，台数2台，轻油密度为0.84公斤/升，低位发热量为42840KJ/Kg,轻油价格为6.76元/升，供冷月为6-9月份，按照每天24小时供冷计算年度运行费用=轻油耗量⨯台数⨯时间⨯单价=2⨯122⨯24⨯84.04284043054101⨯⨯⨯6.76=213.13万元3）设备年度费用设备年度费用=固定费用+年度使用费用=213.13+194.55=407.68万元2.4方案四：采用BZ-VI 系列燃气型溴化锂吸收式冷水机组表3 BZ-VI50燃油型溴化锂冷水机组性能参数 型号 BZ-VI50 制冷量(KW) 581 台数 2 单价(万元） 45.07 天然气耗量（Nm3/h) 43 低位热值（KJ/Kg) 46000 冷冻水 水量(M3/h) 100 压降(Kpa) 120 接管直径（DN)125冷却水 水量(M3/h) 163 压降(Kpa) 120 接管直径（DN)1501）固定费用设备初投资：2⨯45.07=90.14（万元） 安装费用：25%⨯90.14=22.54(万元)系统总投资费用L=90.14+22.54=112.68 (万元)银行年利率i =5.94% 使用年限n=15年1)1()1(1-++⨯=nni i i L L =194.55万元 2）年度使用费用单台设备天然气耗量为43Nm3/h ，台数2台，天然气价格为2.5元/m3，热值为33.45MJ/m3,供冷月为6-9月份，按照每天24小时供冷计算 年度运行费用=轻油耗量⨯台数⨯时间⨯单价=2⨯122⨯24⨯334504600093⨯⨯2.5=86.57万元3）设备年度费用设备年度费用=固定费用+年度使用费用=194.55+86.57=281.12万元2.5 技术性分析(一)活塞式冷水机组 (1) 优点：a.用材简单，可用一般金属材料，加工容易，造价低；b.系统装置简单，润滑容易，不需要排气装置；c.采用多机头，高速多缸，性能可得到改善；d.可提供5到12℃左右的冷水，适合于负荷比较分散的建筑群以及制冷量小于580KW 的中小型空调系统；e.属于有极调节。
MAXIM公司部分IC芯片应用简介(续一)
MAXIM公司部分IC芯片应用简介(续一)
王淑霞
【期刊名称】《集成电路应用》
【年(卷),期】2001(000)005
【摘要】7 内含精密电阻网络的单8通道、双4通道校准多路器芯片——MAX4539/MAX4540 单8通道的MAX4539和双4通道的MAX4540是一种具有校准功能的多路转换开关(校准多路器),适用于系统自检及精密型ADC。
它们内置的精密电阻分压网络能够提供精确的V+/2、5/8(V+-V-)、15V_(REF/)4096和4081V_(REF/)/4096(其中V_(REF)为外接基准电压)参考电压。
【总页数】3页(P78-79,83)
【作者】王淑霞
【作者单位】胶南市大场西柳沟村电子开发部,266414
【正文语种】中文
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AM335x 处理器 SDK RTOS 板库端口和启动说明书
Board Porting\Bring up using Processor SDK RTOS for AM335xProcessor SDK RTOS component known as board library consolidates all the board-specific information so that all the modifications made when moving to a new custom platform using the SOC can be made in the source of this library.There are three different components in PRSDK that help in porting and bring up of a custom board:∙Board library updatesa.PLL Clocking and PRCMb.Pin mux Updatec.DDR Configurationd.Peripheral instances updates∙Diagnostics tests∙Boot loader updatesBoard Library Updates in Processor SDK RTOS:PLL ClockingThere are two places where the device PLL configurations are performed when using Processor SDK RTOS and CCS.Debug environment:Debug environment refers to development setup where code is debugged using JTAG emulator on the SOC. The PRSDK software relies on the GEL file that is part of the target configuration to setup the clocks and the DDR for the device. The CCS GEL file for AM335x platforms is located in the CCS package at the location ccsv7\ccs_base\emulation\boards\<boardName>For example for beagle bone black, the files can be found atccsv7\ccs_base\emulation\boards\beaglebone\gelThe GEL is the first piece of software that should be brought up on a custom board.Production environment:Production environment refers to the setup when the base application is booted from a boot media like a flash memory or host interface. In this environment, the bootloader sets performs all the SOC and board initialization and copies the application from flash memory to the device memory.The clock setup in the bootloader code can be located atpdk_am335x_x_x_x\packages\ti\starterware\bootloader\src\am335xUsers can choose to use the platform clocking similar to one of TI reference platforms or can modify them as per their application requirements. By default the PLL settings are setup for OPP_NOM settings (MPU= 600 MHz.)TI provides Clock Tree tool to allow users to simulate the clocking on the SOC. For quick reference of the multiplier and divider settings to change the PLL setting is provided in the spreadsheetAM335x_DPLL_CALCv3.xlsx.After modifying the clocking in the bootloader, users need to rebuild the bootloader using instructions provided in Processor_SDK_RTOS_BOOT_AM335x/AM437xPRCM Modules Enable:PRCM Module Enable is required to turn on the power domain and the clocking to each of the modules on the SOC. The PRCM Enable calls to enable each module are made from the functionBoard_moduleClockInit which is found in the location.pdk_am335x_1_0_9\packages\ti\board\src\bbbAM335x\bbbAM335x.cCheck every instance and peripheral required in the application platform and enable the module in the board library.For example to use three UARTs 0, 1 and 4, ensure that you have the following code as part of the board library setup:/* UART */status = PRCMModuleEnable(CHIPDB_MOD_ID_UART, 0U, 0U);status = PRCMModuleEnable(CHIPDB_MOD_ID_UART, 1U, 0U);status = PRCMModuleEnable(CHIPDB_MOD_ID_UART, 4U, 0U);Note: PRCMEnable function is defined in pdk_am335x_1_0_9\packages\ti\starterware\soc\am335x Pinmux updates in the Board library:Generating a New PinMux Configuration Using the PinMux Utility: This procedure uses the cloud-based pinmux utilityNavigate to ${PDK_INSTALL_DIR}\packages\ti\starterware\tools\pinmux_config\am335x and Load beaglebone_black_configAdd and remove peripheral instances and select the appropriate use cases required for development based on the application platform requirements and resolve all conflicts.Refer Pin_Mux_Utility_for_ARM_MPU_ProcessorsPost Processing steps:1.Change the Category filter to starterware and download the pinmux files am335x_pimnmux.hand am335x_pinmux_data.c2.At the bottom of am335x_pinmux.h change extern pinmuxBoardCfg_t gAM335xPinmuxData[];to extern pinmuxBoardCfg_t gBbbPinmuxData[];3.Change am335x_pinmux_data.c to am335x_beagleboneblack_pinmux_data.c.4.Change gAM335xPinmuxData to gBbbPinmuxData at the end of the file in file5.am335x_beagleboneblack_pinmux_data.c.Replace the existing files with the new files and rebuild the board library using the instructions in the section Rebuilding board Library in Processor SDK RTOS:Updating DDR settings:Similar to clock and PLL settings, DDR initialization is configured in the Debug environment through GEL files and in production environment using bootloader source files.TI provides AM335x_EMIF_Configuration_tips which contains a spreadsheet to enter the timing from the DDR datasheet to compute the EMIF timing number required to initialize DDR.We strongly recommend changing the value and testing using GEL files before using them in the bootloader software. For Sanity test, you can perform read/write tests using CCS Memory Browser or run the diagnostic memory read/write test that we provide in diagnostics package here:PDK_INSTALL_PATH\packages\ti\board\diag\memOnce the DDR timings have been confirmed, you can use the settings in the file:PDK_INSTALL_PATH \packages\ti\starterware\bootloader\src\am335x\sbl_am335x_platform_ddr.c Peripheral initialization:The board library is responsible for most of the SOC initialization but it also setup some board level components such as ethernet PHY and debug UART and I2C for reading board ID from EEPROM. All of the other peripheral instances and initialization needs to be done from the application level.For example for beagleboneblack, the peripheral initialization are performed from the source filepdk_am335x_1_0_9\packages\ti\board\src\bbbAM335x\bbbAM335x_lld_init.cThe debug UART instance, I2C Addresses are set using the file board_cfg.h found under:pdk_am335x_1_0_9\packages\ti\board\src\bbbAM335x\includeDefault UART instance is set to 0 in the board library. The Board initialization will configure the UART instance 0 to send binary log data to serial console using the Board_UARTInit function. If you wish to use more UART instances then we recommend linking in the UART driver in the application and using UART_open() and UART_stdioInit API calls from the application.Each peripheral driver in the Processor SDK RTOS has a SOC configuration that provides the interrupt numbers, base address, EDMA channels which can be updated using the file <peripheral>_soc.c file. This is used as default setup for initializing the driver instance. It can be overridden from the application using peripheral_getSOCInitCfg() and peripheral_setSOCInitCfg()For Example: All instances of UART for AM335x have been mapped in the filepdk_am335x_1_0_9\packages\ti\drv\uart\soc\am335x\UART_soc.cSystem integrators need to ensure that no interrupt numbers and EDMA resource conflicts exist in the SOC configuration for all drivers used in the system.To exercise three UARTs in the system, users can use the following code://Setup Debug UARTboardCfg = BOARD_INIT_PINMUX_CONFIG |BOARD_INIT_MODULE_CLOCK |BOARD_INIT_UART_STDIO;Board_init(boardCfg);// Open Additional UART Instances:/* UART SoC init configuration */UART_initConfig(false);/* Initialize the default configuration params. */UART_Params_init(&uartParams);// Open UART Instance 1uartTestInstance =1;uart1 = UART_open(uartTestInstance, &uartParams);//Open UART Instance 4uartTestInstance = 4;uart4 = UART_open(uartTestInstance, &uartParams);BoardID Detect:TI supports multiple evaluation and reference platforms for AM335x hence the hardware platforms are populated with an EEPROM which contains information that identifies the hardware and its revision. The board library and software components read the boardID and initialize the platform based on the boardID. The BoardID_detect function can be found in the source in the file bbbAM335x_info.c in the board library and board_am335x.c in the bootloader source at:<PDK_INSTALL_PATH>\packages\ti\starterware\board\am335xRebuilding board Library in Processor SDK RTOS:While Creating a new folder for the custom board is an option users can explore, TI recommends that users make there changes in existing board package using either bbbAM335x, evmAM335x oriceAM335x folder to avoid spending additional effort to modify the build files for including the customBord.Once all the update to the board library are completed, the board library can be updated using the following instructions.Instructions to rebuild board library:Setup Processor SDK build environment before following steps provided below.cd pdk_am335x_1_0_9\packagesgmake board_libFor a specific board users are required to provide the LIMIT_BOARDS argument.LIMIT_BOARDS : evmAM335x icev2AM335x iceAMIC110 bbbAM335x skAM335xFor Example for beagleboneblack, users can use the following build option:gmake board_lib LIMIT_BOARDS=bbbAM335xDiagnostics:After the board library is built, we highly recommend that you create a diagnostics package similar to one provided in board library to test different interfaces functionally during board bring up.The diagnostics package can be located at pdk_am335x_1_0_9\packages\ti\board\diag. These are simple bare-metal tests that use peripheral drivers to help functionally validate the pins and interfaces.Documentation for all available diagnostic tests is provided here:/index.php/Processor_SDK_RTOS_DIAGBootloader in Processor SDK RTOS:As part of the production flow, users are required to develop/port flashing and booting utilities so the application can be launched on the custom board with JTAG. TI provides a bootloader mechanism where the ROM bootloader loads a secondary bootloader on the onchip memory that initializes the SOC and DDR and then copies the application into DDR memory.The boot process and flashing tools have been described in detail in the following article that is part of processor SDK RTOS Software developer`s guide:/index.php/Processor_SDK_RTOS_BOOT_AM335x/AM437x#Building_the_B ootloader。
MAX3490摘出资料(部分中文)
MAX3488, MAX3490，MAX3491 功能，全双工通信，而 MAX3483, MAX3485, MAX3486是专为半双工通信。
单一的电源供应，没有电荷注入；具有+ 5V 逻辑电源互操作；最大偏斜为 8ns ； 2ns 低电流掉电模式；共模输入电压范围：—7〜+ 12V ,总线上允许多达 32个收发器；全双工和半双工版本；具有电流限制和热 关机驱动器过载保护驱动器具有短路电流限制和对功耗过大的保护，热关断电路，驱动器输岀置于高阻抗状态。
接收器输入具 有故障安全功能，保证逻辑高输岀，如果两个输入端开路。
选择MAX3490做RS-422,下图为 MAX3490引脚图1 ——VCC2―― RO 接收器输出 3―― DI 驱动器输入 4 ——GND 5 ---- Y 同相驱动器输出 6 ---- Z 反相驱动器输出 7 ---- B反相接收器输入8——A 同相接收器输入保证数据传输速率（Mbps ） 10电源电压（V ） to 半/全双工 全双工摆率限制 无 驱动器/接收器使 无 关断电流（NA ）关断时无引脚数8频率大，高频谐波明显MAX3490没有接收器发送器使能，控制逻辑如下图Dences 宙Rhouf Receiver/Driver Enable（MAX3488/MAX349a}T^ble 3. Transmitting T^able 4. ReceivingMAX3490 （无RE 、DE 引脚）绝对最大额定值如下图:IN^UTOUTPUTSDI zY 1 D 1 □1INPUTSOUTPUTA. 6 RO *D.2V1 <-a.2v0 Inputs Open1□IP/SOE L叵叵DABSOLUTE MAXIMUM RATINGSS U P P 卜F \ 01 ^3 9 e l\/ kill ■ ■ ■ ■ ■■!■■■■■■ iri ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■■ ■ ■ ■ ■ ■ i ■ ■ ■ r ■ ■ ■ ■ ■ ■ ■Control IrpiJ ValLage (RE, D£) ............... .......... ............... -0.3V ta 7V□rtvsr Inpul Voltage (6l).............. .......... .......... ............... -0.3Vtn 7VOnvar Output VcItaQ* (A,気V, ZX - ......................... -7J5V to12.SVftccer^CF Input VaKagc |A, B) . -7.5V to )2 5VReceiver Ojtput Voltage (RO) . . -O.3Vto (Vcc * 0 3V)Gontinucus Power g$ipmTk?n (T R= +70芒|各Pin Pi/Mc DIP 忖申rate 9 09mWU above +70© 72?mW8-Pin SO (<1HW 5 aarrrtVy «bove +7C P C), 471mW14-Rn Plastic DlP(de<m© 10mW fl C above +70忙》... HOOtrMf14-Rn SO (deia1^ fl.SSmW.^C abaw +70*C> __________ UUJllMfOperating Temperalur?MAXU C .............. ......... *........ ... ..................... -.Ot：to +7[TCMAX3d_ _E__”…lh.. “一,. ,.H.…““-“,-H.⑷乜B +85\：Storage Temperafur? Range lo +16[yCbead Tempeiature [wldering lOlMC)..................................... +XD*CMAX3490驱动器的开关特性如下图:DRIVER SWITCHING CHARACTERISTICS-MAX3465h MAX14$0, and MAX3491ri^E：» 3.3M a T*w *25*CJPARAMtFER CONCilTICNS m TVP MA 9(UNITSDrrwf OHtreftfiii OdljMjt Del叩g■ Sdll, Figure 7 122M mDrvcr Wfe-oEiii Ckrlp ui T M7»C r Time hno良L * fiOtl, Flpm 71&25mEtr p临他n M■丫LCfflMCHHiah Lrvtl IpiLM R L * 37(1. F4l/*a T2235m轉、ion Delay Hl0hi&-Lew Leveli IpML R. - ZTflFiflWWE■Jr22 35tp L n - iPHitl □越g*曲m Dtt&Ff吕的却iH^ie S- IPDS R.fc• 27n, FipL<eS E mDRIVER OUTPUT ENABLEJOIS^BLE TIMES {IWS-iflS'IMLW3-431 聞切Dmw CXJtput tnable r me I Q L OW LE^el tfZL Ri= 110SL f^FLFa 10 45 M OEDiwci" OulpiJl EiwN? Trne tg High Len el S FZH Ri ■ 110(1 钿ure $ 45raDrw CMp讥04»^le Time tom Migih Level fi t* 11(X1. F»flL*t940 to POriw D・*l・ Tim from LwLwi tpLE R L* 11IMI. i&40 BO mDTM< dip Lit Errtb^A Tiffii Au墟电叭旳Lx L#v4l tm Rl ■匚如i 10<8W gm 他Qrta&r ErrtBifi Titre frw 电靜©询|a H(；h 4PCH R; - 1inni FigiLiraS®o r»MAX3490CPA(TCto +70'Q8 Ptasttc DIPMAX349OCSA(TCt口+7D B C\8 SOMAX3490C/D crcto+70e c \Dice'MAX349OEPA-4(rc to +85X8 Plastic DIPMAX349OESA■40X10+9598 SOMAX3490引脚配置与典型工作电路，如下图|l巒4e 2 MAA J4ML JWAJC3啲Pin 8 两#挪询事呵Typ"C^ uftMOTE AEANODE O 8LXF砂*师悶ZKSQW诂沖盟F训卜皿咻斥$钵自Ncrv^OfU MAX3490封装尺寸L -15^ Plastic DIPPLASTIC DU AL-IN-LINE PACKAGE(0.300 in.)DIM [HOMES MLLlWETESS MIN MAA MIN MAXA a 200A1ocn&-■"20 12& C 175 3104-iS *3 0D5& Q0» 1.402W0.01S a 022 041 OKoo^ 1 MC DQOB0 0120200 30 &1D0Q&0 09001328E0.300 0 925 A2A E10咖0 310dia7VT e OJOO■■eA D.3H)■*tB Q4P0 10 16 L 0 IU a iso 2923J1 PINSMCHES MJJME1TER3-MN NUM MNI MAXa 0 3430 w BM 891 0140^3513-6719-43 ET lir o.-«Q -B51: 911&.43 010MBS 0i1522 4B 23.24 020 101S104535742454□24 1 14H2B52S DE37 13。
MAX335 CMOS 8-Channel Analog Switch with Serial Di
General DescriptionThe MAX335 analog switch with serial digital interface offers eight separately controlled single-pole-single-throw (SPST) switches. All switches conduct equally in either direction, and on-resistance (100Ω) is constant over the analog signal range.These CMOS switches can operate continuously with power supplies ranging from ±4.5V to ±20V and handle rail-to-rail analog signals. Upon power-up, all switches are off, and the internal serial and parallel shift registers are reset to zero. The MAX335 is equivalent to two DG211 quad switches but controlled by a serial interface.The interface is compatible with the Motorola SPI interface standard. Functioning as a shift register, this serial interface allows data (at DIN) to be locked in synchronous with the rising edge of clock (SCLK). The shift register’s output (DOUT) enables several MAX335s to be daisy chained. Applications●Serial Data Acquisition and Process Control●Avionics●Signal Routing●Networking Features●8 Separately Controlled SPST Switches ●SPI-Compatible Serial Interface●Accepts ±15V Analog Swings●Multiple Devices Can Be Daisy-Chained19-0220; Rev 4; 7/17*Contact factory for dice specifications.**Contact factory for availability and processing to MIL-STD-883.PART TEMP RANGE PIN-PACKAGEMAX335CNG 0°C to +70°C24 Narrow Plastic DIP MAX335CWG 0°C to +70°C24 Wide SOMAX335C/D 0°C to +70°C Dice*MAX335ENG -40°C to +85°C24 Narrow Plastic DIP MAX335EUG -40°C to +85°C24 TSSOPMAX335EWG -40°C to +85°C24 Wide SOMAX335MRG -55°C to +125°C24 Narrow CERDIP** Ordering InformationPin ConfigurationMAX335+241232223214205196187178169151014111312SCLKV+DINGNDNO0COM0NO1COM1NO2COM2NO3COM3CSTOP VIEWDIP/SOVLDOUTV-NO7COM7NO6COM6NO5COM5NO4COM4Voltages Referenced to V-V+ ......................................................................................44V GND ...................................................................................25V V L ................................................(GND - 0.3V) to (V+ + 0.3V) SCLK, CS , DIN, DOUT, NO_, COM_ ...........V- -2V to V+ +2Vor 30mA, whichever occurs firstContinuous Current (any terminal) .....................................30mA Peak Current, NO or COM(pulsed at 1ms, 10% duty cycle MAX) ...........................00mA Continuous Power Dissipation (T A = +70°C) (Note 1) Narrow Plastic DIP(derate 13.33mW/°C above +70°C) ..........................1067mW Wide SO (derate 11.76mW/°C above +70°C) .............941mW Narrow CERDIP (derate 12.50mW/°C above +70°C) ...1000mW TSSOP (derate 12.2mW/°C above +70°C) ........................30mA Operating Temperature RangesMAX335C_ _ ..........................................................0°C to +70°C MAX335E_ _ ......................................................-40°C to +85°C MAX335MRG ...................................................-55°C to +125°C Storage Temperature Range ............................-65°C to +160°C Lead Temperature (soldering, 10sec) .............................+300°C(V L = +5V ±10%, V+ = 15V, V- = -15V, T A = T MIN to T MAX , unless otherwise noted. Typical values are at T A = +25°C.)Note 1: All leads are soldered or welded to PC boards.PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSSWITCHAnalog Signal Range V ANALOG T A = T MIN to T MAX -1515V On-ResistanceR ONV COM = ±10V, I NO = 1mA T A = +25°C 100150Ω200NO Off-Leakage CurrentI NO(OFF)V COM = -14V, V NO = +14V T A = +25°C -10.0021nA -2020V COM = -14V, V NO = +14V T A = +25°C -10.0021-2020COM Off-Leakage CurrentI COM(OFF)V COM = -14V, V NO = +14V T A = +25°C -10.0021nA -2020V COM = -14V, V NO = +14V T A = +25°C -10.0021-2020COM On-Leakage CurrentI COM(ON)V COM = V NO = +14VT A = +25°C -20.012nA -2040V COM = V NO = -14VT A = +25°C-20.012-2040DIGITAL I/ODIN, SCLK, CS Input Logic Threshold HighV IH V L = +5V 2.4V V L = +15V 11DIN, SCLK, CS Input Logic Threshold LowV IL V L = +5V 0.8V V L = +15V3DIN, SCLK, CS Input Current Threshold HighI INH V DIN , V SCLK , V CS = 2.4V-10.031µA V L = +15V, V DIN , V SCLK , V CS = 11V -10.031DIN, SCLK, CS Input Current Threshold Low I INL V DIN , V SCLK , V CS = 0.8V-10.031µA V L = +15V, V DIN , V SCLK , V CS = 3V -10.031DOUT Output Voltage Logic HighV DOUTI DOUT = 0.8mA3.5V LVAbsolute Maximum RatingsStresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.Electrical Characteristics(V L = +5V ±10%, V+ = 15V, V- = -15V, T A = T MIN to T MAX , unless otherwise noted. Typical values are at T A = +25°C.)Note 2: When V L falls below this voltage, all switches are set off and the internal shift register is cleared (all zero).Note 3: Guaranteed, not production tested.PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSDIGITAL I/ODOUT Output Voltage Logic Low V DOUT I DOUT = -1.6mA 0.4V V L RESET Voltage V LL (Note 2)0.8V V L RESET Voltage V LH T A = +25°C 2.4V SCLK Input HysteresisSCLK HYSTT A = +25°C 100mVSWITCH DYNAMIC CHARACTERISTICS Turn-On Timet ON From rising-edge of CST A = +25°C 200400ns500Turn-Off Time t OFF From rising-edge of CS T A = +25°C 90400ns 500NO Off-Capacitance C NO(OFF)V S = GND, f = 1MHz T A = +25°C 2pF COM Off-Capacitance C COM(OFF)V S = GND, f = 1MHz T A = +25°C 2pF Channel On-Capacitance C COM(ON)V D = V S = GND, f = 1MHzT A = +25°C 8pF Off IsolationOIRR R L = 100Ω, C L = 15pF, V S = 1V RMS , f = 100kHz T A = +25°C 90dB Channel-to-Channel Crosstalk CCRR R L = 50Ω, C L = 15pF, V S = 1V RMS , f = 100kHzT A = +25°C100dB Break-Before-Make Delay T BBM 1525ns Clock Feedthrough at S, D (Note 3)ESCLKD LOAD = S LOAD = 75Ω, measured at S and DT A = +25°C100nV-secPOWER SUPPLIESPower-Supply Voltage Range V+/V-±4.5±20V V L Power-Supply Voltage RangeV L 4.5V+V V+ Supply CurrentI+DIN = CS = SCLK = 0V/5VT A = +25°C 150300µA500V- Supply Current I-DIN = CS = SCLK = 0V/5VT A = +25°C 0.0110µA10V L Supply Current I LDIN = CS = SCLK = 0V/5VT A = +25°C50100µA200Electrical Characteristics (continued)(V L = +5V ±10%, V+ = 15V, V- = -15V, T A = T MIN to T MAX , unless otherwise noted.)Note 4: This specification guarantees that data at D OUT never appears before SCLK’s falling edge.PARAMETERSYMBOL CONDITIONSMIN TYPMAXUNITS SCLK Maximum Frequency f SCLK 2.1MHz Cycle Time t CH + t CL 480ns CS Lead Time t CSS 240ns CS Lag Time t CSH2240ns SCLK High Time t CH 190ns SCLK Low Time t CL 190ns Data-Setup Time t DS 200ns Data-Hold Time t DH 0ns DOUT Data Valid After Falling SCLKt DO50% of SCLK to 10% of DOUT CL = 10pF T A = +25°C240ns 400DOUT Data-Hold Time After Rising SCLK (Note 4)C L = 10pFns Rise Time of DOUT (Note 3)20% V L to 70% V L , C L = 10pF 100ns Allowable Rise Time at DIN, SCLK, CS (Note 3)20% V L to 70% V L , C L = 10pF 2µs Fall Time of DOUT (Note 3)70% V L to 20% V L , C L = 10pF 100ns Allowable Fall Time at DIN, SCLK, CS (Note 3)70% V L to 20% V L , C L = 10pF2µsTiming Characteristics of Serial Digital Interface (Figure 1)(V+ = +15V, V- = -15V, V L = 5V, T A = +25°C, unless otherwise noted.)Typical Operating CharacteristicsR ON vs. V COM AND POWER-SUPPLY VOLTAGEV COM (V)R O N (Ω)100-10501001502002503000-2020DATA-HOLD TIME vs.POWER-SUPPLY VOLTAGEM A X 335t o c 04SUPPLY VOLTAGE (V)D A T A -H O L D T I ME (n s )±20±15±10-40-200204060-60±5CHARGE INJECTION vs. V COMV COM (V)Q (p C )100-10-70-3503570105-105-20155-5-1520R ON vs. V COM AND TEMPERATUREV COM (V)R O N (Ω)100-10501001502002503000-2020DATA-SETUP TIME vs.POWER SUPPLYM A X 335t o c 05SUPPLY VOLTAGE (V)D A T A -SE T U P T I M E (n s )±20±15±101020304050600±5SUPPLY vs. TEMPERATUREM A X 335t o c 08TEMPERATURE (°C)I +, I -, I L (µA )+250.010.111010010000.001-55+125I+I LI-t ON, t OFF vs. V COMV COM (V)t O N , t O F F (n s )151051002003004005006000020LEAKAGE CURRENT vs.TEMPERATUREM A X 335t o c 06TEMPERATURE (°C)O N -L E A K A G E (p A )+125+250.0020.020.22202000.0002-55MINIMUM SCLK PULSE WIDTHvs. POWER SUPPLYM A X 335t o c 09SUPPLY VOLTAGE (V)S C L K (n s )±20±15±101020304050600±5Detailed DescriptionSerial Digital InterfaceBasic OperationRefer to Figure 2. The MAX335 interface can be thought of as an 8-bit shift register controlled by CS. While CS is low, input data appearing at DIN is clocked into the shift register synchronous with SCLK’s rising edge. The data is an 8-bit word, each bit controlling one of eight switches in the MAX335 (Table 1). DOUT is the output of the shift register, with data appearing synchronous with SCLK’s falling edge. Data at DOUT is simply the input data delayed by eight clock cycles.When shifting the input data, D7 is the first bit in and out of the shift register. While shifting data, the switches remain in their original configuration. When the 8 bits of data have been shifted in, CS is brought high. This updates the new switch configuration and inhibits further data from entering the shift register. Transitions at DIN and SCLK have no effect when CS is high, and DOUT holds the last bit in the shift register.The MAX335 three-wire serial interface is compatible with the SPI™ and Microwire™ standards. If interfacing with a Motorola processor serial interface, set CPOL = 0. The MAX335 is considered a slave device (Figures 2 and 3). Upon power-up, the shift register contains all zeros, and all switches are off.The latch that drives the analog switch is only updated on the rising edge of CS when SCLK is low. If SCLK is high when CS rises, the latch will not be updated until SCLK goes low. The CPOL = 1, CPHA = 1 SPI configuration does not update the latch correctly. Daisy ChainingFor a simple interface using several MAX335s, “daisy chain” the shift registers as shown in Figure 5. The CS pins of all devices are connected together, and a stream of data is shifted through the MAX335s in series. When CS is brought high, all switches are updated simultaneously. Additional shift registers may be included anywhere in series with the MAX335 data chain.Addressable Serial InterfaceWhen several serial devices are configured as slaves, addressable by the processor, DIN pins of each MAX335 are connected together (Figure 6). Address decode logic individually controls CS of each slave device. When a slave is selected, its CS is brought low, data is shifted in, and CS is brought high to latch the data. Typically, only one slave is addressed at a time. DOUT is not used. Digital FeedthroughDigital feedthrough energy measures 100nV-sec, which means that with no filtering at the signal channel, feedthrough from a sharply rising clock edge into an unfiltered switch channel can be measured at 1Vp-p for 100ns. However, even 100pF capacitance in the switch channel, when combined with the switch resistance, yields a filter that reduces this transient to 10mVp-p typical. T o reduce digital feedthrough, hysteresis (150mV typ) was added to the SCLK input so triangle or sine waves may be used.PIN NAME FUNCTION1SCLK Serial Clock Input2V+Positive Supply Voltage3DIN Serial Data Input4GND Ground5NOØSwitch 06COMØSwitch 07NO1Switch 18COM1Switch 19NO2Switch 210COM2Switch 211NO3Switch 312COM3Switch 313COM4Switch 414NO4Switch 415COM5Switch 516NO5Switch 517COM6Switch 618NO6Switch 619COM7Switch 720NO7Switch 721V-Negative Supply Voltage 22DOUT Serial Data Output23V L Logic Supply/Reset24CS Chip SelectPin DescriptionFigure 1. Timing DiagramFigure 2. Three-Wire Interface TimingTable 1. Serial-Interface Switch ProgrammingX = Don’t careFigure 3. Connections for Microwire Figure 4. Connections for SPIDATA BITSFUNCTIOND7D6D5D4D3D2D1D00X X X X X X X Switch 7 open (off)1X X X X X X X Switch 7 closed (on)X 0X X X X X X Switch 6 open X 1X X X X X X Switch 6 closed X X 0X X X X X Switch 5 open X X 1X X X X X Switch 5 closed X X X 0X X X X Switch 4 open X X X 1X X X X Switch 4 closed X X X X 0X X X Switch 3 open X X X X 1X X X Switch 3 closed X X X X X 0X X Switch 2 open X X X X X 1X X Switch 2 closed X X X X X X 0X Switch 1 open X X X X X X 1X Switch 1 closed X X X X X X X 0Switch 0 open X XXXXXX1Switch 0 closedFigure 5. Daisy-Chained ConnectionFigure 6. Addressable Serial InterfaceApplications Information8 x 1 MultiplexerTo use the MAX335 as an 8 x 1 multiplexer, tie all drains together (COM0 to COM7); the mux inputs now source each switch (NO0 to NO7). Input a single 0V to +3V pulse at DIN. As this is clocked through the register by SCLK, each switch will sequence on one at a time.4-2 Differential MultiplexerTo use the MAX335 as a 4-2 differential multiplexer, tie COM0 through COM3 together and COM4 through COM7 together. Differential inputs will be the source inputs as follows: (NO0, NO4), (NO1, NO5), (NO2, NO6), (NO3, NO7). Figure 7 shows the serial input control at DIN required to turn on two switches making a differential multiplexer.CS is held low for four clock pulses; the first pulse is clocked into the fifth switch position as the second pulse is clocked into the first switch position. CS is pulled high to update switches; then CS is pulled low, and SCLK advances pulses to S1 and S5 positions, where CS is pulled high to update, etc.SPDT SwitchesTie COM0 to NO1 so that NO0 and COM1 are now inputs and COM0/NO1 is the common output. SP is common output. Up to four SPDT switches can be made from each MAX335. Multiples of four or more can be made by daisy chaining devices. In Figure 8, DIN is a pulse train. Again, CS is held low to clock in pulses and CS is pulled high to update; CS is held low to shift pulses, then pulled high to update, etc.Reset FunctionPulsing V L below +0.8V initiates the power-up reset function. The switches are set to the off position, and the serial shift register is reset to all zeros.Power-Supply OperationThe MAX335 operates with V = ±4.5V to ±20V and V L = +5V. With V- tied to ground, the part operates with V+ = +10V to +30V.The V L supply sets TTL input compatibility at a 1.6V switching threshold. As V L is raised, the switching threshold is raised, so the part is no longer TTL compatible. The MAX335 also operates with a single power supply: V L = V+ and V- = 0V. With V L tied to V+, the V L supply cannot be used as a reset function.Figure 7. Differential Multiplexer Input ControlFigure 8. Serial-Input Control for SPDT SwitchChip TopographyTRANSISTOR COUNT: 387SUBSTRATE CONNECTED TO V+.Package InformationPackage Information (continued)Package Information (continued)REVISION NUMBER REVISIONDATEDESCRIPTIONPAGESCHANGED47/17Updated Min and Typ values of Break-Before-Make Delay inElectrical Characteristics table3Revision HistoryMaxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at .。
AM335x IBIS Model使用指南说明书
How to use the AM335x IBIS ModelsIntroductionThe AM335x External Memory Interface is a very flexible interface which can be used with LPDDR, DDR2, DDR3, and DDR3L. There are many settings available to fine-tune the signal timing on this interface. These settings include ODT options, pullups, pulldowns, slew rate, etc. IBIS modeling can be used to fine tune the set of options for a given PCB. That said, understanding the mapping between the various IBIS models and the corresponding register configuration options is critical to doing this correctly. This article is intended to help bridge that gap so that AM335x users can properly model their memory interface and program the best options in the AM335x registers. NOTE: TI does not support timing analysis with IBIS simulations. Rather, customers are encouraged to use the IBIS models for Signal Integrity (SI) analysis. As far as the timing goes, please follow the routing guidelines and length/skew matching requirements in the Data Manual.IBIS StructureEvery pin on the device is listed with a corresponding "Selector". For example:P1 DDR_DQS0 Selector_1If you then go and look at the definition of that Selector you will find all of the available models for that given I/O cell. For example:[Model Selector] Selector_1Model_1000 INPUT,1.5V,FULLTERM, 1.00*RExt,IND,5%,DIFF_VREF_FULLTERM_8MA_5PER_1P5 Model_1001 INPUT,1.5V,Half Thevenin, 1.60*RExt,IND,5%,DIFF_VREF_HALFTERM_5MA_5PER Model_1002 INPUT,1.5V,FULLTERM, 0.88*RExt,IND,5%,DIFF_VREF_FULLTERM_9MA_5PER_1P5Each of the models above corresponds to the I/O cell behavior given a specific set of configuration options. Register MappingParameters for a typical modelEach model has the following structure:ReadsModel_xyz INPUT, <voltage>, <ODT>, <Impedance>, <Temperature>, <Voltage-tolerance> WritesModel_xyz 3-STATE, <voltage>, <ODT>, <slew>, <Impedance>, <Temperature>, <Voltage-tolerance>Parameter Options Register Setting TRM Reference<voltage>DDR3L (1.35V), DDR3 (1.5V), orDDR2/LPDDR (1.8V)<ODT>Reads:NOTERM_WEAK_PU_ON,NOTERM_WEAK_PD_ON,NOTERM_WEAK_PUPD_OFF,FULLTERM, Half TheveninWrites: ODT Off DDR_PHY_CTRL_1[reg_phy_rd_local_odt]Table 7-254.DDR_PHY_CTRL_1Register FieldDescriptions<slew>fastest, fast, slow, slowest ddr_cmd0_ioctrl, ddr_cmd1_ioctrl,ddr_cmd2_ioctrl, ddr_data0_ioctrl,ddr_data1_ioctrl ["sr" fields]Table 9-7. DDR Slew Rate Control Settings<Impedance>0.67*RExt0.73*RExt0.8*RExt0.88*RExt1.00*RExt1.14*RExt1.33*RExt1.6*RExt ddr_cmd0_ioctrl, ddr_cmd1_ioctrl,ddr_cmd2_ioctrl, ddr_data0_ioctrl,ddr_data1_ioctrl ["I" fields]Table 9-8. DDRImpedance ControlSettings<Temperature>IND = -40 to 125C, 25C nominal(In IBIS Comments)<Voltage-tolerance>(Power supply tolerance, not a register)5% or 10%Additional considerations for LPDDR vs DDR2LPDDR and DDR2 are both 1.8V interfaces. However, they use different signaling technologies:•LPDDR -> LVCMOS•DDR2 -> SSTLLet’s look at the pin DDR_D4 as an example…N3 DDR_D4 Selector_11So here is the corresponding snippet from Selector_11:|*****************************************************************************************| Usage I/O#1.35/1.5V/1.8V#X#X#BCSHTLTCSCDVPBFZ_SSDHV.PAD| Base model BCSHTLTCSCDVPBFZ_SSDHV|***************************************************************************************** [Model Selector] Selector_11<snip>Model_440 INPUT,1.8V,Pull-up/down off,IND,5%,VREF_NOTERM_PUPD_OFF_5PER_1P8<snip>Model_452 INPUT,1.8V,Pull-up/down off,IND,5%,LVCMOS_PUPD_OFF_5PER_1P8Model_440 and Model_452 above are nearly identical, but that is because both LPDDR and DDR2 are 1.8V interfaces. The final field holds the difference between them. Model_440 is of type VREF_NOTERM which3corresponds to DDR2 with no termination enabled (i.e. SSTL). Model_452 is of type LVCMOS, which is used for LPDDR.The register mapping that corresponds to this selection in the actual hardware is ddr_io_ctrl[mddr_sel]:•mddr_sel=0 -> DDR2/3 (SSTL)•mddr_sel=1 -> LPDDR (LVCMOS)Additional Notes on ioctrl Pin MappingThe ioctrl registers map to the actual pins as follows:Register[bits]Signalsddr_cmd0_ioctrl[9:5]ddr_ck, ddr_cknddr_cmd0_ioctrl[4:0]ddr_ba0, ddr_ba2, ddr_wen, ddr_a[9:8], ddr_a[6:3]ddr_cmd1_ioctrl[4:0]ddr_15, ddr_a[12:10], ddr_a7, ddr_a2, ddr_a0, ddr_ba1, ddr_casn, ddr_rasnddr_cmd2_ioctrl[4:0]ddr_cke, ddr_resetn, ddr_odt, ddr_csn0, ddr_[a14:13], ddr_a1ddr_data0_ioctrl[9:5]ddr_dqs1, ddr_dqsn1ddr_data0_ioctrl[4:0]ddr_d[15:8], ddr_dqm1ddr_data1_ioctrl[9:5]ddr_dqs0, ddr_dqsn0ddr_data1_ioctrl[4:0]ddr_d[7:0], dqm0ExampleIn AM335x EMIF Configuration tips the recommendation is to set all the IOCTRL registers to a value of 0x18B which breaks down as:•SR[9:8] = 01 slow•I[7:5] = 100 0.88*RExt•SR[4:3] = 01 slow•I[2:0] = 011 1.00*RExtAs an example, let's assume you would like to model this type of configuration for your own hardware. And let's assume for this example that you're using DDR3 (1.5V). Finally, we'll do this modeling using 5% power supply tolerance, though it could similarly be modeled using 10% tolerance (i.e. just choose the corresponding model).The IOCTRL settings above correspond to the slew rate for ALL signals being set to "slow". The Impedance is being configured differently for some of the signals. The breakdown of signals controlled by these registers can be found in Table 9-9. DDR PHY to IO Pin Mapping. The register descriptions of the IOCTRL specifies which signals are affected by SR[9:8]/I[7:5]. So in particular, the following use 0.88*RExt:•DQS•DQSn•CK•CKnCorrespondingly the signals above should choose models with Impedance of 0.88*RExt. The others should use1.00*RExt. So in this scenario we would use the following:4Signal Model DescriptionDQS Model_6553-STATE,1.5V,ODT off,slow, 0.88*RExt,IND,5%,SR01_9MA_PADP_5PER_1P5DQS#Model_8473-STATE,1.5V,ODT off,slow, 0.88*RExt,IND,5%,SR01_9MA_PADN_5PER_1P5CK Model_3433-STATE,1.5V,ODT off,slow, 0.88*RExt,IND,5%,SR01_9MA_5PER_1P5CK#Model_3433-STATE,1.5V,ODT off,slow, 0.88*RExt,IND,5%,SR01_9MA_5PER_1P5DQ Model_3523-STATE,1.5V,ODT off,slow, 1.00*RExt,IND,5%,SR01_8MA_5PER_1P5DM Model_3523-STATE,1.5V,ODT off,slow, 1.00*RExt,IND,5%,SR01_8MA_5PER_1P5Note that the write models always have ODT off since in that scenario ODT would be a function of the memory onthe other side. For reads, ODT would be the responsibility of AM335x and so that parameter is configurable for reads:Signal Model DescriptionDQS Model_1002INPUT,1.5V,FULLTERM, 0.88*RExt,IND,5%,DIFF_VREF_FULLTERM_9MA_5PER_1P5DQS#Model_1002INPUT,1.5V,FULLTERM, 0.88*RExt,IND,5%,DIFF_VREF_FULLTERM_9MA_5PER_1P5CK Model_3433-STATE,1.5V,ODT off,slow, 0.88*RExt,IND,5%,SR01_9MA_5PER_1P5CK#Model_3433-STATE,1.5V,ODT off,slow, 0.88*RExt,IND,5%,SR01_9MA_5PER_1P5DQ Model_496INPUT,1.5V,FULLTERM, 1.00*RExt,IND,5%,VREF_FULLTERM_8MA_5PER_1P5DM Model_3523-STATE,1.5V,ODT off,slow, 1.00*RExt,IND,5%,SR01_8MA_5PER_1P5Note that the DDR_CK, DDR_CKN, and DDR_DQM pins are always driven by the AM335x (not the memory) which is why it is of type "3-STATE" (output) for both write and read operations above.Verifying DDR ConfigurationAfter investing the effort to determine the best models for your board, it will be up to the software team to actually make the necessary changes. This final and most critical step of the process is often done improperly! In order to simplify the process, a JTAG based script was created to read important registers on the device and parse the contents to show what's actually being used. Here's how to use download and use this script:1.Download am335x-ddr-analysis.dss [1].unch CCS.3.Create an appropriate target configuration file for connecting to your board.•File -> New -> Target Configuration File•Supply a name/location for the file.•View -> Target Configurations to see the available target configurations (yours should now be among them!).•Double-click your file in the Target Configurations panel to open it for editing.•Select your emulator and processor. Be sure to select a processor and not a board, as we don't want any gel files to be part of the configuration. Save.unch the debugger, but do not connect to any CPUs.•In the Target Configurations window, right-click on your ccxml file and select "Launch Selected Configuration"unch the scripting console by going to View -> Scripting Console.6.Load am335x-ddr-analysis.dss in the scripting console by executing "loadJSFile<path-to-dss-file>/am335x-ddr-analysis.dss".57.It will use the Debug Access Port (DAP) unobtrusively behind the scenes such that the Cortex A8 is never halted.It will generate a am335x-ddr-analysis_yyyy-mm-dd_hhmmss.txt file on your desktop.References[1]https:///sitara-dss-files/am335x-dss-files/blobs/raw/master/am335x-ddr-analysis.dss6 Article Sources and ContributorsHow to use the AM335x IBIS Models Source: /index.php?oldid=235642 Contributors: BradGriffis。
MAX32665 MAX32666 用户指南说明书
MAX32665/MAX32666 USER GUIDE UG6971; Rev 3; 2/2022Abstract: This user guide provides application developers information on how to use the memory and peripherals of the MAX32665/MAX32666 microcontroller. Detailed information for all registers and fields in the device are covered. Guidance is given for managing all the peripherals, clocks, power and startup for the device family.MAX32665/MAX32666 User GuideTable of Contents1.Overview ----------------------------------------------------------------------------------------------------------------- 291.1 Block Diagram ---------------------------------------------------------------------------------------------------------------- 302.Resource Protection Unit (RPU) ------------------------------------------------------------------------------------ 31 2.1 Instances ----------------------------------------------------------------------------------------------------------------------- 31 2.2 Usage --------------------------------------------------------------------------------------------------------------------------- 332.2.1Reset State -------------------------------------------------------------------------------------------------------------------------------- 332.2.2MPU Implementation ------------------------------------------------------------------------------------------------------------------ 332.2.3MPU Protection Fault ------------------------------------------------------------------------------------------------------------------ 332.2.4RPU Protection Fault-------------------------------------------------------------------------------------------------------------------- 332.2.5RPU Fault Handler ----------------------------------------------------------------------------------------------------------------------- 33 2.3 Registers ----------------------------------------------------------------------------------------------------------------------- 342.4 Register Details -------------------------------------------------------------------------------------------------------------- 363.Memory, Register Mapping, and Access ------------------------------------------------------------------------- 40 3.1 Memory, Register Mapping, and Access Overview ----------------------------------------------------------------- 40 3.2 Field Access Definitions ---------------------------------------------------------------------------------------------------- 43 3.3 Standard Memory Regions ------------------------------------------------------------------------------------------------ 443.3.1Code Space -------------------------------------------------------------------------------------------------------------------------------- 443.3.2SRAM Space ------------------------------------------------------------------------------------------------------------------------------- 443.3.3Peripheral Space ------------------------------------------------------------------------------------------------------------------------- 453.3.4External RAM Space -------------------------------------------------------------------------------------------------------------------- 463.3.5External Device Space ------------------------------------------------------------------------------------------------------------------ 463.3.6System Area (Private Peripheral Bus) ---------------------------------------------------------------------------------------------- 463.3.7System Area (Vendor Defined) ------------------------------------------------------------------------------------------------------- 46 3.4 Device Memory Instances ------------------------------------------------------------------------------------------------- 463.4.1Main Program Flash Memory -------------------------------------------------------------------------------------------------------- 463.4.2Cache Memories ------------------------------------------------------------------------------------------------------------------------- 473.4.3Information Block Flash Memory---------------------------------------------------------------------------------------------------- 473.4.4System SRAM ----------------------------------------------------------------------------------------------------------------------------- 473.4.5AES Key and Working Space Memory ---------------------------------------------------------------------------------------------- 483.4.6MAA Key and Working Space Memory -------------------------------------------------------------------------------------------- 483.4.7TPU Memory ------------------------------------------------------------------------------------------------------------------------------ 48 3.5 AHB Interfaces --------------------------------------------------------------------------------------------------------------- 483.5.2AHB Masters ------------------------------------------------------------------------------------------------------------------------------ 48 3.6 Peripheral Register Map --------------------------------------------------------------------------------------------------- 493.6.1APB Peripheral Base Address Map -------------------------------------------------------------------------------------------------- 493.6.2AHB Peripheral Base Address Map ------------------------------------------------------------------------------------------------- 50 3.7 Error Correction Coding (ECC) Module --------------------------------------------------------------------------------- 513.7.1SRAM --------------------------------------------------------------------------------------------------------------------------------------- 513.7.2FLASH --------------------------------------------------------------------------------------------------------------------------------------- 513.7.3Cache --------------------------------------------------------------------------------------------------------------------------------------- 524.System, Power, Clocks, Reset --------------------------------------------------------------------------------------- 53 4.1 Oscillator Sources and Clock Switching -------------------------------------------------------------------------------- 534.1.1Oscillator Implementation ------------------------------------------------------------------------------------------------------------ 554.1.296MHz Internal Main High-Speed Oscillator ------------------------------------------------------------------------------------- 554.1.360MHz Low Power Internal Oscillator --------------------------------------------------------------------------------------------- 554.1.432MHz Bluetooth Radio Oscillator -------------------------------------------------------------------------------------------------- 554.1.57.3728MHz Internal Oscillator ------------------------------------------------------------------------------------------------------- 564.1.632.768kHz External Crystal Oscillator ---------------------------------------------------------------------------------------------- 564.1.78kHz Ultra-Low Power Nano-Ring Internal Oscillator ------------------------------------------------------------------------- 57 4.2 Operating Modes ------------------------------------------------------------------------------------------------------------ 574.2.1ACTIVE Mode ----------------------------------------------------------------------------------------------------------------------------- 584.2.2SLEEP Low Power Mode --------------------------------------------------------------------------------------------------------------- 584.2.3DEEPSLEEP Low Power Mode -------------------------------------------------------------------------------------------------------- 604.2.4BACKUP Low Power Mode ------------------------------------------------------------------------------------------------------------ 62 4.3 Device Resets ----------------------------------------------------------------------------------------------------------------- 634.3.1Peripheral Reset ------------------------------------------------------------------------------------------------------------------------- 664.3.2Soft Reset ---------------------------------------------------------------------------------------------------------------------------------- 664.3.3System Reset, External Reset --------------------------------------------------------------------------------------------------------- 664.3.4Power-On Reset -------------------------------------------------------------------------------------------------------------------------- 66 4.4 Cache --------------------------------------------------------------------------------------------------------------------------- 66 4.5 Instruction Cache Controller ---------------------------------------------------------------------------------------------- 674.5.1Enabling ICC0/ICC1/SFCC -------------------------------------------------------------------------------------------------------------- 674.5.2Flushing the ICC0/ICC1/SFCC Cache ------------------------------------------------------------------------------------------------ 684.5.3Flushing SRCC Cache -------------------------------------------------------------------------------------------------------------------- 68 4.6 Instruction Cache Controller Registers --------------------------------------------------------------------------------- 68 4.7 External RAM SPIXR Cache Controller (SRCC) ------------------------------------------------------------------------ 71 4.8 RAM Memory Management ---------------------------------------------------------------------------------------------- 714.8.2RAM Low Power Modes --------------------------------------------------------------------------------------------------------------- 71 4.9 Miscellaneous Control Registers ----------------------------------------------------------------------------------------- 72 4.10 Miscellaneous Control Registers Details ------------------------------------------------------------------------------- 73 4.11 Single Inductor Multiple Output (SIMO) Power Supply ------------------------------------------------------------ 754.11.1Power Supply Monitor ------------------------------------------------------------------------------------------------------------------ 76 4.12 Single Inductor Multiple Output (SIMO) Registers ------------------------------------------------------------------ 76 4.13 Single Inductor Multiple Output (SIMO) Registers Details -------------------------------------------------------- 78 4.14 Power Sequencer and Always-On Domain Registers --------------------------------------------------------------- 83 4.15 Power Sequencer and Always-On Domain Register Details ------------------------------------------------------- 84 4.16 Global Control Registers (GCR) ------------------------------------------------------------------------------------------- 92 4.17 Global Control Register Details (GCR) ---------------------------------------------------------------------------------- 92 4.18 Function Control Registers ---------------------------------------------------------------------------------------------- 121 4.19 Function Control Register Details ------------------------------------------------------------------------------------- 121 4.20 AES Key Registers ---------------------------------------------------------------------------------------------------------- 1224.21 AES Key Register Details ------------------------------------------------------------------------------------------------- 1225.Interrupts and Exceptions ------------------------------------------------------------------------------------------ 124 5.1 Features ---------------------------------------------------------------------------------------------------------------------- 1245.2 Interrupt Vector Table --------------------------------------------------------------------------------------------------- 1246.General-Purpose I/O and Alternate Function Pins (GPIO) --------------------------------------------------- 128 6.1 Instances --------------------------------------------------------------------------------------------------------------------- 128 6.2 Usage ------------------------------------------------------------------------------------------------------------------------- 1326.2.1Reset State ------------------------------------------------------------------------------------------------------------------------------ 1326.2.2Input Mode Configuration----------------------------------------------------------------------------------------------------------- 1326.2.3Output Mode Configuration -------------------------------------------------------------------------------------------------------- 1326.2.4Alternate Function Configuration ------------------------------------------------------------------------------------------------- 132 6.3 Configuring GPIO (External) Interrupts ------------------------------------------------------------------------------- 1326.3.1GPIO Interrupt Handling ------------------------------------------------------------------------------------------------------------- 1336.3.2Using GPIO for Wake-up from Low Power Modes ---------------------------------------------------------------------------- 133 6.4 Registers --------------------------------------------------------------------------------------------------------------------- 1346.5 Register Details ------------------------------------------------------------------------------------------------------------ 1357.Flash Controller (FLC) ------------------------------------------------------------------------------------------------ 143 7.1 Instances --------------------------------------------------------------------------------------------------------------------- 143 7.2 Usage ------------------------------------------------------------------------------------------------------------------------- 1437.2.1Clock Configuration ------------------------------------------------------------------------------------------------------------------- 1447.2.3Flash Write Width --------------------------------------------------------------------------------------------------------------------- 1447.2.4Flash Write ------------------------------------------------------------------------------------------------------------------------------ 1447.2.5Page Erase ------------------------------------------------------------------------------------------------------------------------------- 1457.2.6Mass Erase ------------------------------------------------------------------------------------------------------------------------------ 145 7.3 Flash Error Correction Coding ------------------------------------------------------------------------------------------ 145 7.4 Flash Controller Registers ----------------------------------------------------------------------------------------------- 1467.5 Flash Controller Register Details --------------------------------------------------------------------------------------- 1468.External Memory ----------------------------------------------------------------------------------------------------- 151 8.1 Overview --------------------------------------------------------------------------------------------------------------------- 151 8.2 SPI Execute-in-Place Flash (SPIXF) ------------------------------------------------------------------------------------- 1518.2.1SPIXF Master Controller -------------------------------------------------------------------------------------------------------------- 1528.2.2SPIXF Master ---------------------------------------------------------------------------------------------------------------------------- 166 8.3 SPI Execute-in-Place RAM (SPIXR) ------------------------------------------------------------------------------------- 1758.3.1SPIXR Master Controller Registers ------------------------------------------------------------------------------------------------ 1768.3.2SPIXR Register Details ---------------------------------------------------------------------------------------------------------------- 176 8.4 SPIXR Cache Controller (SRCC) ----------------------------------------------------------------------------------------- 1868.4.1Features ---------------------------------------------------------------------------------------------------------------------------------- 1868.4.2Enabling the SRCC --------------------------------------------------------------------------------------------------------------------- 1868.4.3Disabling the SRCC -------------------------------------------------------------------------------------------------------------------- 1868.4.4SRCC Registers -------------------------------------------------------------------------------------------------------------------------- 1868.4.5SRCC Register Details ----------------------------------------------------------------------------------------------------------------- 187 8.5 Secure Digital Host Controller ------------------------------------------------------------------------------------------ 1888.5.1Instances --------------------------------------------------------------------------------------------------------------------------------- 1908.5.2SDHC Peripheral Clock Selection --------------------------------------------------------------------------------------------------- 1918.5.3Usage ------------------------------------------------------------------------------------------------------------------------------------- 1918.5.4SD Command Generation ----------------------------------------------------------------------------------------------------------- 1928.5.5SDHC Registers ------------------------------------------------------------------------------------------------------------------------- 1938.5.6SDHC Register Details ---------------------------------------------------------------------------------------------------------------- 1959.Standard DMA (DMA) ------------------------------------------------------------------------------------------------ 232 9.1 Instances --------------------------------------------------------------------------------------------------------------------- 232 9.2 DMA Channel Operation (DMA_CH) ---------------------------------------------------------------------------------- 2339.2.1DMA Channel Arbitration and DMA Bursts ------------------------------------------------------------------------------------- 2339.2.2DMA Source and Destination Addressing --------------------------------------------------------------------------------------- 2339.2.3Data Movement from Source to DMA ------------------------------------------------------------------------------------------- 2349.2.4Data Movement from the DMA to Destination -------------------------------------------------------------------------------- 2359.4 Count-to-Zero (CTZ) Condition ----------------------------------------------------------------------------------------- 236 9.5 Chaining Buffers ----------------------------------------------------------------------------------------------------------- 236 9.6 DMA Interrupts ------------------------------------------------------------------------------------------------------------ 238 9.7 Channel Timeout Detect ------------------------------------------------------------------------------------------------- 238 9.8 Memory-to-Memory DMA ---------------------------------------------------------------------------------------------- 239 9.9 DMA Registers -------------------------------------------------------------------------------------------------------------- 239 9.10 DMA Register Details ----------------------------------------------------------------------------------------------------- 239 9.11 DMA Channel Register Summary -------------------------------------------------------------------------------------- 239 9.12 DMA Channel Registers -------------------------------------------------------------------------------------------------- 2409.13 DMA Channel Register Details ----------------------------------------------------------------------------------------- 24010.Analog-to-Digital Converter (ADC) and Comparators ----------------------------------------------------- 245 10.1 Features ---------------------------------------------------------------------------------------------------------------------- 245 10.2 Instances --------------------------------------------------------------------------------------------------------------------- 245 10.3 Architecture ----------------------------------------------------------------------------------------------------------------- 245 10.4 Clock Configuration ------------------------------------------------------------------------------------------------------- 247 10.5 Power-Up Sequence ------------------------------------------------------------------------------------------------------ 247 10.6 Conversion ------------------------------------------------------------------------------------------------------------------ 248 10.7 Reference Scaling and Input Scaling ---------------------------------------------------------------------------------- 24810.7.1AIN0 – AIN7 Scale Limitations ------------------------------------------------------------------------------------------------------ 24810.7.2Scale Limitations for All Other Input Channels --------------------------------------------------------------------------------- 24810.7.3Data Conversion Output Alignment ---------------------------------------------------------------------------------------------- 24910.7.4Data Conversion Value Equations ------------------------------------------------------------------------------------------------- 24910.7.5Data Limits and Out of Range Interrupts ---------------------------------------------------------------------------------------- 25010.7.6Power-Down Sequence--------------------------------------------------------------------------------------------------------------- 252 10.8 Comparator Operation --------------------------------------------------------------------------------------------------- 252 10.9 Registers --------------------------------------------------------------------------------------------------------------------- 25210.10 Register Details ------------------------------------------------------------------------------------------------------------ 25211.UART ------------------------------------------------------------------------------------------------------------------ 257 11.1 Instances --------------------------------------------------------------------------------------------------------------------- 257 11.2 UART Frame ----------------------------------------------------------------------------------------------------------------- 257 11.3 UART Interrupts ------------------------------------------------------------------------------------------------------------ 258 11.4 UART Baud Rate Clock Source ------------------------------------------------------------------------------------------ 258 11.5 UART Baud Rate Calculation -------------------------------------------------------------------------------------------- 258 11.6 FIFOs -------------------------------------------------------------------------------------------------------------------------- 26011.6.2Receive FIFO Operation -------------------------------------------------------------------------------------------------------------- 260 11.7 UART Configuration and Operation ----------------------------------------------------------------------------------- 260 11.8 Wake-up Time -------------------------------------------------------------------------------------------------------------- 261 11.9 Hardware Flow Control -------------------------------------------------------------------------------------------------- 261 11.10 Registers --------------------------------------------------------------------------------------------------------------------- 26111.11 Register Details ------------------------------------------------------------------------------------------------------------ 26212.I2C Master/Slave Serial Communications Peripheral (I2C) ------------------------------------------------ 270 12.1 I2C Master and Slave Features ------------------------------------------------------------------------------------------ 272 12.2 Instances --------------------------------------------------------------------------------------------------------------------- 272 12.3 I2C Overview ---------------------------------------------------------------------------------------------------------------- 27212.3.1I2C Bus Terminology ------------------------------------------------------------------------------------------------------------------- 27212.3.2I2C Transfer Protocol Operation --------------------------------------------------------------------------------------------------- 27312.3.3START and STOP Conditions -------------------------------------------------------------------------------------------------------- 27312.3.4Master Operation --------------------------------------------------------------------------------------------------------------------- 27312.3.5Acknowledge and Not Acknowledge --------------------------------------------------------------------------------------------- 27312.3.6Bit Transfer Process ------------------------------------------------------------------------------------------------------------------- 274 12.4 I2C Configuration and Usage -------------------------------------------------------------------------------------------- 27412.4.1SCL and SDA Bus Drivers ------------------------------------------------------------------------------------------------------------- 27412.4.2SCL Clock Configurations ------------------------------------------------------------------------------------------------------------ 27512.4.3SCL Clock Generation for Standard, Fast and Fast-Plus Modes ----------------------------------------------------------- 27512.4.4SCL Clock Generation for Hs-Mode ----------------------------------------------------------------------------------------------- 27612.4.5Master Mode Addressing ------------------------------------------------------------------------------------------------------------ 27712.4.6Master Mode Operation ------------------------------------------------------------------------------------------------------------- 27712.4.7Slave Mode Operation --------------------------------------------------------------------------------------------------------------- 28012.4.8Interrupt Sources ---------------------------------------------------------------------------------------------------------------------- 28412.4.9Transmit FIFO and Receive FIFO --------------------------------------------------------------------------------------------------- 28412.4.10Transmit FIFO Preloading ------------------------------------------------------------------------------------------------------- 28512.4.11Interactive Receive Mode (IRXM) --------------------------------------------------------------------------------------------- 28612.4.12Clock Stretching -------------------------------------------------------------------------------------------------------------------- 28712.4.13Bus Timeout ------------------------------------------------------------------------------------------------------------------------- 28712.4.14DMA Control ------------------------------------------------------------------------------------------------------------------------ 288 12.5 Registers --------------------------------------------------------------------------------------------------------------------- 28812.6 Register Details ------------------------------------------------------------------------------------------------------------ 28913.Serial Peripheral Interface (SPI) -------------------------------------------------------------------------------- 303 13.1 Instances --------------------------------------------------------------------------------------------------------------------- 304。
GSM900M无线宽带室内干放(V2.0 )整机调试说明
深圳国人通信有限公司GSM900M无线宽带室内主干放（500ｍW、1W、2W、5W）GSM900M无线宽带室内从干放（500ｍW、1W、2W、5W）整机调试说明文件编号：SGR2.012.946TS版本：V1.0生效日期：编制：部门／职位：开发工程师日期：初审：部门／职位：项目经理日期：复审：部门／职位：部门经理日期：批准：部门／职位：总工程师日期：文件更改履历表目录1 范围 (1)2 测量条件 (1)3 测试所需仪器列表 (1)4 测试连接框图 (1)5 测试附加损耗及测试仪器的校准 (3)6 测试内容及规范 (4)6.1 最大输出功率 (4)6.2 ALC自动电平控制 (4)6.3 最大增益 (5)6.4 增益调节范围 (5)6.5 增益调节步长及步长误差 (5)6.6 带外杂散发射 (5)6.7 互调衰减 (5)6.8 输入输出电压驻波比 (6)6.9 时延测试 (6)6.10 带内波动 (6)6.11 环境实验 (7)6.12 动态老化试验 (7)6.13 监控程序烧录 (7)6.13.1 烧录准备工具： (7)6.13.2 烧录步骤 (7)7 中移协议 (11)7.1 中移协议机型 (11)7.2 调试工具 (11)7.3 调试步骤 (11)7.3.1 配置界面 (11)7.3.2 进入主菜单 (13)7.3.3 设备信息 (13)7.3.4 设置参数 (14)7.3.5 告警和状态 (16)7.3.6 实时采样数据 (18)8 联通协议 (19)8.1 联通协议机型 (19)8.2 调试工具 (19)8.3 调试步骤 (19)8.3.1 配置界面 (19)8.3.2 设置类操作 (21)8.3.3 查询类操作 (25)9 注意事项 (28)1 范 围本文件适用于中移和联通协议，具体可参见各自说明。
2 测量条件应在下列正常工作条件下进行测量：－ 温度：+15℃～+35℃ － 相对湿度：45～75%3 测试所需仪器列表信号源Agilent E4438C/E4432B 2台频谱分析仪 Agilent E4405B/E4402B 或 ADVANTEST 1台 矢量网络分析仪Agilent 8573ES 1套 噪声系数仪Agilent N8973A 1套 合路器（3dB ） 1个 衰减器30dB( 25W 以上) 2个 衰减器20 dB( 25W 以上) 1个 隔离器 800M-1G2个4 测试连接框图图2 测试功率、增益、ALC、增益调节步长误差等指标连线图图3 驻波测试连接图图4 波动/时延测试连接图5测试附加损耗及测试仪器的校准如图（1）所示，将信号源与直放站输入端口之间的线损校入信号源,将直放站输入端口与频谱分析仪之间的损耗校入频谱分析仪。
AM335x uboot spl分析
AM335x uboot spl分析芯片到uboot启动流程ROM → SPL→ uboot.img简介在335x 中ROM code是第一级的bootlader。
mpu上电后将会自动执行这里的代码，完成部分初始化和引导第二级的bootlader，第二级的bootlader引导第三级bootader，在ti官方上对于第二级和第三级的bootlader由uboot提供。
SPLTo unify all existing implementations for a secondary program loader (SPL) and to allow simply adding of new implementations this generic SPL framework has been created. With this framework almost all source files for a board can be reused. No code duplication or symlinking is necessary anymore.1> Basic ARM initialization2> UART console initialization3> Clocks and DPLL locking (minimal)4> SDRAM initialization5> Mux (minimal)6> BootDevice initialization(based on where we are bootingfrom.MMC1/MMC2/Nand/Onenand)7> Bootloading real u-boot from the BootDevice and passing control to it.uboot spl源代码分析一、makefile分析打开spl文件夹只有一个makefile 可见spl都是复用uboot原先的代码。
Motorola 3.5 kHz 产品说明书
RVN4126 3.59100-386-9100-386/T DEVICERVN41772-CD2-3.5MCS/MTSRVN41821-CD2-3.5XTS3000/SABER PORTABLE YES RKN4046KHVN9085 3.51-20 R NO HLN9359 PROG. STAND RVN4057 3.532 X 8 CODEPLUG NO3080385B23 & 5880385B30 MDVN4965 3.59100-WS/T CONFIG KITRVN4053 3.5ASTRO DIGITAL INTERFACE NO3080385B23RVN41842-CD RKN4046A (Portable) 2-3.5ASTRO PORTABLE /MOBILE YES3080369B73 or0180300B10 (Mobile) RVN41831-CD3080369B732-3.5ASTRO SPECTRA MOBILE YES(Low / Mid Power)0180300B10 (High Power) RVN4185CD ASTRO SPECTRA PLUS MOBILE NO MANY OPTIONS; SEESERVICE BRIEF#SB-MO-0101RVN4186CD ASTRO SPECTRA PLUS MANY OPTIONS;MOBILE/PORTABLE COMB SEE SERVICE BRIEF#SB-MO-0101RVN4154 3.5ASTROTAC 3000 COMPAR.3080385B23RVN5003 3.5ASTROTAC COMPARATORS NO3080399E31 Adpt.5880385B34RVN4083 3.5BSC II NO FKN5836ARVN4171 3.5C200RVN4029 3.5CENTRACOM SERIES II NO VARIOUS-SEE MANUAL6881121E49RVN4112 3.5COMMAND PLUS NORVN4149 3.5COMTEGRA YES3082056X02HVN6053CD CT250, 450, 450LS YES AAPMKN4004RVN4079 3.5DESKTRAC CONVENTIONAL YES3080070N01RVN4093 3.5DESKTRAC TRUNKED YES3080070N01RVN4091 3.5DGT 9000 DESKSET YES0180358A22RVN4114 3.5GLOBAL POSITIONING SYS.NO RKN4021AHVN8177 3.5GM/GR300/GR500/GR400M10/M120/130YES3080070N01RVN4159 3.5GP60 SERIES YES PMLN4074AHVN9128 3.5GP300 & GP350RVN4152 3.5GP350 AVSRVN4150 3.5GTX YES HKN9857 (Portable)3080070N01(Mobile) HVN9025CD HT CDM/MTX/EX SERIES YES AARKN4083/AARKN4081RiblessAARKN4075RIBLESS NON-USA RKN4074RVN4098H 3.5HT1000/JT1000-VISAR YES3080371E46(VISAR CONV)RVN4151 3.5HT1000 AVSRVN4098 3.5HT1000/ VISAR CONV’L.YES RKN4035B (HT1000) HVN9084 3.5i750YES HLN-9102ARVN4156 3.5LCS/LTS 2000YES HKN9857(Portable)3080070N01(Mobile) RVN4087 3.5LORAN C LOC. RECV’R.NO RKN4021ARVN4135 3.5M100/M200,M110,M400,R100 includesHVN9173,9177,9646,9774YES3080070N01RVN4023 3.5MARATRAC YES3080070N01RVN4019 3.5MAXTRAC CONVENTIONAL YES3080070N01RVN4139 3.5MAXTRAC LS YES3080070N01RVN4043 3.5MAXTRAC TRK DUPLEX YES3080070N01RVN4178CD MC SERIES, MC2000/2500DDN6124AW/DB25 CONNECTORDDN6367AW/DB9 CONNECTOR RVN41751-CD Rib to MIC connector 1-3.5MCS2000 RKN4062BRVN41131-3.5MCS2000RVN4011 3.5MCX1000YES3000056M01RVN4063 3.5MCX1000 MARINE YES3000056M01RVN4117 3.5MDC/RDLAP DEVICESRVN4105 3.5MOBILE PROG. TOOLRVN4119 3.5MOBITEX DEVICESRVN4128 3.5MPT1327-1200 SERIES YES SEE MANUALRVN4025 3.5MSF5000/PURC/ANALOG YES0180355A30RVN4077 3.5MSF5000/10000FLD YES0180355A30RVN4017K 3.5MT 1000YES RTK4205CRVN4148 3.5MTR 2000YES3082056X02RVN4140 3.5MTRI 2000NORVN41761-CD MTS2000, MT2000*, MTX8000, MTX90001-3.5*programmed by DOS which is included in the RVN4176RVN4131 3.5MTVA CODE PLUG FIXRVN4142 3.5MTVA DOCTOR YES3080070N01RVN4131 3.5MTVA3.EXERVN4013 3.5MTX800 & MTX800S YES RTK4205CRVN4097 1-CD MTX8000/MTX9000,MTS2000,MT2000*,* programmed by DOS which is included in the RVN4176HVN9067CD MTX850/MTX8250MTX950,MTX925RVN4138 3.5MTX-LS YES RKN4035DRVN4035 3.5MX 1000YES RTK4203CRVN4073 3.5MX 800YES RKN4006BHVN9395 P100, P200 LB, P50+, P210, P500, PR3000RVN4134 3.5P100 (HVN9175)P200 LB (HVN9794)P50+ (HVN9395)P210 (HVN9763)P500 (HVN9941)PR3000 (HVN9586)YES RTK4205HVN9852 3.5P110YES HKN9755A/REX1143 HVN9262 3.5P200 UHF/VHF YES RTK4205RVN4129 3.5PDT220YVN4051 3.5PORTABLE REPEATER Portable rptr.P1820/P1821AXRVN4061C 3.5PP 1000/500NO3080385B23 & 5880385B30 RVN5002 3.5QUANTAR/QUANTRO NO3O80369E31RVN4135 3.5R100 (HVN9177)M100/M200/M110/M400YES0180358A52RVN4146 3.5RPM500/660RVN4002 3.5SABER YES RTK4203CRVN4131 3.5SETTLET.EXEHVN9007 3.5SM50 & SM120YESRVN4039 3.5SMART STATUS YES FKN5825AHVN9054 3.5SOFTWARE R03.2 P1225YES3080070N01HVN9001 3.5SOFTWARE R05.00.00 1225LS YES HLN9359AHVN9012 3.5SP50RVN4001N 3.5SPECTRA YES3080369B73 (STANDARD)0180300B10 (HIGH POWER) RVN4099 3.5SPECTRA RAILROAD YES3080369B73RVN4110 3.5STATION ACCESS MODULE NO3080369E31RVN4089A 3.5STX TRANSIT YES0180357A54RVN4051 3.5SYSTEMS SABER YES RTK4203BRVN4075 3.5T5600/T5620 SERIES NO3080385B23HVN9060CD TC3000, TS3000, TR3000RVN4123 3.5VISAR PRIVACY PLUS YES3080371E46FVN4333 3.5VRM 100 TOOLBOX FKN4486A CABLE &ADAPTORRVN4133 3.5VRM 500/600/650/850NORVN4181CD XTS 2500/5000 PORTABLES RKN4105A/RKN4106A RVN41002- 3.5XTS3000 ASTRO PORTABLE/MOBILERVN4170 3.5XTS3500YES RKN4035DRIB SET UPRLN4008E RADIO INTERFACE BOX (RIB)0180357A57RIB AC POWER PACK 120V0180358A56RIB AC POWER PACK 220V3080369B71IBM TO RIB CABLE (25 PIN) (USE WITH XT & PS2)3080369B72IBM TO RIB CABLE (9 PIN)RLN443825 PIN (F) TO 9 PIN (M) ADAPTOR (USE W/3080369B72 FOR AT APPLICATION) 5880385B308 PIN MODULAR TO 25 PIN ”D” ADAPTOR (FOR T5600 ONLY)0180359A29DUPLEX ADAPTOR (MOSTAR/TRAXAR TRNK’D ONLY)Item Disk Radio RIB Cable Number Size Product Required Number Item Disk Radio RIB Cable Number Size Product Required NumberUtilizing your personal computer, Radio Service Software (RSS)/Customer Programming Software (CPS)/CustomerConfiguration Software (CCS) enables you to add or reprogram features/parameters as your requirements change. RSS/CPS/CCS is compatible with IBM XT, AT, PS/2 models 30, 50, 60 and 80.Requires 640K RAM. DOS 3.1 or later. Consult the RSS users guide for the computer configuration and DOS requirements. (ForHT1000, MT/MTS2000, MTX838/8000/9000, Visar and some newer products —IBM model 386, 4 MEG RAM and DOS 5.0 or higher are recommended.) A Radio Interface Box (RIB) may be required as well as the appropriate cables. The RIB and cables must be ordered separately.Licensing:A license is required before a software (RVN) order is placed. The software license is site specific (customer number and ultimate destination tag). All sites/locations must purchase their own software.Be sure to place subsequent orders using the original customer number and ship-to-tag or other licensed sites; ordering software without a licensed customer number and ultimate tag may result in unnecessary delays. To obtain a no charge license agreement kit, order RPX4719. To place an order in the U.S. call 1-800-422-4210. Outside the U.S., FAX 847-576-3023.Subscription Program:The purchase of Radio ServiceSoftware/Customer Programming/Customer ConfigurationSoftware (RVN & HVN kits) entitles the buyer/subscriber to three years of free upgrades. At the end of these three years, the sub-scriber must purchase the same Radio Service Software kit to receive an additional three years of free upgrades. If the sub-scriber does not elect to purchase the same Radio Service Software kit, no upgrades will be sent. Annually a subscription status report is mailed to inform subscribers of the RSS/CPS/CCS items on our database and their expiration dates.Notes:1)A subscription service is offered on “RVN”-Radio Service Software/Customer Programming/Customer Configuration Software kits only.2)“RVN” software must only be procured through Radio Products and Services Division (RPSD). Software not procured through the RPSD will not be recorded on the subscription database; upgrades will not be mailed.3)Upgrades are mailed to the original buyer (customer number & ultimate tag).4)SP software is available through the radio product groups.The Motorola General Radio Service Software Agreement is now available on Motorola Online. If you need assistance please feel free to submit a “Contact Us” or call 800-422-4210.SMART RIB SET UPRLN1015D SMART RIB0180302E27 AC POWER PACK 120V 2580373E86 AC POWER PACK 220V3080390B49SMARTRIB CABLE (9 PIN (F) TO 9 PIN (M) (USE WITH AT)3080390B48SMARTRIB CABLE (25 PIN (F) TO 9 PIN (M) (USE WITH XT)RLN4488ASMART RIB BATTERY PACKWIRELESS DATA GROUP PRODUTS SOFTWARERVN4126 3.59100-386/9100T DEVICES MDVN4965 3.59100-WS/T CONFIG’TN RVN41173.5MDC/RDLAP DEVICESPAGING PRODUCTS MANUALS6881011B54 3.5ADVISOR6881029B90 3.5ADVISOR ELITE 6881023B20 3.5ADVISOR GOLD 6881020B35 3.5ADVISOR PRO FLX 6881032B30 3.5BR8506881032B30 3.5LS3506881032B30 3.5LS5506881032B30 3.5LS7506881033B10 3.5LS9506881035B20 3.5MINITOR III8262947A15 3.5PAGEWRITER 20008262947A15 3.5PAGEWRITER 2000X 6881028B10 3.5TALKABOUT T3406881029B35 3.5TIMEPORT P7308262947A15 3.5TIMEPORT P930NLN3548BUNIVERSAL INTERFACE KITItem Disk Radio NumberSize Product。
TIAM335x系列处理器6LoWPAN网络参考设计TIDA010032
TI公司的AM335x系列微处理器是基于ARM Cortex-A8处理器,工作频率高达1GHz,具有增强图像,图形处理,外设和工业接口选择如EtherCAT和PROFIBUS,支持高级操作系统(HLOS).器件还具有NEON™ SIMD协处理器,32KB L1指令和32KB数据缓存,256KB L2高速缓存,176KB引导ROM和64KB专用RAM,主要用在数据集中器和无线通信.本文介绍了AM335x处理器主要特性,功能框图以及支持以太网,6LoWPAN RF网络和更多的通用数据集中器参考设计TIDA-010032主要指标,网络指标,框图,系统架构图,电路图,材料清单和PCB设计图.The AM335x microprocessors, based on the ARM Cortex-A8 processor, are enhanced with image,graphics processing, peripherals and industrialinterface options such as EtherCAT and PROFIBUS. Thedevices supporthigh-level operating systems (HLOS). Processor SDK Linux® and TI-RTOS are availablefree of charge from TI.The AM335x microprocessor contains the subsystems shown in theFunctional Block Diagram and a briefdescription of each follows: The contains the subsystems shown in the Functional Block Diagramand a brief description of eachfollows:The microprocessor unit (MPU) subsystem is based on the ARM Cortex-A8 processor and the PowerVRSGX™ Graphics Accelerator subsystemprovides 3D graphics acceleration to support display and gamingeffects.The PRU-ICSS is separate from the ARM core, allowing independentoperation and clocking for greaterefficiency and flexibility.The PRU-ICSS enables additional peripheral interfaces and real-time protocolssuch as EtherCAT, PROFINET, EtherNet/IP, PROFIBUS, Ethernet Powerlink, Sercos, and others.Additionally, the programmable nature of the PRU-ICSS, along with its access to pins, events and allsystem-on-chip (SoC) resources, providesflexibility in implementing fast, real-time responses, specializeddatahandling operations, custom peripheral interfaces, and in offloading tasks from the other processorcores of SoC.AM335x处理器主要特性:• Up to 1-GHz Sitara™ ARM® Cortex®-A8 32 BitRISC Processor– NEON™ SIMD Coprocessor– 32KB of L1 Instruction and 32KB of Data CacheWith Single-ErrorDetection (Parity)– 256KB of L2 Cache With Error Correcting Code(ECC)– 176KB of On-Chip Boot ROM– 64KB of Dedicated RAM– Emulation and Debug - JTAG– Interrupt Controller (up to 128 InterruptRequests)• On-Chip Memory (Shared L3 RAM)– 64KB of General-Purpose On-Chip MemoryController (OCMC) RAMTI AM335x系列处理器6LoWPAN网络参考设计TIDA－010032– Accessible to All Masters– Supports Retention for Fast Wakeup• External Memory Interfaces (EMIF)– mDDR(LPDDR), DDR2, DDR3, DDR3LController:– mDDR: 200-MHz Clock (400-MHz Data Rate)– DDR2: 266-MHz Clock (532-MHz Data Rate)– DDR3: 400-MHz Clock (800-MHz Data Rate)– DDR3L: 400-MHz Clock (800-MHz DataRate)– 16-Bit Data Bus– 1GB of Total Addressable Space– Supports One x16 or Two x8 Memory DeviceConfigurations– General-Purpose Memory Controller (GPMC)– Flexible 8-Bit and 16-Bit AsynchronousMemory Interface With up toSeven Chip Selects (NAND, NOR, Muxed-NOR, SRAM)– Uses BCH Code to Support 4-, 8-, or 16-BitECC– Uses Hamming Code to Support 1-Bit ECC– Error Locator Module (ELM)– Used in Conjunction With the GPMC toLocate Addresses of Data Errors fromSyndrome Polynomials Generated Using aBCH Algorithm– Supports 4-, 8-, and 16-Bit per 512-ByteBlock Error Location Based on BCHAlgorithms • Programmable Real-Time Unit Subsystem andIndustrial Communication Subsystem (PRU-ICSS)– Supports Protocols such as EtherCAT®,PROFIBUS, PROFINET,EtherNet/IP™, and More– Two Programmable Real-Time Units (PRUs)– 32-Bit Load/Store RISC Processor Capableof Running at 200 MHz– 8KB of Instruction RAM With Single-ErrorDetection (Parity)– 8KB of Data RAM With Single-Error Detection(Parity)– Single-Cycle 32-Bit Multiplier With 64-BitAccumulator– Enhanced GPIO Module Provides Shift-In/Out Support and Parallel Latch on External Signal– 12KB of Shared RAM With Single-ErrorDetection (Parity)– Three 120-Byte Register Banks Accessible byEach PRU– Interrupt Controller (INTC) for Handling SystemInput Events– Local Interconnect Bus for Connecting Internaland External Masters to the Resources Insidethe PRU-ICSS– Peripherals Inside the PRU-ICSS:– One UART Port With Flow Control Pins,Supports up to 12 Mbps– One Enhanced Capture (eCAP) Module– Two MII Ethernet Ports that Support IndustrialEthernet, such as EtherCAT – One MDIO Port• Power, Reset, and Clock Management (PRCM)Module– Controls the Entry and Exit of Stand-By andDeep-Sleep Modes– Responsible for Sleep Sequencing, PowerDomain Switch-Off Sequencing, Wake-Up Sequencing, and Power Domain Switch-OnSequencing– Clocks– Integrated 15- to 35-MHz High-frequencyOscillator Used to Generate a Reference Clock for Various System and PeripheralClocks– Supports Individual Clock Enable and DisableControl for Subsystems and Peripherals toFacilitate Reduced Power Consumption– Five ADPLLs to Generate System Clocks(MPU Subsystem, DDR Interface, USB and Peripherals [MMC and SD, UART, SPI, I2C],L3, L4, Ethernet, GFX [SGX530], LCD Pixel Clock)– Power– Two Nonswitchable Power Domains (Real-Time Clock [RTC], Wake-UpLogic[WAKEUP])– Three Switchable Power Domains (MPUSubsystem [MPU], SGX530 [GFX], Peripherals and Infrastructure [PER])– Implements SmartReflex™ Class 2B for CoreVoltage Scaling Based On Die Temperature,Process Variation, and Performance(Adaptive Voltage Scaling [AVS])– Dynamic Voltage Frequency Scaling (DVFS)• Real-Time Clock (RTC)– Real-Time Date (Day-Month-Year-Day of Week)and Time (Hours-Minutes-Seconds) Information– Internal 32.768-kHz Oscillator, RTC Logic and1.1-V Internal LDO– Independent Power-on-Reset(RTC_PWRONRSTn) Input– Dedicated Input Pin (EXT_WAKEUP) forExternal Wake Events– Programmable Alarm Can be Used to GenerateInternal Interrupts to the PRCM (for Wakeup) orCortex-A8 (for Event Notification)– Programmable Alarm Can be Used WithExternal Output(PMIC_POWER_EN) to Enablethe Power Management IC to Restore Non-RTCPower Domains• Peripherals– Up to Two USB 2.0 High-Speed DRD (Dual-Role Device) Ports WithIntegrated PHY– Up to Two Industrial Gigabit Ethernet MACs (10,100, 1000 Mbps)– Integrated Switch– Each MAC Supports MII, RMII, RGMII, andMDIO Interfaces– Ethernet MACs and Switch Can OperateIndependent of Other Functions – IEEE 1588v2 Precision Time Protocol (PTP)– Up to Two Controller-Area Network (CAN) Ports– Supports CAN Version 2 Parts A and B– Up to Two Multichannel Audio Serial Ports(McASPs)– Transmit and Receive Clocks up to 50 MHz– Up to Four Serial Data Pins per McASP PortWith Independent TX and RX Clocks– Supports Time Division Multiplexing (TDM),Inter-IC Sound (I2S), andSimilar Formats– Supports Digital Audio Interface Transmission(SPDIF, IEC60958-1, and AES-3 Formats)– FIFO Buffers for Transmit and Receive (256Bytes)– Up to Six UARTs– All UARTs Support IrDA and CIR Modes– All UARTs Support RTS and CTS FlowControl– UART1 Supports Full Modem Control– Up to Two Master and Slave McSPI SerialInterfaces– Up to Two Chip Selects– Up to 48 MHz– Up to Three MMC, SD, SDIO Ports– 1-, 4- and 8-Bit MMC, SD, SDIO Modes– MMCSD0 has Dedicated Power Rail for 1.8 Vor 3.3-V Operation– Up to 48-MHz Data Transfer Rate– Supports Card Detect and Write Protect– Complies With MMC4.3, SD, SDIO 2.0Specifications– Up to Three I2C Master and Slave Interfaces– Standard Mode (up to 100 kHz)– Fast Mode (up to 400 kHz)– Up to Four Banks of General-Purpose I/O(GPIO) Pins– 32 GPIO Pins per Bank (Multiplexed WithOther Functional Pins)– GPIO Pins Can be Used as Interrupt Inputs(up to Two Interrupt Inputs per Bank)– Up to Three External DMA Event Inputs that canAlso be Used as Interrupt Inputs– Eight 32-Bit General-Purpose Timers– DMTIMER1 is a 1-ms Timer Used forOperating System (OS) Ticks– DMTIMER4–DMTIMER7 are Pinned Out– One Watchdog Timer– SGX530 3D Graphics Engine– Tile-Based Architecture Delivering up to 20Million Polygons per Second – Universal Scalable Shader Engine (USSE) isa Multithreaded EngineIncorporating Pixel and Vertex Shader Functionality– Advanced Shader Feature Set in Excess ofMicrosoft VS3.0, PS3.0, andOGL2.0– Industry Standard API Support of Direct3DMobile, OGL-ES 1.1 and 2.0,and OpenMax– Fine-Grained Task Switching, LoadBalancing, and Power Management– Advanced Geometry DMA-Driven Operationfor Minimum CPU Interaction – Programmable High-Quality Image Anti-Aliasing– Fully Virtualized Memory Addressing for OSOperation in a UnifiedMemory Architecture– LCD Controller– Up to 24-Bit Data Output; 8 Bits per Pixel(RGB)– Resolution up to 2048 × 2048 (WithMaximum 126-MHz Pixel Clock)– Integrated LCD Interface Display Driver(LIDD) Controller– Integrated Raster Controller– Integrated DMA Engine to Pull Data from theExternal Frame BufferWithout Burdening theProcessor via Interrupts or a Firmware Timer– 512-Word Deep Internal FIFO– Supported Display Types:– Character Displays - Uses LIDD Controllerto Program these Displays– Passive Matrix LCD Displays - Uses LCDRaster Display Controller toProvideTiming and Data for Constant GraphicsRefresh to a Passive Display – Active Matrix LCD Displays – UsesExternal Frame Buffer Space andtheInternal DMA Engine to Drive StreamingData to the Panel– 12-Bit Successive Approximation Register(SAR) ADC– 200K Samples per Second– Input can be Selected from any of the EightAnalog Inputs MultiplexedThrough an 8:1 Analog Switch– Can be Configured to Operate as a 4-Wire, 5-Wire, or 8-Wire ResistiveTouch Screen Controller (TSC) Interface– Up to Three 32-Bit eCAP Modules – Configurable as Three Capture Inputs orThree Auxiliary PWM Outputs– Up to Three Enhanced High-Resolution PWMModules (eHRPWMs)– Dedicated 16-Bit Time-Base Counter WithTime and Frequency Controls – Configurable as Six Single-Ended, Six Dual-Edge Symmetric, or ThreeDual-Edge Asymmetric Outputs– Up to Three 32-Bit Enhanced QuadratureEncoder Pulse (eQEP) Modules • Device Identification– Contains Electrical Fuse Farm (FuseFarm) ofWhich Some Bits are Factory Programmable– Production ID– Device Part Number (Unique JTAG ID)– Device Revision (Readable by Host ARM)• Debug Interface Support– JTAG and cJTAG for ARM (Cortex-A8 andPRCM), PRU-ICSS Debug– Supports Device Boundary Scan– Supports IEEE 1500• DMA– On-Chip Enhanced DMA Controller (EDMA) hasThree Third-Party Transfer Controllers (TPTCs)and One Third-Party Channel Controller(TPCC), Which Supports up to 64 Programmable Logical Channels and EightQDMAChannels. EDMA is Used for:– Transfers to and from On-Chip Memories– Transfers to and from External Storage(EMIF, GPMC, Slave Peripherals)• Inter-Processor Communication (IPC)– Integrates Hardware-Based Mailbox for IPC andSpinlock for Process Synchronization BetweenCortex-A8, PRCM, and PRU-ICSS – Mailbox Registers that Generate Interrupts – Four Initiators (Cortex-A8, PRCM, PRU0,PRU1)– Spinlock has 128 Software-Assigned LockRegisters • Security– Crypto Hardware Accelerators (AES, SHA,RNG)– Secure Boot • Boot Modes– Boot Mode is Selected Through BootConfiguration Pins Latched on the Rising Edge of the PWRONRSTn Reset Input Pin • Packages:– 298-Pin S-PBGA-N298 Via Channel Package(ZCE Suffix), 0.65-mm Ball Pitch– 324-Pin S-PBGA-N324 Package(ZCZ Suffix), 0.80-mm Ball PitchAM335x处理器应用:• Gaming Peripherals• Home and Industrial Automation • Consumer Medical Appliances • Printers • Smart Toll Systems• Connected Vending Machines • Weighing Scales • Educational Consoles • Advanced Toys图1:AM335x处理器功能框图支持以太网,6LoWPAN RF 网络和更多的通用数据集中器参考设计TIDA-010032IPv6-based grid communications are becoming the standard choice in industrial markets and applications like smart meters and grid automation. The universal data concentrator design provides a complete IPv6-based network solution integrated with Ethernet backbone communication, 6LoWPAN RF mesh networking, RS-485 and more. The 6LoWPAN mesh networking addresses key concerns such as standard-basedinteroperability, reliability, security and long-distance connectivity. This design allows controlling and monitoring end devices remotely with a webserver accessible via Ethernet backbone communication. It also provides 3.3V and 5V voltage rails and various peripheral interfaces to extend to additional connectivity such as broadband power-line communication (PLC), cellular and Wi-Fi®.参考设计TIDA-010032主要特性:Implements universal data concentrator supporting Ethernet, 6LoWPAN mesh and RS-485 connectivity devicesAllows Internet of Things (IoT) services with web server and Ethernet backbone connectivityImplements 6LoWPAN RF mesh network protocols of 6LoWPAN, RPL, IPv6/ICMPv6 and UDPIntegrates with TI 15.4-Stack that supports frequency hopping (FH) and data encryption Fully compatible with the TIDA-010003 and TIDA-010024 end-node reference designs to provide a complete network solution Capable of extending to other connectivity devices such as broadband PLC, cellular and Wi-Fi参考设计TIDA-010032应用:Data concentrators Wireless communications图2:参考设计TIDA-010032外形图。
AM335x核心板
SOM335x 是 EMA 推出的一款基于 TI Cortex-A8 AM335x 系列处理器的低功耗工业级 ARM 核心板， 板载高达 512MB DDR3，4GB eMMC /1GB NAND 大容量存储。SOM335x 体积极小，通过两个 2x50pin B2B 插针连接器，将多路 UART/IIC/SPI/MMC、8 路 ADC、2 路 CAN、2 路千兆 MAC、24bit LCD 等外设 全部引出，系统集成度高，有效降低客户开发成本。提供完善的参考设计，大大降低客户的开发周期。
2
HMI335x 是广州英码科技发布的一款基于 SOM335x 设计的工业级主板，通过两路 2x50pin B2B 插针 连接器与 SOM335x 连接。基于 HMI335x，客户只需要关注于上层应用软件。
n n n 可根据客户需要，提供配套的产品外壳 9~24V宽压DC电源输入 串口资源 2x RS232（一个DB9接口、一个TJC3接口）
1
1xRS485（DB9接口） 1x 3.3V TTL UART（TJC3接口） n n n n n n n n n n n 1x DCAN 2.0B（DB9接口） 1x 千兆网口 1x WIFI Module（可选） 8x 12-bit ADC/TSC 1x 24bit LCD接口 2x USB 2.0 Host 2x SPI总线接口 1x 蜂鸣器 1x6-bit 启动拨码开关 1x14针JTAG标准接口 音频接口 1x双声道扬声器输出接口 1x双声道麦克风输入接口 n 按钮 1x复位按键 1x自定义按键 n n MMC/SD/SDIO/SDHC卡槽，最高支持32GByte 扩展功能接口 1x GPMC总线接口 2x USB 2.0 Host接口 2x USB 2.0 OTG接口 1x Reset信号线 1x MDIO总线 Linux 操作系统 Bootloader：u-boot 2011.9, 支持从 SD Card/eMMC/NAND 启动,支持串口和网络下载 内核版本：Linux3.2，文件系统：UBIFS 相关驱动：eMMC，CAN, Serial port, RTC, Ethernet, LCD, McSPI, EEPROM, Touch screen, MMC/SD , USB OTG, USB , Audio input/output 等 Android 操作系统 Android 版本：Android4.0 内核版本：Linux3.2 I-Android 工业控制套件： 支持 CAN 总线、RS232、RS485、I2C、GPIO 设备等设备接入
max3485中文资料
MAX3483, MAX3485, MAX3486, MAX3488, MAX3490以及MAX3491是用于RS-485与RS-422通信的3.3V，低功耗收发器，每个器件中都具有一个驱动器和一个接收器。
MAX3483和MAX3488具有限摆率驱动器，可以减小EMI，并降低由不恰当的终端匹配电缆引起的反射，实现最高250kbps的无差错数据传输。
MAX3486的驱动器摆率部分受限，可以实现最高2.5Mbps的传输速率。
MAX3485,MAX3490和MAX3491则可以实现最高10Mbps 的传输速率。
驱动器具有短路电流限制，并可以通过热关断电路将驱动器输出置为高阻状态，防止过度的功率损耗。
接收器输入具有失效保护特性，当输入开路时，可以确保逻辑高电平输出。
使用MAX3488, MAX3490和MAX3491可以实现全双工通信，而MAX3483，MAX3485与MAX3486则为半双工应用设计。
这篇文章介绍的就是MAX34852 芯片介绍2.1 主要特点半双工速率：10Mbps限摆率：NO接收允许控制：YES 关断电流：2 nA引脚数：82.2 引脚配置根据上图、上表可知：DE和RO为使能管脚。
DE为低电平、RE为低电平时为接收；DE 为高电平、RE为高电平时为发送；RO和DI为数据管脚。
RO为接收，DI为发送；因此我们经常将DE和RE直接连接，用一个IO口控制（见3.2 电路实现）。
3.1 应用场景工业控制局域网集成服务数字网络低功耗RS-485/RS-422收发器（我做的几个项目都是该功能）分组交换技术电信用于EMI敏感应用的收发器3.2 电路实现485是2线式，两个485接口的设备相连通过A、B两根线即可（也就是至少2个485芯片），连接方式如下图所示：我们使用MAX3485一般是用下图电路：从上图中我们可以看到：RO直接和TTL电平的UART_RX（或模拟串口的RX）相连，DI直接和TTL电平的UART_TX（或模拟串口的TX）相连，R34为1K。
Sigmastar SSC335 全功能开发板技术手册说明书
Sigmastar SSC335全功能开发板技术手册一、应用场合：1. 适用于开发以下产品：（1）200万/300万网络摄像机。
（2）300万抓拍摄像机。
（3）安防监控产品。
（4）网络音视频产品。
（5）低功耗快速启动摄像机。
（6）4G/WIFI无线传输产品。
（7）编码器。
（8）双路摄像机。
（9）运动相机。
（10）航拍摄像机。
（11）UVC相机。
2. 适用于学习linux平台、熟悉ARM开发的开发者。
3. 适用于需要熟悉sigmstar平台音视频编解码、图像处理、UVC相机、4G/WIFI无线传输的开发人员。
二、型号：CA-M3335AID-MAIN-V1三、产品特色：■主控芯片采用Sigamastar高性能多媒体处理器片上系统(SOC)，，内部集成A7、FPU、NEON，主频800MHZ。
■支持WDR、多级降噪及多种图像增强和矫正算法，为客户提供专业级的图像质量。
■采用标准的H.264/H.265 High Profile压缩算法，方便在窄带上实现高清晰的图像传输。
■最大支持300万编码.最高支持2304x1296@30帧、2048*1536@30帧、1920x1080@45帧H.264/H.265编码。
■内置1Gb DDR2。
■支持MIPI、USB Sensor输入、图像质量优异。
■支持双向语音对讲。
■支持ONVIF2.4标准协议，可对接海康、大华、雄迈等NVR。
■支持GB28181协议。
■支持手机监看。
■支持4G全网通：5模或者7模。
■支持WIFI：热点和STA模式。
■支持GPS、北斗定位。
■支持POE供电，功率13W，符合IEEE802.3af/at标准■支持二次开发。
■尺寸26*24mm，邮票孔。
方便做小型化产品。
■接口全，且与本公司其他主控、平台定义一致，适合兼容多款产品。
四、技术参数：五、产品外观及接口定义：J24：音频输入1.AIN0(左)2.音频地3.AIN1(右)J5：报警/485接口1.报警输出22.报警输出13. RS485正4. RS485负4. RS485_D+J15：SD 外接接口1. SD_DATA22. SD_DATA33. SD_CMD 4. 3.3V 5. SD_CLK J2：接POE 模块脚位接口定义主控pin脚接口类型电平功能描述说明1 SD_CDZ19 输入 3.3V SD卡插入检测低电平有效2 SD_DATA1 81 输入/输出 3.3V SD卡数据13 SD_DATA0 79 输入/输出 3.3V SD卡数据04 SD_CLK 77 输出 3.3V SD卡时钟50MHz5 GND 地数字地6 SD_CMD 78 输出 3.3V SD卡命令信号7 SD_DATA3 82 输入/输出 3.3V SD卡数据38 SD_DATA2 81 输入/输出 3.3V SD卡数据29 NC10 NC11 NC12 NC13 NC14 NC15 NC16 LINK_LAN 输入/输出 3.3V 网络连接状态指示输出高，网络连接成功连接网口RJ45绿灯17 ACT_LAN 输入/输出 3.3V 网络数据传输指示高/低切换：有数据传输，切换速度指示传输速度。
萃取柱内液_液两相流CFD_PBM模拟研究进展_李少伟
平衡方程及破碎与聚并模型方程等，见表 1. 2.1 流动方程 流体力学涉及的方程一般包括质量守恒方程和动 量守恒方程(即连续性方程和 NavierStokes 方程)， CFDPBM 两相流模拟也不例外 . 对萃取柱内的液 液两相 流，所用模拟方法一般是欧拉欧拉方法，即两相流体 都采用欧拉法进行描述，见式(1), (2)
料及涂料等众多行业， 是化学工程学科的重要研究对象. 但由于其复杂性，相关研究还很不成熟. 现代科学技术 的发展对传质分离过程提出了更高要求， 发展高效低能 耗的液 液分散、传质分离技术和设备，深入进行液 液分散体系的基础研究，成为化学工程学科十分迫切的 任务之一. 液液两相流涉及复杂的界面行为，其理论研究一 直是化工学科的一大难点. 近年来随着计算机技术的飞 速发展，计算流体力学(Computational Fluid Dynamics, CFD)模拟成为重要的研究手段， 它可揭示流体内部的流 动、混合等规律，提供两相流动、浓度分布、传质与反 应过程等的细节信息，成为实验研究的重要补充手段， 越来越多的学者开展了相关的研究工作. 当前两相流模拟研究主要可分为两大类， 一类是关 注液液两相界面的形状与形变的“真实”模拟，一类 是忽略界面形状信息的简化模拟. 在“真实”模拟中，将一定的相界面描述和捕捉手 段与计算流体力学相结合是主要方法. 目前已有多种方 法用于两相流“真实”模拟中，如 VOF 方法(Volume of Fluid Method)
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李少伟等： 萃取柱内液液两相流 CFD-PBM 模拟研究进展
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2
基本理论与方程
CFD-PBM 模拟所涉及的方程包括流动方程、群体
成，表示为式(5)，式中 BC(L, t)表示由于小尺寸液滴聚 并成为所关注尺寸的液滴而造成的数密度的增加， DC(L, t) 表示由于所关注尺寸的液滴与其他液滴聚并而 造成的数密度的减少，BB(L, t)表示由于大液滴破碎生成 所关注尺寸的液滴而造成的数密度的增加， DB(L, t)表示 由于所关注尺寸的液滴破碎而造成的数密度的减少. 在 只考虑二元聚并与破碎的情况下， 这 4 部分可表达为式
仪器分析课习题
仪器分析课习题第一章电磁辐射基础1对下列单位进行换算：（1）1.50ÅX射线的波数（cm-1）(6.66×107)（2）670.7nm锂线的频率（HZ）（4.47×1014)（3）3300cm-1波数的波长（nm）（3030）（4）Na5889.95Å相应的能量（eV）（2.11）2写出下列各种跃迁所需的能量范围（eV）（1）原子内层电子跃迁(1.2×102-1.2×106)（2）原子外层电子跃迁（6.2-1.7)（3）分子的电子跃迁（6.2-1.7)（4）分子振动能级跃迁（0.5-0.02)（5）分子转动能级跃迁(2×10-2-4×10-7)3某种玻璃的折射率为1.7000,求光在此玻璃介质中的传播速度.(1.76×1010cm/s)4辐射通过空气与玻璃界面时,其反射损失大约有多少?(～4%)5解释下列名词(1)单重态与三重态(2)原子荧光与分子荧光(3)选择跃迁与禁阻跃迁(4)激发电位与共振电位6阐明光谱项符号和能级图的意义7用光谱项符号写出Mg2852Å(共振线)的跃迁(31S0-31P1)8下列哪种跃迁不能产生,为什么?(1)31S0-31P1(2)31S-31D2(3)33P2-33D3(4)43S1-43P1(31S-31D2)第二章原子发射光谱分析法1解释下列名词(1)激发电位和电离电位;(2)原子线和离子线;(3)共振线和共振电位;(4)等离子体;(5)谱线的自吸.2计算Cu3273.96Å和Na5895.92Å的激发电位(eV)(3.78,2.10)3谱线自吸对光谱分析有什么影响?4说明影响原子发射光谱分析中谱线强度的主要因素.5阐述原子发射光谱定性分析的原理,怎样选择摄谱法定性分析时的主要工作条件.6光谱定性分析摄谱时,为什么要用哈德曼光栏?7推导摄谱法原子发射光谱定量分析的基本关系式.8选择分析线应根据什么原则?9下表中列出铅的某些分析线,若测定水中痕量铅应选用哪条谱线,当试样中含量为0.1%时是否仍选用此线.说明理由铅线波长/Å激发电位/eV2833.0714.372802.0015.742873.3215.632663.1715.972393.7916.5010说明选择内标元素及内标线的原则?11说明缓蚀剂在矿石定量分析中所起的作用?12采用K4047.20Å作分析线时,受Fe4045.82Å和弱氰带的干扰,可用何种物质消除此干扰?13为什么在碳电极直流电弧光源中采用惰性气氛?14分析下列试样应选用什么光源:(1)矿石的定性、半定量；(2)合金中的铜（～x%）;(3)钢中的锰（0.0x-0.X%）;(4)污水中的Cr.Mn.Cu.Fe.V.Ti等(ppm-x%).15分析下列试样时应选用什么类型的光谱仪:(1)矿石的定性、半定量；(2)高纯Y2O3中的稀土杂质元素;(3)卤水中的微量铷、铯.16说明乳剂特性曲线的制作及其在光谱定性和定量分析中的作用.17简述ICP光源的特点及应用.18试比较摄谱法与光电法.19绘出原子发射光谱仪的方框图,并指出各部件的具体名称及主要作用.20当试样量很少而又必须进行多元素测定时,应选用下列那种方法:(1)单道ICP-AES;(2)原子吸收光谱法;(3)摄谱法原子发射光谱法21若光栅刻痕为1200条/mm,当入射光垂直照射时,求3000Å波长光的一级衍射角.(21.10)22当一级光谱波长为5000Å时,其入射角为60°,反射角(衍射角)为-40°,此光栅的刻痕数应为多少条/mm?(446条/mm)23有某红外光栅(72条/mm),当入射角为50°,反射角为20°时,其一级和二级光谱的波长为多少(um)?(15.4,7.7)24当某光栅(1250条/mm)的焦距为1.6m时,计算其一级和二级光谱的倒线色散率.(5Å/mm,2.5Å/mm)25若光栅宽度为50mm,刻痕数为1200条/mm,此光栅的理论分辨率应为多少?(60000)26上述光栅能否将铌3094.18Å与铝3092.71Å分开?为什么?27试对棱镜光谱与光栅光谱进行比较.28若光谱工作范围为200-400nm,应选用什么材料制作棱镜和透镜,为什么?第三章原子吸收与原子荧光光谱法1试比较原子吸收与分子吸收光谱法.2解释下列名词:(1)多普勒变宽(2)自然宽度(3)压力变宽(4)振子强度(5)光谱通带3计算在火焰温度为3000K时,Na5890Å谱线的激发态与基态原子数的比值(Pj/P0=2).(6×10-4)4原子吸收亮度计的单色器倒线色散率为16Å/mm,欲测定Si2516.1Å的吸收值,为了消除多重线Si2514.3Å和Si2519.2Å的干扰,应采取什么措施?5采用那些措施才能检测到原子吸收信号,并说明其理由.6简述常用原子化器的类型及其特点.7测定人发中硒时,应选用何种火焰,并说明其理由.8分析矿石中的锆时,应选用何种火焰,并说明其理由.9怎样能使空心阴极灯处于最佳工作状态?如果不处于最佳状态时,对分析工作有什么影响?10火焰的高度和气体的比例对被测元素有什么影响,试举例说明.11说明原子吸收光谱中产生背景的主要原因及影响.12如何用氘灯法校正背景,此法尚存在什么问题?13什么是原子吸收光谱分析中的化学干扰?用哪些方法可消除此类干扰?14在测定血清中钾时,先用水将试样稀释40倍,再加入钠盐至800ug/mL.试解释此操作的理由,并说明标准溶液应如何配制?15指出下列原子荧光跃迁的类型(共振、非共振)（1）Cu3274Å(42S1/2-42P1/2)（2）Cd2288Å(51S0-51P1)（3）Sn3034Å(53P1-53P)（4）As2350Å(42S3/2-42P1/2)16试从产生原理上对原子荧光与原子发射光谱进行比较.17试从仪器部件及光路结构对原子与原子荧光仪进行比较.18欲测定下述物质,应选用哪一种原子光谱法,并说明其理由:(1)血清中锌和镉(Zn2ug/ml,Cd0.003ug/ml）;(2)鱼肉中汞的测定（xppm）；(3)水中砷的测定(0.xppm)；(4)矿石中La、Ce、Pr、Nd、Sm的测定(0.00x-0.x%)；(5)废水中Fe、Mn、Al、Ni、Co、Cr的测定(ppm-0.x%)。
AM335x Sitara
ProductFolderSample &BuyTechnical Documents Tools &SoftwareSupport &Community Reference DesignAM3359,AM3358,AM3357,AM3356,AM3354,AM3352ZHCS488H –OCTOBER 2011–REVISED MAY 2015AM335x Sitara™处理器1器件概述中的PRU-ICSS 、AVS 、和DVFS 列表项1.1特性•8KB 带有单位检错（奇偶校验）的指令RAM •高达1GHz Sitara™ARM ®Cortex ®-A832位精简指令集计算机(RISC)处理器•8KB 带有单位检错（奇偶校验）的数据RAM –NEON™单指令流多数据流(SIMD)协处理器•具有64位累加器的单周期32位乘法器–32KB L1指令和32KB 带有单位检错（奇偶校•增强型GPIO 模块为外部信号提供移入/移出验）的数据缓存支持以及并行锁断–带有错误校正码(ECC)的256KB L2缓存–12KB 带有单位检错（奇偶校验）的共享RAM –176KB 片载启动ROM –三个120字节寄存器组，可被每个PRU 访问–64KB 专用RAM –用于处理系统输入事件的中断控制器模块(INTC)–仿真和调试-JTAG–用于将内部和外部主机连接到PRU-ICSS 内部资源的本地互连总线–中断控制器（最多可控制128个中断请求）–PRU-ICSS 内的外设：•片上存储器（共享L3RAM ）•一个带有流控制引脚的通用异步收发器–64KB 通用片上存储器控制器(OCMC)随机存取(UART)端口，支持高达12Mbps 的数据速率存储器(RAM)•一个增强型捕捉(eCAP)模块–可访问所有主机•两个MII 以太网端口，支持工业以太网（例如–支持保持以实现快速唤醒EtherCAT ）•外部存储器接口(EMIF)•一个MDIO 端口–mDDR(LPDDR)、DDR2、DDR3、DDR3L 控制•电源、复位和时钟管理(PRCM)模块器：–控制待机模式和深度休眠模式的进入和退出•mDDR ：200MHz 时钟（400MHz 数据速率）–负责休眠排序、电源域关闭排序、唤醒排序和电•DDR2：266MHz 时钟（532MHz 数据速率）源域打开排序•DDR3：400MHz 时钟（800MHz 数据速率）–时钟•DDR3L ：400MHz 时钟（800MHz 数据速•集成了15MHz 至35MHz 的高频振荡器，用率）于为各种系统和外设时钟生成参考时钟•16位数据总线•支持子系统和外设的单独时钟使能和禁用控•1GB 全部可寻址空间制，帮助降低功耗•支持一个x16或两个x8存储器件配置•五个用于生成系统时钟（MPU 子系统、DDR –通用存储器控制器(GPMC)接口、USB 、外设[MMC 和SD 、UART 、•灵活的8位和16位异步存储器接口，具有多SPI 、I 2C]、L3、L4、以太网、GFX达七个片选（NAND 、NOR 、复用NOR 和[SGX530]以及LCD 像素时钟）的ADPLL SRAM ）–电源•使用BCH 代码，支持4位、8位或16位•两个不可切换的电源域（实时时钟[RTC]和ECC唤醒逻辑[WAKEUP]）•使用海明码来支持1位ECC •3个可切换电源域（MPU 子系统–错误定位器模块(ELM)[MPU]，SGX530[GFX]，外设和基础设施•与GPMC 一起使用时，可通过BCH 算法确[PER]）定所生成的伴随多项式中数据错误的地址•执行SmartReflex™2B 类，基于芯片温度、•根据BCH 算法，支持4位、8位和16位每过程变化和性能实现内核电压调节（自适应电512字节块错误定位压调节[AVS]）•可编程实时单元子系统和工业通信子系统(PRU-•动态电压频率缩放(DVFS)ICSS)•实时时钟(RTC)–支持EtherCAT ®、PROFIBUS 、PROFINET 、–实时日期（年、月、日和星期几）和时间（小EtherNet/IP™等协议时、分钟和秒）信息–2个可编程实时单元(PRU)–内部32.768kHz 振荡器，RTC 逻辑和1.1V 内部•32位可运行在200MHz 的负载/存储RISC 处理低压降稳压器(LDO)器–独立的加电复位(RTC_PWRONRSTn)输入AM3359,AM3358,AM3357,AM3356,AM3354,AM3352ZHCS488H–OCTOBER2011–REVISED –用于外部唤醒事件的专用输入引脚(EXT_•DMTIMER1是用于操作系统(OS)节拍的WAKEUP)1ms定时器–可编程警报可用于生成PRCM内部中断（用于唤•DMTIMER4–DMTIMER7为引脚输出醒）或Cortex-A8内部中断（用于事件通知）–一个安全装置定时器–可编程警报可与外部输出(PMIC_POWER_EN)–SGX5303D图形引擎一起用来使能电源管理IC，从而恢复非RTC电•拼图架构每秒可提供最多2000万个多边形源域•通用可扩展着色引擎(USSE)是一款包含像素•外设和顶点着色功能的多线程引擎–多达两个带有集成PHY的USB2.0高速OTG•超过Microsoft VS3.0、PS3.0和OGL2.0的端口高级着色功能集–多达两个工业千兆位以太网MAC（10、100和•Direct3D Mobile、OGL-ES1.1和2.0、1000Mbps）OpenVG1.0以及OpenMax的行业标准API •集成开关支持•每个MAC都支持MII、RMII、RGMII和•精细的任务切换、负载均衡和电源管理MDIO接口•高级几何DMA驱动型操作，最大程度地减少•以太网MAC和交换机可独立于其它功能运行CPU交互•IEEE1588v2精密时间协议(PTP)•可编程高质量图像防锯齿–多达2个控制器局域网(CAN)端口•用于统一存储器架构中操作系统运行的完全虚•支持CAN版本2部分A和B拟化存储器寻址–多达两个多通道音频串行端口(McASP)–LCD控制器•高达50MHz的发送和接收时钟•多达24位数据输出；每像素8位(RGB)•每个具有独立TX和RX时钟的McASP端口•分辨率最高可达2048×2048（具有最高对应多达四个串行数据引脚126MHz的像素时钟）•支持时分多路复用(TDM)、内部IC声音•集成LCD接口显示驱动器(LIDD)控制器(I2S)和类似格式•集成光栅控制器•支持数字音频接口传输（SPDIF、IEC60958-•集成DMA引擎可通过中断或固件定时器从外1和AES-3格式）部帧缓冲器获取数据，无需加重处理器的负担•用于发送和接收的FIFO缓冲器（256字节）•512字深内部FIFO–最多6个UART•支持的显示类型：•所有UART支持IrDA和CIR模式–字符显示器-使用LIDD控制器对这些显•所有UART支持RTS和CTS流量控制示器进行编程•UART1支持完整的调制解调器控制–无源矩阵LCD显示-使用LCD光栅显示控制器来为到无源显示的持续图形刷新提供–多达两个主从McSPI串行接口定时和数据•最多2个芯片选择–有源矩阵LCD显示-使用外部帧缓冲器空•高达48MHz间和内部DMA引擎来驱动到控制面板的–多达三个MMC、SD和SDIO端口流数据•1位、4位和8位MMC、SD和SDIO模式–12位逐次逼近寄存器(SAR)ADC •MMCSD0具有专用于1.8V或3.3V操作的电•每秒采集200K个样本源轨•可从8:1模拟开关复用的八个模拟输入中任意•高达48MHz的数据传输速率选择输入•支持卡检测和写保护•可配置为用作4线、5线或8线电阻式触摸•符合MMC4.3、SD和SDIO2.0规范屏控制器(TSC)接口–多达三个I2C主从接口–多达三个32位eCAP模块•标准模式（高达100kHz）•可配置为三个捕捉输入或者三个备用PWM输•快速模式（高达400kHz）出–多达四组通用I/O(GPIO)引脚–多达三个增强型高分辨率PWM模块(eHRPWM)•每组包含32个GPIO引脚（与其他功能引脚•具有时间和频率控制功能的16位专用时基计复用）数器•GPIO引脚可作为中断输入（每组多达两个中•可配置为6个单端，6个双边对称，或者3断输入）个双边不对称输出–多达三个外部直接存储器访问(DMA)事件输入也–多达3个32位增强型正交编码脉冲(eQEP)模可用作中断输入块–八个32位通用定时器•器件标识AM3359,AM3358,AM3357,AM3356,AM3354,AM3352 ZHCS488H–OCTOBER2011–REVISED MAY2015–包含电子熔丝组(FuseFarm)，其中一些位厂家可•处理器间通信(IPC)编程–集成了基于硬件的IPC邮箱，以及用于Cortex-A8、PRCM和PRU-ICSS之间进程同步的•生产IDSpinlock•器件部件号（唯一的JTAG ID）•生成中断的邮箱寄存器•设备版本（可由主机ARM读取）–4个初启程序(Cortex-•调试接口支持A8，PRCM，PRU0，PRU1)–用于ARM（Cortex-A8和PRCM）和PRU-•自旋锁具有128个软件指定的锁寄存器ICSS调试的JTAG和cJTAG•安全性–支持器件边界扫描–密码硬件加速器(AES，SHA，PKA，RNG)–支持IEEE1500•启动模式•DMA–通过锁存在PWRONRSTn输入引脚上升沿上的–片上增强型DMA控制器(EDMA)搭载三个第三启动配置引脚来选择启动模式方传送控制器(TPTC)和一个第三方通道控制器(TPCC)，支持多达64个可编程逻辑通道和8个•封装：QDMA通道。
如何选择模拟开关
如何选择模拟开关模拟开关模拟开关和多路转换器的作用主要是用于信号的切换。
目前集成模拟电子开关在小信号领域已成为主导产品，与以往的机械触点式电子开关相比，集成电子开关有许多优点，例如切换速率快、无抖动、耗电省、体积小、工作可靠且容易控制等。
但也有若干缺点，如导通电阻较大，输入电流容量有限，动态范围小等。
因而集成模拟开关主要使用在高速切换、要求系统体积小的场合。
在较低的频段上f<10MHz），集成模拟开关通常采用CMOS工艺制成：而在较高的频段上（f>10MHz），则广泛采用双极型晶体管工艺。
如何选择模拟开关选择开关时需考察以下指标：通道数量集成模拟开关通常包括多个通道。
通道数量对传输信号的精度和开关切换速率有直接的影响，通道数越多，寄生电容和泄漏电流就越大。
因为当选通一路时，其它阻断的通道并不是完全断开，而是处于高阻状态，会对导通通道产生泄漏电流，通道越多，漏电流越大，通道之间的干扰也越强。
泄漏电流一个理想的开关要求导通时电阻为零，断开时电阻趋于无限大，漏电流为零。
而实际开关断开时为高阻状态，漏电流不为零，常规的CMOS漏电流约1nA。
如果信号源内阻很高，传输信号是电流量，就特别需要考虑模拟开关的泄漏电流，一般希望泄漏电流越小越好。
导通电阻导通电阻的平坦度与导通电阻一致性导通电阻会损失信号，使精度降低，尤其是当开关串联的负载为低阻抗时损失更大。
应用中应根据实际情况选择导通电阻足够低的开关。
必须注意，导通电阻的值与电源电压有直接关系，通常电源电压越大，导通电阻就越小，而且导通电阻和泄漏电流是矛盾的。
要求导通电阻小，则应扩大沟道，结果会使泄漏电流增大。
导通电阻随输入电压的变化会产生波动，导通电阻平坦度是指在限定的输入电压范围内，导通电阻的最大起伏值△RON=△RONMAX—△RONMI N。
它表明导通电阻的平坦程度，△RON应该越小越好。
导通电阻一致性代表各通道导通电阻的差值，导通电阻的一致性越好，系统在采集各路信号时由开关引起的误差也就越小。
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MAX335
______________Ordering Information
PART MAX335CNG MAX335CWG MAX335C/D MAX335ENG MAX335EUG MAX335EWG MAX335MRG TEMP RANGE 0°C to +70°C 0°C to +70°C 0°C to +70°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -55°C to +125°C PIN-PACKAGE 24 Narrow Plastic DIP 24 Wide SO Dice* 24 Narrow Plastic DIP 24 TSSOP 24 Wide SO 24 Narrow CERDIP**
— – VL = +15V, VDIN, VSCLK, V – CS = 11V
SYMBOL
CONDITIONS
MIN -15
TYP
MAX 15
UNITS V Ω
TA = +25°C TA = +25°C TA = +25°C TA = +25°C TA = +25°C TA = +25°C TA = +25°C -1 -20 -1 -20 -1 -20 -1 -20 -2 -40 -2 -40 2.4 11
__________________Pin Configuration
TOP VIEW
NO0
NO7
SCLK V+ DIN
1 2 3 4 5 6 7 8 9
24 CS 23 VL 22 DOUT
COX335
21 V20 NO7 19 COM7 18 NO6 17 COM6 16 NO5 15 COM5 14 NO4 13 COM4
100 0.002 0.002 0.002 0.002 0.01 0.01
150 200 1 20 1 20 1 20 1 20 2 40 2 40
Serial Controlled, 8-Channel SPST Switch MAX335
ABSOLUTE MAXIMUM RATINGS
Voltages Referenced to VV+...........................................................................................44V GND .......................................................................................25V VL .....................................................(GND - 0.3V) to (V+ + 0.3V) SCLK, CS, DIN, DOUT, NO_, COM_ ...............V- -2V to V+ +2V or 30mA, whichever occurs first Continuous Current (any terminal) .......................................30mA Peak Current, NO or COM (pulsed at 1ms, 10% duty cycle MAX) ...............................00mA Note 1: All leads are soldered or welded to PC boards. Continuous Power Dissipation (TA = +70°C) (Note 1) Narrow Plastic DIP (derate 13.33mW/°C above +70°C)1067mW Wide SO (derate 11.76mW/°C above +70°C) .................941mW Narrow CERDIP (derate 12.50mW/°C above +70°C) .....1000mW TSSOP (derate 12.2mW/°C above +70°C)...........................30mA Operating Temperature Ranges MAX335C_ _ ............................................................0°C to +70°C MAX335E_ _ .........................................................-40°C to +85°C MAX335MRG.......................................................-55°C to +125°C Storage Temperature Range ..............................-65°C to +160°C Lead Temperature (soldering, 10sec)...............................+300°C
19-0220; Rev 3; 10/03
Serial Controlled, 8-Channel SPST Switch
_______________General Description
The MAX335 analog switch with serial digital interface offers eight separately controlled single-pole-singlethrow (SPST) switches. All switches conduct equally in either direction, and on-resistance (100 W) is constant over the analog signal range. These CMOS switches can operate continuously with power supplies ranging from ±4.5V to ±20V and handle rail-to-rail analog signals. Upon power-up, all switches are off, and the internal serial and parallel shift registers are reset to zero. The MAX335 is equivalent to two DG211 quad switches but controlled by a serial interface. The interface is compatible with the Motorola SPI interface standard. Functioning as a shift register, this serial interface allows data (at DIN) to be locked in synchronous with the rising edge of clock (SCLK). The shift register's output (DOUT) enables several MAX335s to be daisy chained.
ELECTRICAL CHARACTERISTICS
(VL = +5V ±10%, V+ = 15V, V- = -15V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SWITCH Analog Signal Range On-Resistance VANALOG RON TA = TMIN to TMAX VCOM = ±10V, INO = 1mA VCOM = -14V, VNO = +14V VCOM = -14V, VNO = +14V VCOM = -14V, VNO = +14V VCOM = -14V, VNO = +14V VCOM = VNO = +14V COM On-Leakage Current ICOM(ON) VCOM = VNO = -14V DIGITAL I/O DIN, SCLK, CS Input Logic Threshold High – DIN, SCLK, CS Input Logic Threshold Low DIN, SCLK, CS Input Current Logic High – DIN, SCLK, CS Input Current Logic Low DOUT Output Voltage Logic High VIH VIL IINH IINL VDOUT VL = +5V VL = +15V VL = +5V VL = +15V VDIN, VSCLK, VCS = 2.4V
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.