2305-2-00-01-00-00-07-0中文资料
备战2023年新高考考向追踪10-正午太阳高度变化(课件)
• 为了更好地保证各楼层都有良好的采光，
楼与楼之间保持适当距离
• 以我国为例，南楼高度为h，该地冬至日
正午太阳高度为H，则最小楼间距L为
N
L=h x cot H
03
07.计算太阳能热水器的安装角度
• 为了更好地利用太阳能，应不断调整太阳 能热水器与地平面之间的倾角，使太阳光 与集热板成直角
• 集热板与地平面之间的夹角(a)和当天的 正午太阳高度角(H)互余，即a+H= 90° 时集热效果最佳
8．该地纬度可能为( )
A．4°N
B．22.5°N
C．30°N
D．45°N
9．当该地正午影长率为a值时
，当地正值一年中( )
A．夜长最短的一天
B．日出最晚的一天
C．气温最高的月份
D．寒潮活动最频繁的季节
为节能减排，河北省邯郸市新建区全部安装可以通过电脑调控太阳能板 与水平面夹角的路灯和路口红绿灯。下图为拍摄的邯郸市红绿灯照片。读 图完成10～11题。
H=26°34′
90°
北京-40°N
S
03
阅读材料，完成下列问题。 材料 上图为云南省略图。下图为上图中甲 地与我国某中学正午太阳高度角之差的年变 化示意图。 • 计算该中学的纬度，说出P至Q时段甲地与
该中学直立物正午日影的朝向及长短变化。 • 【答案】4.20°N。 • 甲地：影子朝北，由短变长。 • 该中学：影子朝南，由长变短。
与纬线之间成30-60°的夹角。下图为36°N某城镇街道与纬线关系图。据此
完成下列5-6题。
5.在春分日，不考虑任何遮挡问题，阳光能从图示的
窗户中直接射入室内的时段大约是A．6～15时
B．9～18时
C．12～15时
PCF8575中文资料
数据表PCF8575远程16位I 2 C总线I/O扩展器内容简介1．特征2．一般描述3．订货信息4．框图5．引脚6．I 2 C总线的特点6．1．位传输6．2．启停条件6．3．系统配置6．4．应答7．功能描述7．1．双向I/O7．2．寻址7．3．读取端口（输入模式）7．4．写入端口（输出模式）7．5．中断8．极限值9．处理10．特点11．I 2 C总线的时序特性12．设备的保护13．封装外形14．焊接14．1焊接表面贴装封装介绍14．2回流焊接14．3波动焊接14．4手工焊接14．5表面安装IC封装的波动和回流焊接方法的适用性15．定义16．支持应用程序17．购买飞利浦I 2 C组件1．特征工作电源电压2.5至5.5 V最大低待机电流消耗10µI 2 C总线并行端口扩展器快至400 kbits/s的I 2 C总线开漏中断输出16位远程I/O端口的I 2 C总线兼容大多数微控制器具有高电流锁存输出驱动能力可直接驱动LED地址由3个硬件地址引脚使用多达8个设备ssop24包装2．一般描述PCF8575是硅CMOS电路。
它提供了通用的远程I/O 扩展对于大多数的微控制器的家庭通过两线双向总线（I 2 C 总线）。
该设备有一个双向16位的接口和一个I 2 C总线接口。
PCF8575具有低电流消耗，包括锁存输出与LED直接驱动高电流驱动能力。
它还具有一个中断线（INT），它可以连接到中断逻辑的微控制器。
通过在这条线上发送中断信号，远程I / O可以通知单片机如果有接口输入的数据而不必通过I 2 C总线通信。
这意味着，PCF8575是I 2 C总线从发送器/接收器。
从PCF8575传输每一个数据必须由偶数个字节组成，第一个字节为P07至P00和第二个字节为P17至P10。
第三个为P07至P00等。
3．订货信息型号：PCF8575TS包装：“名称：SSOP24。
”“描述：塑料收缩小外形封装；24引线；机身宽度5.3毫米。
MP2307中文资料
ELECTRICAL CHARACTERISTICS
VIN = 12V, TA = +25°C, unless otherwise noted.
Parameter
© 2006 MPS. All Rights Reserved.
元器件交易网
TM
MP2307 – 3A, 23V, 340KHz SYNCHRONOUS RECTIFIED STEP-DOWN CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS
© 2006 MPS. All Rights Reserved.
元器件交易网
TM
MP2307 – 3A, 23V, 340KHz SYNCHRONOUS RECTIFIED STEP-DOWN CONVERTER
PACKAGE REFERENCE
TOP VIEW
BS 1 IN 2 SW 3 GND 4
100
95 90 VIN = 12V
VIN = 5V
85
80
VIN = 23V
75
70
65
60
55
50
0.1
1.0
10
LOAD CURRENT (A)
MP2307_EC01
MP2307 Rev. 1.7
1
3/14/2006
MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.
数学六年级下册第34课时《鸽巢问题-例2》课件
课堂小结 通过这节课的学习， 你有什么收获?
鸽巢问题的一般规律，可以用假设 法，列式计算
a÷n=b……c（c≠0）， 至少数=b+1。
没有余数：至少数=b
作业：
(1)把17支铅笔放进4个文具盒里，至少 有一个文具盒里放几支？
(2)幼儿园里有80个小朋友，各种玩具共 有330件。把这些玩具分给小朋友，是否 有人会得到5件或5件以上的玩具？
把两种颜色看成两个抽屉，正方体的6个 面看成分放的物体，至少3个面要涂上相同的 颜色。
6÷2=3（个）
（教材P71 练习十三第4题）
4.把红、蓝、黄三种颜色的筷子各 3根混在一起。如果让你闭上眼睛， 每次最少拿出几根才能保证一定有 2根同色的筷子？如果要保证有2双 不同色的筷子呢？（指一双筷子为 其中一种颜色，另一双筷子为另一 种颜色。）
13÷12＝1（人）……1（人） 1＋1＝2（人）
（教材P71 练习十三2） 2.张叔叔参加飞镖比赛，投了5镖，
成绩是41环。张叔叔至少有一镖不低于9 环。为什么？
41÷5=8（环）……1（环） 8+1=9（环）
（教材P71 练习十三第3题）
3.给一个正方体木块的6个面分别涂上蓝、黄两种颜 色。不论怎么涂至少有3个面涂的颜色相同。为什么？
人教版六年级数学下册
数学广角—鸽巢问题
第 2 课时
知识回顾：
把n+1个物体放进n个抽屉，能得到 什么结论？
尝试探究：
例2 ： 把7本书放在3个抽屉里，不管怎么放，
总有一个抽屉里至少放进3本书。为什么？
例2 ： 把7本书放在3个抽屉里，不管怎么放， 总有一个抽屉里至少放进3本书。为什么？
自主探究： 用自己喜欢的、能理解的方法进行说理。
ASCII码表(0-255)
ASCII表(0-255)注：" "为不支持字符二进制八进制十进制十六进制缩写/字符解释000000000000NUL(null)空字符000000011101SOH(start of headling)标题开始000000102202STX(start of text)正文开始000000113303ETX(end of text)正文结束000001004404EOT(end of transmission)传输结束000001015505ENQ(enquiry)请求000001106606ACK(acknowledge)收到通知000001117707BEL(bell)响铃0000100010808BS(backspace)退格0000100111909HT(horizontal tab)水平制表符0000101012100A LF(NL line feed, new line)换行键0000101113110B VT(vertical tab)垂直制表符0000110014120C FF(NP form feed, new page)换页键0000110115130D CR(carriage return)回车键0000111016140E SO(shift out)不用切换0000111117150F SI(shift in)启用切换00010000201610DLE(data link escape)数据链路转义00010001211711DC1(device control 1)设备控制1 00010010221812DC2(device control 2)设备控制2 00010011231913DC3(device control 3)设备控制3 00010100242014DC4(device control 4)设备控制4 00010101252115NAK(negative acknowledge)拒绝接收00010110262216SYN(synchronous idle)同步空闲00010111272317ETB(end of trans. block)传输块结束00011000302418CAN(cancel)取消00011001312519EM(end of medium)介质中断0001101032261A SUB(substitute)替补0001101133271B ESC(escape)溢出0001110034281C FS(file separator)文件分割符0001110135291D GS(group separator)分组符0001111036301E RS(record separator)记录分离符0001111137311F US(unit separator)单元分隔符00100000403220(space)空格00100001413321!00100010423422" 00100011433523# 00100100443624$ 00100101453725% 00100110463826& 00100111473927' 00101000504028( 00101001514129) 0010101052422A* 0010101153432B+ 0010110054442C, 0010110155452D-0010111056462E. 0010111157472F/ 001100006048300 001100016149311 001100106250322 001100116351333 001101006452344 001101016553355 001101106654366 001101116755377 001110007056388 001110017157399 0011101072583A: 0011101173593B; 0011110074603C< 0011110175613D= 0011111076623E> 0011111177633F? 010000001006440@ 010000011016541A 010000101026642B 010000111036743C 010001001046844D 010001011056945E 010001101067046F010001111077147G 010010001107248H 010010011117349I 01001010112744A J 01001011113754B K 01001100114764C L 01001101115774D M 01001110116784E N 01001111117794F O 010100001208050P 010100011218151Q 010100101228252R 010100111238353S 010101001248454T 010101011258555U 010101101268656V 010101111278757W 010110001308858X 010110011318959Y 01011010132905A Z 01011011133915B[ 01011100134925C\ 01011101135935D] 01011110136945E^ 01011111137955F_ 011000001409660` 011000011419761a 011000101429862b 011000111439963c 0110010014410064d 0110010114510165e 0110011014610266f 0110011114710367g 0110100015010468h 0110100115110569i 011010101521066A j 011010111531076B k011011001541086C l011011011551096D m011011101561106E n011011111571116F o0111000016011270p0111000116111371q0111001016211472r0111001116311573s0111010016411674t0111010116511775u0111011016611876v0111011116711977w0111100017012078x0111100117112179y011110101721227A z011110111731237B{011111001741247C|011111011751257D}011111101761267E~011111111771277F DEL(delete)删除二进制八进制十进制十六进制缩写/字符解释1000000020012880š10000001201129811000001020213082Ś1000001120313183ŗ1000010020413284ś1000010120513385…1000011020613486Ŝ1000011120713587ŝ1000100021013688Ř1000100121113789‟100010102121388AŔ100010112131398Bş100011002141408CŒ100011012151418D100011102161428EŽ100011112171438F据链路转义10010000220144901001000122114591‘1001001022214692’1001001122314793“1001010022414894”1001010122514995Ş1001011022615096–1001011122715197—1001100023015298ř1001100123115399Ţ100110102321549Aŕ100110112331559BŠ100111002341569Cœ100111012351579D100111102361589Ež100111112371599FŖ10100000240160A0 (space)半角空格10100001241161A1¡10100010242162A2¢10100011243163A3£10100100244164A4¤10100101245165A5¤10100110246166A6¥10100111247167A7§10101000250168A8¨10101001251169A9¦10101010252170AA§10101011253171AB¨10101100254172AC©10101101255173ADª10101110256174AE«10101111257175AF¬10110000260176B0©10110001261177B1ª10110010262178B2二次方10110011263179B3®三次方10110100264180B4¯10110101265181B5°10110110266182B6±10110111267183B7«10111000270184B8²10111001271185B9³10111010272186BA´10111011273187BBµ10111100274188BC¶10111101275189BD·10111110276190BE¸10111111277191BF¹11000000300192C0º11000001301193C1»11000010302194C2¼11000011303195C3½11000100304196C4¾11000101305197C5¿11000110306198C6À11000111307199C7Á11001000310200C8Â11001001311201C9Ã11001010312202CAÄ11001011313203CBÅ11001100314204CCÆ11001101315205CDÇ11001110316206CEÈ11001111317207CFÉ11010000320208D0Ê11010001321209D1Ë11010010322210D2Ì11010011323211D3Í11010100324212D4Î11010101325213D5Ï11010110326214D6Ð11010111327215D7¬11011000330216D8Ñ11011001331217D9Ò11011010332218DAÓ11011011333219DBÔ11011100334220DCÕ11011101335221DDÖ11011110336222DE×11011111337223DFØ11100000340224E011100001341225E1®11100010342226E2Ù11100011343227E3Ú11100100344228E4Û11100101345229E5Ü11100110346230E6Ý11100111347231E7Þ11101000350232E8¯11101001351233E9°11101010352234EA±11101011353235EBß11101100354236EC²11101101355237ED³11101110356238EEà11101111357239EFá11110000360240F0â11110001361241F1ã11110010362242F2´11110011363243F3µ11110100364244F4ä11110101365245F5å11110110366246F6æ11110111367247F7¶11111000370248F8ç11111001371249F9·11111010372250FA¸11111011373251FBè11111100374252FC¹11111101375253FDé11111110376254FEê11111111377255FFë。
欧姆龙PLC编程手册(中文)07
CPM2AH CPU单元
最多可以连接3个扩展单元，包括扩展I/O单元
CPM1A-20EDR1
CPM1A-20EDT
CPM1A-AD041
扩展
扩展 I/O单元
4模拟量
4路模拟量输入
注： 1．CPM1A/CPM2A最多只可以连1台CPM1A-AD041和1台其它的扩展单元或扩 展I/O单元。
项目 输入点数 输入信号范围
MOV 指令
写入量程控制字 读出转换数据
模拟量输入单元
通道(n+1) 通道(n+2) 通道(m+1) 通道(m+2) 通道(m+3) 通道(m+4)
量程控制字
模拟量输入1 转换数据
模拟量输入2 转换数据 模拟量输入3 转换数据
模拟量输入4 转换数据
‘m’为分配给CPU单元或前一个扩展单元或扩展I/O 单元的最后一个输入通道，‘n’为分配给CPU单元或 前一个扩展单元或扩展I/O单元的最后一个输出通道
2．一旦设定好量程控制字，在CPU单元上电期间不能再改变设定。如需改 变设定，必须将CPU单元断电后重新上电。
3．对于不使用的输入，将输入通道设置为OFF，并且将电压输入端子VIN 和COM短路。
模拟输入设备的配线 CPM1A-AD041端子排列
IN
CH
I IN1 V IN2 COM2 I IN3 V IN4 COM4 AG
189C(6300) 1770(6000)
0000(0)
-0.25 V
0V
FED4(-300)
5 V 5.25 V
1～5 V
1～5V的电压输入对应于十六进制数0000～1770(0000～6000)。完整的数据输出范围是FED4～189C (-300～6300)。输入电压在0.8到1V之间时使用补码来表示转换数据。如果输入的电压小于0.8V时，断线检测功 能将被激活并且转换的数据为8000。
FC游戏金手指
《魂斗罗》真
00AE-01-05 无敌
0032-01-30 命
00AA-01-00 普通子弹
00AA-01-01 M弹
00AA-01-02 F弹
00AA-01-03 S弹
00AA-01-04 L弹
《魂斗罗2代》真
00C4-01-15 无敌
0053-01-30 命
00BA-01-09 １Ｐ分數，輸入１＝ １０。
00BC-01-09 １Ｐ分數，輸入１＝ １。
00E8-01-01 １Ｐ ITEM 箭 枝
00EA-01-01 １Ｐ ITEM 閃
00EC-01-01 １Ｐ ITEM 電
00EE-01-01 １Ｐ ITEM 鳥
00F0-01-01 １Ｐ ITEM 盾
0797-01-FF 敌人状态<00动态,FF僵硬>
079E-01-01 隐身<00正常,01隐身>
07FA-01-01 时间锁定<00正常,01锁定>
0754-01-FF 上穿墙
0723-01-00
荒野大镖客
#1 007A-01-06 生命无限
《脱狱》真
0424-01-25 血
0438-01-a1 刀
0438-01-9b 子弹
《脱狱2》真
05c2-01-04 命
05da-01-51 无敌
05c6-01-01 枪
05ca-01-04 大枪(01 - 1弹 02 - 2弹 03 - 3弹 04 - 大弹)
#1 0076-01-09 生命
#1 0064-11-63 忍
#1 00C9-01-85 最强武器
188协议水表MBUS-MODBUS转换器说明书201503
188协议⽔表MBUS-MODBUS转换器说明书201503188协议⽔表MBUS－MODBUS转换器使⽤说明书MBUS－MODBUS是MBUS到MODBUS转换模块，⽤于任何MODBUS 主站读取MBUS设备的数据。
现在转换器最多⽀持64块⽔表数据的读取，现在⽀持表类型有：00-真兰⼩⼝径⽔表01-真兰⼤⼝径⽔表02-宁波⽔表03-潍潍⽔表04-兴源⿍新05-连利⼩⼝径热⽔表06-西安旌旗/浙江华⽴利源07-新天⽔表/威胜⼩⼝径⽔表08-京源⽔表09-湖南威胜⼤⼝径⽔表16-荷德⽔表17-艾创⽔表表的型号可以增加，可以跟据⽤户的要求，定制读取其他MBUS⽔表的数据。
随转换器设备提供的软件⽤于配置MODBUS地址、波特率、校验位及MBUS 数据的读取时间以及⽔表的型号和数量。
同时配置软件也可⽤于测试⽬的。
转换器采⽤24V直流输⼊电压，具有MBUS接⼝⽤于连接MBUS仪表(具有⽔表短路保护功能)，具有隔离的485接⼝⽤于和MODBUS主站相连。
MBUS－MODBUS转换模块可以⽀持的⽔表的型号可以由⽤户设定。
技术特性：1.供电电压：DC 24V输⼊。
2.隔离：电源、MBUS、485三端隔离。
3.MODBUS：MODBUS RTU从设备（波特率2400－115200可配置，地址可配置，校验可配置，8位数据，1位停⽌位）4.MODBUS连接⽅式：RS4855.MBUS：⽀持多表读取，表的型号可设；6.MBUS 通信设置：2400波特率，8位数据，偶校验，1位停⽌位7.出⼚设置：MODBUS地址：01 ，MODBUS波特率：9600，MODBUS校验：⽆校验，MBUS采集时间180S8.⼯作温度：－20—＋70度。
9.开孔尺⼨：150mm*90mm*42mm（长×宽×⾼）⼀、 MBUS－MODBUS实物图与接线图图 1 MBUS－MODBUS实物图图 2 MBUS－MODBUS接线图图3产品侧⾯图1、MBUS－MODBUS中有4个灯，LD1是RUN灯，该绿灯闪烁说明模块正常运⾏（⼤约1S闪⼀次）；LD2是Modbus灯，Modbus主设备读取数据时，该绿灯闪烁；LD3是MBUS 灯，转换器读取MBUS 设备时，该绿灯会闪烁；LD4是SHORT红⾊灯，M+和M-之间短路或过载时该红灯亮，如果SHORT红灯亮MBUS设备数据就不能正常读取。
网络安全事件通报预警分类编码规则、网络安全数据目录编码样例、标记标签样例
GA/T XXXX.3—XXXX附录A（规范性附录）分类编码规则A.1 分类编码规则网络安全数据编码中的第23～45位是网络安全数据所属目录编号，包括行业门类、网络安全业务、要素、类别、活动特征和属性共六段，以面分类法构建编码，标识网络安全数据的一个分类维度，全部分类维度构建唯一的网络安全数据所属目录编号；其中，六段编码不可同时全为零。
网络安全数据编码中的第29～34位表示属性、业务、类别、要素、活动特征五个维度构成的类别编码，标识网络安全数据目录的分类，亦采用面分类法编码。
根据第5章的规定，从四个维度对数据进行多维分类，构成彼此互无树型隶属关系的面，每个面都包含一组细目。
将单个面中的细目与其他面的细目组合构成复合细目形态的分类对象编码。
网络安全分类编码中的第36～45位为预留编码，适用于活动特征的进一步细分。
A.2 网络安全数据分类编码网络安全数据编号结构为“CS-XXXXXXXXXXXXXXXXXX（网络安全数据事权单位机构代码，事权单位为公安机关则按照GA/T 380填写；事权单位为非公安机关则填写18位全国组织机构代码或全国统一信用代码，前补0）- XXXXX-XXXXXX-XXXXXXXXX（网络安全数据所属目录编号）”。
示例：CS-121000004000123696-S9223-200532-001001000│└──────网络安全数据所属目录编号└───────事权单位机构代码其中，网络安全数据所属目录编号S9223-200512-001001000具体含义如下：a)S9223表示该网络安全数据的行业门类代码，依据GB/T 4754的规定为“公共安全管理机构”；b)200532表示该网络安全数据的分类代码，第1位代码“2”表示网络安全数据属性分类“资源数据”；第2~4位“005”表示网络安全业务代码，具体为“通报业务”；第5位代码“3”代表网络安全数据类别“活动信息”；第6位代码“2”网络安全数据活动特征分类中的“网络安全活动”；c)001001000表示网络安全活动类别的具体分类，有害程序事件-僵尸控制，最后3位“000”为补全位。
医嘱执行频次(周期)
1次/天 1次/天 1次/天 1次/天 1次/天 1次/天 2次/天 2次/天 2次/天 2次/天 2次/天 2次/天 每天2次，餐 前服用
tid
3次/天
tidac
每天3次，餐 前服用
qid
4次/天
qm
每天早上1次
qn
每天晚上1次
hs
睡前1次
qod
隔日1次
1 1D 1 1D 1 1D 1 1D 1 1D 1 1D 2 1D 2 1D 2 1D 2 1D 2 1D 2 1D 2 1D
例：开嘱时间为12：00，执行频次为：Q8h，遵医嘱时间执行为“是”，则对应的医嘱执行时间为12：00，20：00；若为 23:50；
医嘱频次 名称
频次次数 频次数目 频次单位 频次时间
持续频次标志
q0.5h qh q2h q3h q4h
q6h
1次/半小时 1次/1小时 1次/2小时 1次/3小时 1次/4小时
qw
1次/周
1 1W
8:00
qw_1 qw_2 qw_3 qw_4 qw_5 qw_6 qw_7
biw_1-4
1次/周 1次/周 1次/周 1次/周 1次/周 1次/周 1次/周
2次/周
biw_2-5 2次/周
biw_3-6 2次/周
biw_4-7 2次/周
tiw135 3次/周
tiw246
prn st ls SOS qd_fix
1次/半小时 1次/1小时 1次/2小时 1次/3小时 1次/4小时
否
否
否
否
否
否
否
否
否
否
1次/6小时
否
否
每6小时1次（从第二次开始， 间隔一次执行）
金手指代码收集查询
金手指代码收集查询（按游戏首字母查询）代码（A区）热血格斗04C2-02-FFFF 血不减05B2-01-1D 最高等级05BE-01-1D 同伴最高等级0605-02-FDFD 快手招式0609-02-FFFF 快脚招式0401-02-0404 虎头降临04C4-32-0000 一击必杀0613-01-08 合体无限（锁定合体游标的位置）0614-01-00 敌人别想合体（右侧）061A-01-00 敌人的L是1（右侧）0619-01-08 我方L是L9（左侧）代码（B区）蝙蝠侠无限血00B7-04-0008无敌00CC-01-B0生命00BE-02-0009蝙蝠侠304C8-01-15闪烁无敌0142-01-FFFF等级/分数/血蝙蝠侠20479-01-11 无敌代码（C区）三目童子无敌0074-01-1B赤色要塞无敌金手指0052-02-FF赤影战士06F0-01-10 1P血0662-01-14 1P武器数量0680-01-XX 1P武器威力（00－等级1 04－等级2 08－等级3）06B2-01-XX 1P武器种类（00－刀锋 03－铁钩）赤影忍者全屏攻击轻松通关金手指06C1-03-19008E注意！！！！！！！！！！！！当与到如下情况是请按DELETE关闭金手指。
否则主角会掉下去火之鸟（无敌/定时/无限血/穿墙）超级宝宝00BA-01-11闪烁无敌彩虹魔法金手指:0022:63 (人数)0024:0b (速度+双彩虹+隐身)0509:01-08 (魔法,开启后立即关掉,BOSS战时开启无效) 057a:0f (魔法持续时间)0052:01-06 (选关) 07 (公开关卡,泡泡龙关)赤影战士金手指:06f0:10 (HP)06b2:00 (刀) 03 (矛)0680:0c (武器最强)0662:14 (手里剑 or 雷)06a1:0e (蓄力超杀,开启后立即关闭)代码（D区）西游记1代0109-03-FFFF 无限金钱代码（F区）斧王（战斧）0091-01-14 血0093-01-14 能量007D-01-11 无敌（受攻击后）代码（G区）古巴战士0028-01-63生命04C2-01-FF 坦克0600-01-81 Weapon0600:00-04 (子弹) 05,06 (?子弹)0600:0a (超级雷,用B键发出)0600:20-24 (子弹+超级雷)0600:80-85 (坦克子弹,己方无敌,但不能下水) 0680:20 (隐身)代码（H区）魂斗罗3(魂斗罗4)#1 0091-01-09 1P人数#1 0093-01-09 1P炸弹数#1 0315-01-0C 1P隐身无敌#1 0312-01-01 1P枪型01-S 04-L#2 0090-01-01 选关#2 00B9-01-16 一直闪震#2 030E-01-0B 屏幕间随意走魂斗罗7_超级战魂#1 00A0-01-02 不死#2 00C4-01-02 透明无敌魂斗罗X_Super Contra X (Unl)#1 00B7-01-02 人数#2 005A-01-01 不死#1 008E-01-01 透明火炮无敌0180-01-05荒野大镖客0078-01-04速度0079-01-04射程0049-01-01通缉令火之鸟060A-03-999 时间0411-02-99 兽面0030-02-99 生命（无限续关）0416-03-000055 无限隐身，穿墙（向日葵的效果）0413-03-5575 小兵定身（哨子的效果）0415-03-0044 撞怪无敌（主角和小兵相遇时小兵死，BOSS无效）0412-03-9900 无限血0416-03-440055 无限隐身+撞怪无敌过关时一定要把隐身关了，否则主角不会拼图，站在那里不动金手指开的越少越好代码（I区）代码（J区）代码（K区）空中魂斗罗（Virtuanes）001C-01-XX 1P人数0012-01-XX 1P武器（00－白弹 01－旋转月牙 02－激光 03－旋转椭圆）0088-01-XX 1P速度设置（00－慢 08－快）SD快打006C-02-999 经验科纳米 KONAMI 世界07de:03 (弹药数量)07df:01 (钥匙)07b1:0f (全道具)07b2:ff (全角色副武器)07ca:00-07 (换人)0040:07 (隐身时间)07db:03 (兵蜂登陆)07dc:03 (战斗机登陆)07d0-07d7:0e (HP不减+不死)第3个门开,忘改了... ...代码（L区）龙之忍者029B-01-0A 血0204-01-63 时间代码（M区）魔界村0647-01-00猫和老鼠3命数0046-01-20红心004A-01-FF猫和老鼠命数04A2-01-09红心04A3-01-09代码（N区）鸟人战士008B-01-40定身无敌0088-01-01绝技（SELECT使用的那个）无限能源战士2(力量刀锋2);Power Blade 2 (U)#1 0055-01-03 POW#1 049A-01-12 血#1 00A0-01-12 ENERGY#1 009D-01-99 L数#1 009E-01-99 E数#1 009F-01-99 人数#2 0054-01-10 发镖时POW仍满格#2 0095-01-05 时间(前两位) #2 009C-01-06 AREA(选小关) #2 05B8-01-14 透明#2 054A-01-80 跳得高代码（O区）代码（P区）代码（Q区）代码（R区）忍者龙剑传无敌1代：0095-01-092代：0068-01-2F3代：无敌00AD-01-0A时间00C7-01-09忍者龙剑传2 (中)0068:20 (隐身)00ae:30 (忍)007d:00-04 (手里剑)忍者龙剑传3 (中)00ad:04 (隐身)00cd:63 (忍)009f:00-04 (手里剑)04ee,04ef:80 (,手里剑发出后开启,过关后先关掉,后期BOSS战前也要先关闭) 00a9:01 (刀)忍者龟2人数无限006A-02-99忍者神龟3006A-01-09 :人数无限人间兵器无敌06F8-01-02代码（S区）沙罗曼蛇2无敌0074-01-05SD快打006C-02-999 经验双截龙2 (U)0432:0a (人数)0422:04,08-0b (选关)双截龙3045d:64 (HP)06df:63 (双截棍数量)06e0:63 (2P双截棍数量)06e1:63 (手里剑数量)06e2:63 (铁爪数量)0074:00-03 (换人) 04-0f (?)SD 快打 (中)006d:04 (快速升级)0034:00-02 (换人,建议不要换成哈格) 003e:09 (人数)0030:** ()松鼠大战I#2 005E-01-11 1P闪烁无敌#2 005F-01-11 2P闪烁无敌#1 05B6-01-82 1P人数不减#1 05E6-01-82 2P人数不减#2 0560-01-01 1P跳起飘浮#2 0561-01-01 2P跳起飘浮#2 0031-01-07 选关00,01,02,03,04……松鼠大战II#2 00D8-01-0A 1P闪烁无敌#2 00D9-01-0A 2P闪烁无敌#2 0072-01-02 选关00,01,02,03,04……沙罗曼蛇 2#1 0056-01-63 生命数#1 0506-01-FF 透明无敌双接龙3045D-01-FF角色1血不减06DF-01-FF双截棍不减04DA-01-FF角色3血不减06E1-01-FF角色3飞标不减代码（T区）踢王无敌 00D2-01-28MP 00EC-01-69EXP 00F0-01-69人数 030E-01-0AHP 06B9-01-B0HPMAX 06BB-01-B0物品 06BE-02-FFFF烟山90坦克#1 0045-01-02 基地是可修复钢墙02 基地是不可修复钢墙00#1 0100-01-02 敌人被定时#1 0051-01-64 P1生命#1 0052-01-64 P2生命#2 00A8-01-60 P1加俩星后(推铁)#2 00A9-01-60 P2加俩星后(推铁)#2 0089-01-10 P1防弹罩(无敌)#2 008A-01-10 P2防弹罩(无敌)#2 007F-01-1C 敌方坦克随机增加#2 0086-01-40 Power位置横向X#2 0087-01-D0 Power位置纵向Y#2 0088-01-06 Power类型 00帽01定时02锹03星04炸弹05坦克06枪07船#1 0178-01-A0 P1推草#1 0179-01-A0 P2推草#1 0101-01-63 P1加枪后(推铁/打不死)#1 0102-01-63 P2加枪后(推铁/打不死)#1 0170-01-FF P1加船后(过河/打不死)#1 0171-01-FF P2加船后(过河/打不死)脱狱043a:64 (人数)0047:00-05 (选关)0715:00-02 (手持物变为,00 枪 01 刀 02 手雷)0438:ca (全能力)0438:da (全能力+手持枪) ea (全能力+手持刀) fa (全能力+手雷) 代码（U区）代码（V区）代码（W区）代码（X区）雪山兄弟0369-01-07 Player 1 攻击上升036A-01-07 Player 2 攻击上升雪人兄弟#1 0369-01-07 1P攻击上升(红蓝黄瓶)#1 036A-01-07 2P攻击上升(红蓝黄瓶)#1 0076-01-0A 1P人数#1 0077-01-0A 2P人数#1 03D2-01-01 1P无敌#1 03D3-01-01 1P无敌雪人兄弟0369:07 (1P全能力+不死)036a:07 (2P全能力+不死)037e:20 (无敌)037f:20 (2P无敌)03d4-03d9:e0 (敌全灭,对BOSS依然见效)0073:00-31 (选关)008a:01 (寿)雪人兄弟#1 0369-01-07 1P全能不死(红蓝黄瓶,快腿大镖快镖) #1 036A-01-07 2P全能不死(红蓝黄瓶,快腿大镖快镖) #1 0076-01-0A 1P人数#1 0077-01-0A 2P人数#1 03D2-01-01 1P隐身无敌#1 03D3-01-01 2P隐身无敌#2 037E-01-20 1P大头无敌(绿瓶)#2 037F-01-20 2P大头无敌(绿瓶)#2 0073-01-28 选关00-09,0A-13,14-1D,1E-27,28-31#2 0082-01-01 摇奖机01(1P加楼),02(2P加楼)#2 03D4-01-E0 敌1(Boss)直接灭#2 03D5-01-E0 敌2(Boss2)直接灭#2 03D6-01-E0 敌3直接灭#2 03D7-01-E0 敌4直接灭#2 03D8-01-E0 敌5直接灭#2 03D9-01-E0 敌6直接灭#2 008A-01-01 祝&寿#2 007F-01-3B 时间西游记010c:05 (如意棒)0113:01 (不死)0117:00-03 (宝种类改变)0118:63 (宝数量)雪人兄弟0369:07 (1P全能力+不死)036a:07 (2P全能力+不死)037e:20 (无敌)的金手指应换算成另一种形式0369-01-07036a-01-07037e-01-20代码（Y区）原人0482-01-05 闪烁无敌烟山90坦克#1 0045-01-02 基地是可修复钢墙02 基地是不可修复钢墙00 #1 0100-01-02 敌人被定时#1 0051-01-64 P1生命#1 0052-01-64 P2生命#2 00A8-01-60 P1加俩星后(推铁)#2 00A9-01-60 P2加俩星后(推铁)#2 0089-01-10 P1防弹罩(无敌)#2 008A-01-10 P2防弹罩(无敌)#2 007F-01-1C 敌方坦克随机增加#2 0086-01-40 Power位置横向X#2 0087-01-D0 Power位置纵向Y#2 0088-01-06 Power类型 00帽01定时02锹03星04炸弹05坦克06枪07船#1 0178-01-A0 P1推草#1 0179-01-A0 P2推草#1 0101-01-63 P1加枪后(推铁/打不死)#1 0102-01-63 P2加枪后(推铁/打不死)#1 0170-01-FF P1加船后(过河/打不死)#1 0171-01-FF P2加船后(过河/打不死)影子传说Legend of Kage, The (U)#1 002B-01-09 人数#1 0041-01-02 LV#1 0046-01-60 20(分身,隐身)60(分身,隐身,八向剑)#2 0046-01-80 金刚咒,数值改为20或者60来关掉。
M35060-XXXSP资料
DESCRIPTIONM35060-XXXSP is CATV screen display control IC which can dis-play 40 (horizontal) ! 16 (vertical). It has built-in SYRAM which can be used with character ROM.It uses a silicon gate CMOS process and it housed in a small 32-pin shrink DIP package. For M35060-001SP and M35060-002SP that are standard ROM versions of M35060-XXXSP , the character pat-terns are also mentioned.FEATURES•Screen composition................................40 characters ! 16 lines •Number of characters displayed...................................680 (Max.)•Character composition .....................................12 ! 13 dot matrix •Characters available character ROM ................256 characters SYRAM..............................63 characters•Character sizes available horizontal.....................2 (once, twice)vertical.........................2 (once, twice)setting by every line•Display locations availableHorizontal direction................................................480 locations Vertical direction ....................................................235 locations •Blinking...................................................................character units Cycle....approximately 1 second, or approximately 0.5 seconds Duty ...............................................................25%, 50% or 75%•Data input ............................................................8-bit parallel ! 3•Coloring Character coloring.........8 colors choices per characterBackground coloring .....8 colors choices per character Raster coloring ..................8 colors choices per screen•Blanking Character size blankingBorder size blankingMatrix-outline Halftone blanking Can be set by every line•General-purpose output ports Combined port output (6)(switching to RGB output)•RAM erase .............................Display RAM erasing by every lineSYRAM erasing separately•Scrolling............Bit by bit smooth scroll implemented by software •Composite synchronizating signal generation....................Built-in(PAL, NTSC, M-PAL)•Display oscillation circuit ....................................................Built-in •Synchronous separation circuit ..........................................Built-in •Synchronous correction circuit ...........................................Built-inREV.1.12MITSUBISHI MICROCOMPUTERSM35060-XXXSPSCREEN CHARACTER and PATTERN DISPLAY CONTROLLERSPIN DESCRIPTIONThese input pins determine address and data of the Display RAM, Control RAM, and Overlay RAM (SYRAM) by 8-bit parallel. Hysteresis input is required.When this input pin transitions from “H” to “L”, the device is reset. Built-in a pull-up resistor. Hysteresis input is required.Digital power supply pin. This pin must be connected to + 5V.Ground pin. This pin must be connected to 0V.This pin outputs the composite video signal. The output signal is 2Vp-p. In superim-pose mode, this pin’s signal consists of the OSD signal combined with the input composite signal CVIN.This input pin is used for controlling the “white” character color level of the OSD signal.This input pin is used for controlling the “black” character color level of the OSD signal.This input pin is used for the superimpose mode. An external composite signal may be input through this pin and mixed with the internally generated OSD signal.This input pin is used to input the same signal as CVIN. The horizontal and vertical sync signals are then extracted internally within the device.This input pin is used to determine the slice voltage for extracting the sync signals from the video composite signal.This is filter output pin 1.Analog power supply pin. This pin must be connected to +5V.This is filter output pin 2.These are the pins for attaching an external oscillator circuit for generating the synchronization signal:NTSC (3.580MHz), PAL (4.434MHz), M-PAL (3.576MHz).Factory test pin. The pin must be connected to GND.This output pin can be configured to port P0 or YM output.This output pin can be configured to port P1 or BLNK output.This output pin can be configured to port P2 or B output.This output pin can be configured to port P3 or G output.This output pin can be configured to port P4 or R output.This output pin can be configured to port P5 or CSYN output.Factory test pin. The pin must be connected to GND.This pin is enabled when the CS pin is “L”. Data input to pins AD0 to AD7 is latched at the rising edge of this signal. This pin is hysteresis input.This is chip selection input pin. When this pin is “L”, transmission is enabled. This pin is hysteresis input.FunctionSymbol AD0~AD7AC V DD1V SSCVIDEOLECHA LEBK CVIN HOR VREF LP1V DD2LP2OSCOUT OSCIN TESTB P0P1P2P3P4P5TESTA SCK CSParallel data input Auto-clear input Power pin Earthing pinComposite video signal output Character level input Black level input Composite video signal inputSynchronous signal inputSlice level input Filter output 1Power pin Filter output 2The pins for attaching an exter-nal oscillator circuit for genera-ting the synchronization signal.Test input Port output Port output Port output Port output Port output Port output Test inputClock input for data inputChip select inputPin name Input/Output Input Input ——OutputInput Input Input Input Input Output —Output Output Input Input Output Output Output Output Output Output Input Input InputMITSUBISHI MICROCOMPUTERSM35060-XXXSP SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS3MITSUBISHI MICROCOMPUTERSM35060-XXXSPSCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS4MITSUBISHI MICROCOMPUTERSM35060-XXXSPSCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS SCREEN CONSTITUTIONThe screen lines and rows are determined from each address of the display RAM.The screen constitution is shown in Figure 1.Fig. 1Screen constitution5MITSUBISHI MICROCOMPUTERSM35060-XXXSPSCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS6MITSUBISHI MICROCOMPUTERSM35060-XXXSPSCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS7HSZ0HSZ1HSZ2HSZ3HSZ4HSZ5HSZ6HSZ7HSZ8HSZ9HSZ10HSZ11HSZ12HSZ13HSZ14HSZ15HSZ16BLINK0BLINK1BLINK2BLINK3———0123456789A B C D E F 101112131415161701010101010101010101010101010101010110101010101(2) Address 2A916Status DA Register ContentsFunctionRemarksSet to line 0 of display RAM Set to line 1 of display RAM Set to line 2 of display RAM Set to line 3 of display RAM Set to line 4 of display RAM Set to line 5 of display RAM Set to line 6 of display RAM Set to line 7 of display RAM Set to line 8 of display RAM Set to line 9 of display RAM Set to line 10 of display RAM Set to line 11 of display RAM Set to line 12 of display RAM Set to line 13 of display RAM Set to line 14 of display RAM Set to line 15 of display RAM Set to line 16 of display RAM HSZx 01Horizontal direction character size 1T/dot 2T/dot T: Display clock 0Blinking OFF Duty 50%1Duty 25%Duty 75%01BLINK1BLINK0Cycle approximately 1 second.Cycle approximately 0.5 second.Normal blinking Normal character, reversed character alternation display.Must be cleared to 0.Blinking duty ratio can be altered.Blinking cycle can be altered.Character is in flashing state.Character is always displayed (normal character, reversed character).8MITSUBISHI MICROCOMPUTERSM35060-XXXSPSCREEN CHARACTER and PATTERN DISPLAY CONTROLLERSVSZ0VSZ1VSZ2VSZ3VSZ4VSZ5VSZ6VSZ7VSZ8VSZ9VSZ10VSZ11VSZ12VSZ13VSZ14VSZ15VSZ16HIDE TEST20EQP TEST12———0123456789A B C D E F 1011121314151617010101010101010101010101010101010101010101010101(3) Address 2AA 16Status DA Register ContentsFunctionRemarksSet to line 0 of display RAM Set to line 1 of display RAM Set to line 2 of display RAM Set to line 3 of display RAM Set to line 4 of display RAM Set to line 5 of display RAM Set to line 6 of display RAM Set to line 7 of display RAM Set to line 8 of display RAM Set to line 9 of display RAM Set to line 10 of display RAM Set to line 11 of display RAM Set to line 12 of display RAM Set to line 13 of display RAM Set to line 14 of display RAM Set to line 15 of display RAM Set to line 16 of display RAMVSZx 01Vertical direction character size1H/dot 2H/dotH: Horizontal synchronous pulseSYRAM writting overSYRAM writting over or character erasing Test mode (Must be cleared to 0.)It does not include equivalent pulse.It includes equivalent pulse.Test mode (Must be cleared to 0.)Must be cleared to 0.Decided by register LINER, G and B or DAC bit of SYRAM.MITSUBISHI MICROCOMPUTERSM35060-XXXSPSCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS9(4) Address 2AB 16DSP0 00DSP0 01DSP0 02DSP0 03DSP0 04DSP0 05DSP0 06DSP0 07DSP0 08DSP0 09DSP0 10DSP0 11DSP0 12DSP0 13DSP0 14DSP0 15DSP0 16PHASE 0PHASE 1PHASE 2TEST25TEST26——0123456789A B C D E F 1011121314151617010101010101010101010101010101010101010101010101Status DA Register ContentsFunctionRemarksSet to line 0 of display RAM Set to line 1 of display RAM Set to line 2 of display RAM Set to line 3 of display RAM Set to line 4 of display RAM Set to line 5 of display RAMSet to line 6 of display RAMSet to line 7 of display RAM Set to line 8 of display RAM Set to line 9 of display RAM Set to line 10 of display RAM Set to line 11 of display RAM Set to line 12 of display RAM Set to line 13 of display RAM Set to line 14 of display RAM Set to line 15 of display RAM Set to line 16 of display RAMSet by combination of DSP 0XX (address 2AB 16 and DSP 1XX )and DSP 1XX (address 2AC 16).At internal synchronous mode (EX = 1), display monitor signal area is all blanking signal (BLNK output) area.Note: For halftone display, it is necessary to input the externalcomposite video signal to the CVIN terminal, and externally con-nect a 100 to 200 resistor in series.However, the halftone display is possible only with superim-posed displays.0Character Matrix-outline1Border Halftone (Note)01DSP0XX DSP1XXRaster color setting.Refer Fig 3, 4 about phase angle.SELCOR=0Black Red Green Yellow Blue Magenta Cyan WhiteSELCOR=1Black Red–2Green–2Yellow Gray Yellow–2Cyan WhiteColor0101010100110011PHASE 0PHASE 1PHASE 200001111Test mode (Must be cleared to 0.)Must be cleared to 0.10MITSUBISHI MICROCOMPUTERSM35060-XXXSPSCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS(5) Address 2AC 16DSP1 00DSP1 01DSP1 02DSP1 03DSP1 04DSP1 05DSP1 06DSP1 07DSP1 08DSP1 09DSP1 10DSP1 11DSP1 12DSP1 13DSP1 14DSP1 15DSP1 16LINERLINEGLINEBTEST21———0123456789A B C D E F 1011121314151617010101010101010101010101010101010101010101010101Status DA Register ContentsFunctionRemarksSet to line 0 of display RAM Set to line 1 of display RAM Set to line 2 of display RAM Set to line 3 of display RAM Set to line 4 of display RAM Set to line 5 of display RAMSet to line 6 of display RAM Set to line 7 of display RAMSet to line 8 of display RAM Set to line 9 of display RAM Set to line 10 of display RAM Set to line 11 of display RAM Set to line 12 of display RAM Set to line 13 of display RAM Set to line 14 of display RAM Set to line 15 of display RAM Set to line 16 of display RAMSet by combination of DSP 0XX (address 2AB 16 and DSP 1XX )and DSP 1XX (address 2AC 16).At internal synchronous mode (EX = 1), display monitor signal area is all blanking signal (BLNK output) area.Note: For halftone display, it is necessary to input the externalcomposite video signal to the CVIN terminal, and externally con-nect a 100 to 200 resistor in series.However, the halftone display is possible only with superim-posed displays.0Character Matrix-outline1Border Halftone (Note)01DSP0XX DSP1XXSYRAM color setting.Color is decided by DAC bit (SYEX) of SYRAM or HIDE register.Refer Fig. 3, 4 about phase angle.SELCOR=0Black Red Green Yellow Blue Magenta Cyan WhiteSELCOR=1Black Red–2Green–2Yellow Gray Yellow–2Cyan WhiteColor0101010100110011LINE R LINE G LINE B 00001111Test mode (Must be cleared to 0.)Must be cleared to 0.ERS0ERS1ERS2ERS3ERS4ERS5ERS6ERS7ERS8ERS9ERS10ERS11ERS12ERS13ERS14ERS15ERS16SERS0SERS1SERS2SERS3TEST22TEST23—0123456789A B C D E F 1011121314151617010101010101010101010101010101010101010101010101(6) Address 2AD 16Status DA Register ContentsFunctionRemarksSet to line 0 of display RAM Set to line 1 of display RAM Set to line 2 of display RAM Set to line 3 of display RAM Set to line 4 of display RAM Set to line 5 of display RAM Set to line 6 of display RAM Set to line 7 of display RAM Set to line 8 of display RAM Set to line 9 of display RAM Set to line 10 of display RAM Set to line 11 of display RAM Set to line 12 of display RAM Set to line 13 of display RAM Set to line 14 of display RAM Set to line 15 of display RAM Set to line 16 of display RAMSet to SYRAM code 0016 to 0F 16Set to SYRAM code 1016 to 1F 16Set to SYRAM code 2016 to 2F 16Set to SYRAM code 3016 to 3E 16Erase display RAMERSx 01RAM erase do erase do not eraseIt is unnecessary to reset these registers to “0”.Multiple settings of ERS n is not allowed.Erase SYRAMSERSx 01SYRAM erase do erase do not eraseIt is unnecessary to reset these registers to “0”.Multiple settings of SERS n is not allowed.Test mode (Must be cleared to 0.)Must be cleared to 0.(7) Address 2AE 16010101010101010101010101010101010101010101010101Status DA 0123456789A B C D E F 1011121314151617Register SBIT0SBIT1SBIT2SBIT3SLIN0SLIN1SLIN2SLIN3SLIN4SST0SST1SST2SST3SST4SEND0SEND1SEND2SEND3SEND4—————ContentsFunctionRemarksSet display start bit of scroll block:Set display start line of scroll block:SA = Σ 2n(SBIT n )3n=0SB = Σ 2n(SLIN n )4n=0Set start line of scroll block(last line number of the fixed block 1):Set start line of fixed block 2(last line number of the scroll block):SD = Σ 2n(SEND n )4n=0Must be cleared to 0.Setting validSA = 0 to 12invalidSA = 13 to 15Setting validSB = 0 to 16invalidSB = 17 to 31Setting validSC = 0 to 15invalidSC = 16 to 31When the scrolling onsetting valid SD = 2 to 17invalid SD = 18 to 31When the scrolling off set SD = 0SD > SC + 2Note: When the scrolling on, set the ratio which will be SC < SB < SD.SC = Σ 2n (SST n )4n=0PTC0PTC1PTC2PTC3PTC4PTC5PTD0PTD1PTD2PTD3PTD4PTD5SRAND0SRAND1SRAND2ALL24PC0PC1PC2PC3PC4PC5PC6PC70123456789A B C D EF1011121314151617010101010101010101010101010101010101010101010101(8) Address 2AF 16Status DA Register ContentsFunctionRemarksPort P0 output YM output Port P1 output BLNK output Port P2 output B outputPort P3 output G outputPort P4 output R outputPort P5 output CSYN outputWhen port output: 0 output, when YM output: negative polarity.When port output: 1 output, when YM output: polarity.When port output: 0 output, when BLNK output: negative polarity.When port output: 1 output, when BLNK output: polarity.When port output: 0 output, when B output: negative polarity.When port output: 1 output, when B output: polarity.When port output: 0 output, when G output: negative polarity.When port output: 1 output, when G output: polarity.When port output: 0 output, when R output: negative polarity.When port output: 1 output, when R output: polarity.When port output: 0 output, when CSYN output: negative polarity.When port output: 1 output, when CSYN output: polarity.0Complete border = 1 dot Complete border = 2 dot Complete border = 3 dot Complete border = 4 dot 1Right and dot border = 1 dot Right and dot border = 2 dot Right and dot border = 3 dot Right and dot border = 4 dot SRAND20011011SRAND 1SRANDVertical direction is 1 dot only.Horizontal display range can be altered when all characters are in matrix-outline size.At external synchronous, set to 0.Operation of character code FF 16becomes ineffective.Blanking with all 40 characters in matrix-outline mode Display frequency f T control f T = f H ! { Σ (2nPC n ) + 512 }7n=0Note:At EX (address 2B016) = “0” (external synchronous), setting “1” of ALL24 register is not available.Refer Fig. 2 about PTC0 to 5, PTD0 to 5.Horizontal display period fully blanked with all characters in matrix-outline size.PC7 to PC0 < 3616,PC7 to PC0 > C616 is not available.Select P0 pin Select P1 pin Select P2 pin Select P3 pin Select P4 pin Select P5 pin Select data of P0 pin Select data of P1 pin Select data of P2 pin Select data of P3 pin Select data of P4 pin Select data of P5 pin Condition of border display is changeable.REGISTER CONSTRUCTION COMPOSITIONPHASE2/LINEB 000011110011001101010101PHASE1/LINEG PHASE0/LINER NTSC —7/1627/16/1617/1611/1623/16—PAL —± 7/16 5/16± /16 15/16± 11/16 9/16—Phase (rad)BlackRed Green Yellow Blue Magenta Cyan WhiteColor PHASE2/LINEB 000011110011001101010101PHASE1/LINEG PHASE0/LINER NTSC —7/1627/16/16—/1623/16—PAL —± 7/16 5/16± /16—± /16 9/16—Phase (rad)BlackRed-2Green-2Yellow Gray Yellow-2Cyan WhiteColor Table 3Color and phase of NTSC, PAL (SELCOR = 0)Table 4Color and phase of NTSC, PAL (SELCOR = 1)Table 6Setting condition at LEVEL 0, 1 and 2 (at operation)Operation state101Stop state010LEVEL0LEVEL1LEVEL2Sync Pedestal Color Burst Black Red Green Yellow Blue Mazenta Cyan WhiteColor name NTSC ——0—7/16 ± 2/1627/16 ± 2/16/16 ± 2/1617/16 ± 2/1611/16 ± 2/1623/16 ± 2/16—PAL ——±4/16—± 7/16 ± 2/16 5/16 ± 2/16± /16 ± 2/16 15/16 ± 2/16± 11/16 ± 2/16 9/16 ± 2/16—±±±Phase (rad)Luminance level (V)Chroma amplitude (vs. color burst)Min.1.31.91.92.12.32.73.12.02.52.93.1Typ.1.52.12.12.32.52.93.32.22.73.13.3Max.1.72.32.32.52.73.13.52.42.93.33.5Min.————1.51.41.01.01.41.5—Typ.——1.0—3.02.82.02.02.83.0—Max.————4.54.23.03.04.24.5—Table 7Video signal level (SELCOR = 0)±±±±±No character display at display clockFor matrix and halftone, a character’s number of dots in the horizontal direction increases to 14.Figure 4 shows a display example for a case where adjacent characters have different background colors and for character code FF16.Fig. 4Number of dots in the horizontal direction at matrix-outline or halftone2. Border modeIn border mode, characters are displayed with borders. (Refer toTable 9.) In matrix and halftone modes also, characters are displayedwith borders if the BLK register (address 2B016) is set to 1.Table 10 lists the types of borders.Table 10BorderingHorizontal direction bordering is only 1 dot. When the character extends to the top line of the matrix, no border is left at the top, and when the character extends to the bottom (12th) line of the matrix, no border is left at the bottom.5. Scroll display modeThe scroll display mode is entered by setting registers SBIT0 to 3 (SA), SLIN0 to 4 (SB), SST0 to 4 (SC), and SEND0 to 4 (SD) (all at address 2AE16). (Scroll is turned off when SD = 0.)The screen is scrolled in the range from the (SC)’th line to the (SD-1)’th line, and sections above and below this range are fixed. The beginning line and beginning dot of scroll are the (SA)’th dot on the (SB)’th line.The screen can be scrolled up or down by successively incrementing or decrementing SA and SB.Figure 6 shows examples of how the display is scrolled. The scroll range in these examples contains 12 lines (second to the 13th lines). However, the screen can display only 11 lines at a time, and the re-maining one line is handled as a dummy line and not displayed.Fig. 6 Scrolling exampleFig. 9 Setting example of SYRAMEXAMPLE FOR DATA INPUTUse an 8-bit parallel ! 3 serial input to set data in the display RAM, display control register, and SYRAM. Table 14 lists an example of how data is set.Table 14Data settingFig. 12 Address constructionTIMING REQUIREMENTS (T a = – 20°C to + 70°C, V DD = 5.00 ± 0.25V unless otherwise noted)t W (SCK)t su (CS)t h (CS)t su (AD)t h (AD)t h (SCK)SymbolSCK width CS setup time CS hold time AD setup time AD hold time 1 word hold timeParamenterLimits Min.20020022002002Typ.——————Max.——————ns ns ms ns ns msUnit Fig. 14 Serial input timing requirementsDATA INPUTPRECAUTIONS1. Note for when starting of systemBefore setting registers at the starting of system, be sure to re-___ set the M35060-XXXSP by applying “L” level to the AC pin.2. When power supply noise is generated, the internal oscillatorcircuit does not stabilize, whereby causing horizontal jitters across the picture display. Therefore, connect a bypass capaci-tor between the power supply and GND.3. Note for when throwing power supply into the M35060-XXXSPWhen power to the M35060-XXXSP is activated, characters are sometimes output without defining the internal display RAM, composite RAM and register. Also, immediately after power is turned ON, up until the oscillator circuit stabilizes, data is some-times not set correctly in the register. Therefore, use the follow-ing start-up procedure.__(a) Throwing power supply into the M35060-XXXSP(AC pin= “L”)__(b) Auto-clear releasing (AC pin = “H”)(c) 200 ms waiting state (stabilization period of internal oscillationcircuit) Data input is forbidden.(d) Set register LEVELn_____(e) Set register PAL/NTSC(f) Set register PCn(g) 20 ms waiting state (stabilization period of internal oscillationcircuit)Data input is forbidden.(h) Set other registers(i) Set SYRAM(j) Set display RAM(k) Set register DSPON and register DSPONV to display ON4. Precautions when resuming internal oscillation from the OFFstate.The internal oscillator circuit stops oscillating when register LEVEL = 1, DSPON = 0, DSPONV = 0 and CS terminal = H.When resuming internal oscillation from the OFF state, up until the oscillator circuit stabilizes, data is sometimes not set cor-rectly in the register. Therefore, start oscillation as follows.__(a) CS pin = “H” (oscillation stop)__(b) CS pin = “L” (oscillation start)(c) 20 ms waiting state (stabilization period of internal oscillationcircuit)(d) Set register LEVEL 1 = 0(e) Set other registers: SYRAM, display RAM(f) Set register DSPON and register DSPONV to display ON5. Note for oscillationMake note of the fact that the internal oscillator circuit cannot stabilize in the below situations.(a)When the external composite video signal is discontinuous(changing channels etc.)(b) When change the setting of register PCn(c) When change the setting of register LEVELnWhen (a)~(c), set the display to OFF by registers DSPON and DSPONV before change the setting. Other registers’ settings are forbidden during 20ms after the setting.6. When no external composite video signal is input (Without a sig-nal, characters cannot be displayed by external synchronization.Therefore, switch to internal synchronization.)7. When signal level of the external composite video signal is ex-tremely poor (With a weak electric field, character display is un-controllable by external synchronization. Therefore, switch to internal synchronization.)8. When a crystal oscillator is connected to OSCIN (22-pin) orOSCOUT (21-pin) (Talk with the manufacturer of the crystal os-cillator you are using about matching it to this IC.)Symbol V DD V I V O P d T opr T stgParameterSupply voltage Input voltage Output voltage Power dissipationOperating temperature Storage temperatureSymbol V DD V IH V IL V CVIN f OSCINSupply voltage“H” level input voltage AC, CS, SCK, AD0 to AD7“L” level input voltage AC, CS, SCK, AD0 to AD7Composite video input supply voltage CVIN Oscillation frequency for synchronous signalParameterABSOLUTE MAXIMUM RATINGS (V DD = 5.00V, T a = – 20°C to +70°C unless otherwise noted)Unit V V V mW °C °CUnit V V V V MHzMin.4.750.8 ! V DD0——Typ.5.00V DD02Vp-p 3.5804.4343.576Max.5.25V DD 0.2 ! V DD——Limits ConditionsWith respect to V SS .T a = 25°CRatings – 0.3 to 6.0V SS – 0.3 < V I < V DD +0.3V SS < V O < V DD300– 20 to 70– 40 to 125RECOMMENDED OPERATIONAL CONDITIONS (V DD = 5.00V, T a = – 20°C to +70°C unless otherwise noted)ELECTRICAL CHARACTERISTICS (V DD = 5.00V, T a = +25°C unless otherwise noted)Symbol V DD I DD V OH V OL R ISupply voltage Supply current“H” level output voltage P0 to P5“L” level output voltage P0 to P5Pull-up resistance ACParameterUnit V mV V V k ΩT a = – 20°C to +70°C V DD = 5.00VV DD = 4.75, I OH = – 0.2mA V DD = 4.75, I OL = 0.2mA V DD = 5.00VTest conditionsMin.4.75—3.75—10Typ.5.0030——30Max.5.2560—0.4100Limits VIDEO SIGNAL INPUT CONDITIONS (V DD = 5V, T a = – 20°C to +70°C)Symbol V IN-CUComposite video signal input clamp supply voltageParameterUnit Sync-chip supply voltageTest conditionsMin.—Typ.1.5Max.—Limits VSTANDARD ROM TYPE: M35060-001SPM35060-001SP is a standard ROM type of M35060-XXXSP .Character patterns are fixed to the contents of Figure 16 to 19.Fig. 16 M35060-001SP character patterns (1)00160116021603160416051606160716081609160A 160B 160C 160D 160E 160F 1610161116121613161416151616161716181619161A 161B 161C 161D 161E 161F 1620162116221623162416251626162716281629162A 162B 162C 162D 162E 162F 1630163116321633163416351636163716381639163A 163B 163C 163D 163E 163F 1640164116421643164416451646164716 481649164A164B164C164D164E164F16 50165116521653165416551656165716 581659165A165B165C165D165E165F16 60166116621663166416651666166716 681669166A166B166C166D166E166F16 70167116721673167416751676167716 781679167A167B167C167D167E167F1600160116021603160416051606160716 081609160A160B160C160D160E160F16 10161116121613161416151616161716 181619161A161B161C161D161E161F16 20162116221623162416251626162716 281629162A162B162C162D162E162F16 30163116321633163416351636163716 381639163A163B163C163D163E163F16Fig. 18 M35060-001SP character patterns (3)40164116421643164416451646164716 481649164A164B164C164D164E164F16 50165116521653165416551656165716 581659165A165B165C165D165E165F16 60166116621663166416651666166716 681669166A166B166C166D166E166F16 70167116721673167416751676167716 781679167A167B167C167D167E167F16STANDARD ROM TYPE: M35060-002SPM35060-002SP is a standard ROM type of M35060-XXXSP. Character patterns are fixed to the contents of Figure 20 to 23.Fig. 20 M35060-002SP character patterns (1)Fig. 22 M35060-002SP character patterns (3)32P4B (32-PIN SHRINK DIP) MARK SPECIFICATION FORM32P4BMITSUBISHI MICROCOMPUTERSM35060-XXXSPSCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS HEAD OFFICE: 2-2-3, MARUNOUCHI, CHIYODA-KU, TOKYO 100-8310, JAPAN© 2000 MITSUBISHI ELECTRIC CORP.New publication, effective July. 2000.Specifications subject to change without notice.REVISION DESCRIPTION LIST M35060-XXXSP DATA SHEETRev.Rev.Revision DescriptionNo.date 1.0First Edition980402 1.1•Deletes some Japanese font and create pdf file (some pages)000725•P39 and P40 MARK SPECIFICATION FORM and PACKAGE OUTLINE are added(1/1)。
中日材料对照-参考
6 7 8 9 NO 1 2 3 NO 1 2 3 4 5 6 7 NO 1 2 3 4 5 6 NO 1 2 3 4 5 6 7 8 NO 1 2 3 4 5 6 7 NO 1 2 3 4 NO 1 2 3
SUS317 SUS317L SUS317J1 SUS321 SUS321 SUS347 SUSXM7 SUSXMl5n SUS329n SUS405 SUS410L SUS430 SUS430F SUS434 SUS447n SUSXM27 SUS403 SUS405 SUS410 SUS410J1 SUS416 SUS420J1 SUS420J2 SUS420F SUS431 SUS440A SUS440B SUS440C SUS440F SUS630 SUS631 SUS632 日本JIS SUH 35 SUH 36 SUH 37 SUH 38 SUH 309 SUH 310 SUH 330 SUH 660 SUH 661 SUS 304 SUS 309S SUS 310S SUS 316 SUS 317 SUS 321 SUS 321 SUS 347 SUS XM15J1 SUH 446 SUS 405 SUS 410L SUS 430
SNC415 SNC815 SNC836 ～SNC815 ～SNC815 SNCM220 SNCM439 SNCM439 日本JIS SUM21 SUM32 SUM22L SUM42 日本JIS SWRCH8A SWRCH10K SWRCH15K SWRCH20K SWRCH25K SWRCH30K SWRCH35K SWRCH40K SWRCH45K SWRCH25K SWRCH27K SWRCH30K SWRCH33K SWRCH35K SWRCH38K SWRCH40K SWRCH43K SWRCH45K SWRCH48K SWRCHB620 日本JIS SUP2 SUP3 SUP6 SUP9 SUP9A SUP13 SUP10 SUP11A 日本JIS SUJ1 SUJ3 SUJ2 SNCM220 SNCM420 SUS440C SUS440C 日本JIS SUS316N SUS316LN SUS316J1 SUS316J1l
dc2598a 描述 lt8390a 60v 2mhz 同步降压-升压控制器 示例手册说明书
1UG-1318 Rev ADESCRIPTIONLT8390A60V 2MHz Synchronous Buck-Boost ControllerDemonstration circuit 2598A is a 60V 2MHz synchronous buck-boost controller featuring the L T ®8390A . It accepts an input voltage from 4V to 24V (with transient to 60V) and regulates 12V output at up to 4A. DC2598A features high efficiency and 2MHz switching frequency, a high speed for a 4-switch buck-boost controller . It has a PGOOD flag, short-circuit fault protection, ISMON current-monitoring output signal, and spread spectrum frequency modulation (SSFM) or frequency synchronization.The LT8390A has a wide input voltage range from 4V to 60V. It can regulate an output as a boost, a buck, or a 4-switch boost-buck controller . It has adjustable switch-ing frequency between 600kHz and 2MHz. It has an option for external frequency synchronization or spread spec-trum frequency modulation. Its high switching frequency is unique to buck-boost controller ICs. Because of this, it can be used for high power when the input may be above, below, or equal to the output.DC2598A features an option to turn on spread spectrum by simply changing the position of a jumper from “NO SSFM/SYNC” to “SSFM” (or to “SYNC”).All registered trademarks and trademarks are the property of their respective owners.PERFORMANCE SUMMARYSmall ceramic input and output capacitors are used to save space and cost. There is a protection diode from LED+ to GND to prevent negative ringing during a short-circuit with long wires. Optional EMI input, output, and gate resistor component placeholders exist when a low EMI application is needed.Under voltage lockout can be adjusted with a few resistors and output voltage can be changed from 12V with FB resis-tors changes. Please note that higher voltage outputs may require higher voltage MOSFETs and output capacitors.The LT8390A data sheet gives a complete description of the part, operation and applications information. The data sheet must be read in conjunction with this demo manual for demonstration circuit 2598A. The LT8390AEUFD is assem-bled in a 28-lead 4mm × 5mm plastic QFN package with a thermally enhanced ground pad. LT8390A is also available in a 28-Lead plastic TSSOP (FE) package. Proper board layout is essential for maximum thermal performance. See the data sheet section “Layout Considerations”. Design files for this circuit board are available at /DC2598ASpecifications are at T A = 25°CPARAMETER CONDITIONMIN TYP MAX Input Voltage RangeOperating4V 60V Full Load (4A) Input Voltage Range Component Temp Rise <60°C with No Airflow 7V23VTypical Efficiency 12V Input, 12V 4A Output, 2MHz 90%Switching Frequency R3 = 59.0k 2MHz Peak Switch Current Limit R1 = 0.005Ω10A (AC) Output Ripple12V Input, 12V 4A Output 70mV P-P Input Under Voltage Lockout (Falling Turn-Off)R7 = 383k, R8 = 165k 4.0V Input Under Voltage Lockout (Rising Turn-On)R7 = 383k, R8 = 165k 5.0V V ISMON12V 4A Output 1.0VMaximum Load Current12V Input, 12V Output44.5A2UG-1318 Rev AQUICK START PROCEDUREFigure 1. Test Procedure Setup Drawing For DC2598ADemonstration circuit 2598A is easy to set up to evaluate the performance of the LT8390A Follow the procedure below:1. With the input power supply off, connect the input power supply and output load as shown in the test setup drawing in Figure 1.2. Connect the EN/UVLO terminal to GND.3. Make sure that the SSFM jumper is in the correct posi-tion – either with SSFM turned ON or OFF . Only placethe jumper in the SYNC position if an external SYNCfrequency source is connected to the SYNC pin.4. Turn the input power supply on and make sure the voltage is between 4V and 24V for proper steady state operation.5. Release the EN/UVLO-to-GND connection.6. Observe the 12V output voltage, the load current mea-surement via the ISMON pin voltage and the high effi-ciency of this small converter .QUICK START PROCEDUREFigure 2. DC2598A, LT8390A 2MHz Buck-Boost Efficiency 12V OUTFigure 3. Recommended Maximum DC Current with No Airflow (for DC2598A)UG-1318 Rev A3QUICK START PROCEDUREFigure 4. DC2598A, LT8390A Output Ripple Measured at C454UG-1318 Rev AQUICK START PROCEDUREUG-1318 Rev A56UG-1318 Rev AQUICK START PROCEDUREOptimized for Fast T ransient ResponseDC2598A is assembled as a very small 2MHz buck-boost converter with high efficiency. The ceramic output capaci-tors are used for a very small solution size overall. How-ever , for large signal transients on the output, more output capacitance may be useful, and matched with new com-pensation values. The figure below shows an optimizedlarge signal transient response DC2598A with the addi-tion of two aluminum electrolytic output capacitors and updated RC compensation values. Simply add two Sun-con 25HVHZ47M 47µF 25V capacitors to the output and change the compensation to R4 = 82k and C4 = 470pF. When these changes are made, the no load to full load (4A) transient has less than ±5% V OUT change.V IN V OUT R1L17UG-1318 Rev AITEM QTY REFERENCE PART DESCRIPTIONMANUFACTURER/PART NUMBERRequired Circuit Components11C1CAP ., 1μF, X7S, 100V, 10%, 080521C2CAP ., 4.7μF, X5R, 10V, 10%, 0402TDK, C1005X5R1A475K050BC 31C3CAP ., 0.47μF, X5R, 16V, 10%, 0402TAIYO YUDEN, EMK105ABJ474KV-F 41C4CAP ., 2200pF, X7R, 25V,1 0%, 0402MURATA, GRM155R71E222KA01D 61C5CAP ., 0.022μF, X7R, 25V, 10%, 0402MURATA, GRM155R71E223KA61D 71C6CAP ., 1μF, X7R, 25V, 10%, 0603KEMET , C0603C105K3RACTU 52C7, C8CAP ., 0.1μF, X7R, 25V, 10%, 0402AVX, 04023C104KAT2A81C10CAP ., 22μF, ALUM, 63V, 20%, SMD 6.3mm × 7.7mm SUN ELECTRONIC INDUSTRIES CORP , 63CE22FS 92C12, C32CAP ., 4.7μF, X7S, 100V, 20%, 1206AVX, 12061Z475MAT2A103C14, C20, C45CAP ., 22μF, X5R, 25V, 10%, 1206MURATA, GRM31CR61E226KE15L 162D1, D2DIODE, SCHOTTKY, 100V, 250mA, SOD-323F, AEC-Q101NXP SEMICONDUCTORS, BAT46WJ 251L1IND., 1μH, Power Shielded, 20%, 7.3A, 6mm × 5.5mm WURTH ELEKTRONIK, 74437336010272M1, M2XSTR., POWER MOSFET , 60V, 40A, TSDSON-8INFINEON, BSZ065N06LS5ATMA1292M3, M4XSTR., POWER MOSFET , 25V, 40A, TSDSON-8INFINEON, BSZ031NE2LS5ATMA1311R1RES., 0.005Ω, ±1%, 1.5W, 3216, AEC-Q200SUSUMU, KRL3216E-C-R005-F-T1321R2RES., 0.01Ω, 1%, 3/4W, 1206, SENSE SUSUMU, KRL1632E-M-R010-F-T5331R3RES., 59k, 1%, 1/16W, 0402, AEC-Q200VISHAY, CRCW040259K0FKED 342R4, R6RES., 10k, 1%, 1/16W, 0402VISHAY, CRCW040210K0FKED 351R5RES., 110k, 1%, 1/16W, 0402VISHAY, CRCW0402110KFKED 361R7RES., 383k, 1%, 1/16W, 0402, AEC-Q200VISHAY, CRCW0402383KFKED 371R8RES., 165k, 1%, 1/16W, 0402, AEC-Q200VISHAY, CRCW0402165KFKED 401R11RES., 100k, 5%, 1/16W, 0402VISHAY, CRCW0402100KFKED 451U1IC, 2MHz SYN. BUCK-BOOST CONTROLLER, 28-PIN QFNLINEAR TECH., LT8390AEUFD#TRPBF Optional Electrical Components 53C37, C38, C44CAP ., 0.1μF, X7R, 25V, 10%, 0402AVX, 04023C104KAT2A 110C26, C34, C39CAP ., OPTION, 0402121C27CAP ., 1μF, X5R, 16V, 10%, 0402AVX, 0402YD105KAT2A130C29, C30CAP ., 0805, OPTION 140C33, C40, C41, C42CAP ., OPTION, 1206152C35, C36CAP ., 0.1μF, X5R, 100V, 10%, 0402MURATA, GRM155R62A104KE14D 171D3DIODE, SCHOTTKY, 20V, 1A, SOD-323F NXP SEMICONDUCTORS, PMEG2010EJ 180D4, D5DIODE, OPTION, SCHOTTKY, SMD 220FB1, FB2, FB3, FB4, FB5, FB6IND., OPTION, BEAD, FERRITE, 1206260L2IND., OPTION, XAL4020 SERIES 30Q1XSTR., OPTION, PPAK 1212-8PARTS LISTPARTS LISTITEM QTY REFERENCE PART DESCRIPTION MANUFACTURER/PART NUMBER381R9RES., 124k, 1%, 1/16W, 0402VISHAY, CRCW0402124KFKED391R10RES., 75k, 1%, 1/16W, 0402VISHAY, CRCW040275K0FKEDRES., OPTION, 0402410R12, R20, R21, R25, R28,R29, R30426R14, R15, R16, R17, R24, R26RES., 0Ω, 1/16W, 0402, AEC-Q200VISHAY, CRCW04020000Z0ED432R18, R19RES., 10Ω, 5%, 1/16W, 0402VISHAY, CRCW040210R0FKED440R22, R23, R27RES., OPTION, 0805Hardware194E1, E2, E9, E10TEST POINT, TURRET, 0.094", MTG. HOLE MILL-MAX, 2501-2-00-80-00-00-07-0206E3, E4, E5, E6, E7, E8TEST POINT, TURRET, 0.064", MTG. HOLE MILL-MAX, 2308-2-00-80-00-00-07-0210E11TEST POINT, OPTION231JP1CONN., HDR, MALE, 2mm × 3,2mm, THT, STR WURTH ELEKTRONIK, 62000621121KEYSTONE, 575-4244J1, J2, J3, J4CONN., BANANA JACK, FEMALE, THT, NON-INSULATED, SWAGE284MH1, MH2, MH3, MH4STANDOFF, NYLON, SNAP-ON, 0.375"WURTH ELEKTRONIK, 702933000461XJP1CONN., SHUNT, FEMALE, 2 POS, 2mm WURTH ELEKTRONIK, 608002134218UG-1318 Rev A9UG-1318 Rev AInformation furnished by Analog Devices is believed to be accurate and reliable. However , no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.SCHEMATIC DIAGRAM10UG-1318 Rev AUG16906-0-5/18(A)© ANALOG DEVICES, INC. 2017-2018ESD CautionESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality.Legal Terms and ConditionsBy using the evaluation board discussed herein (together with any tools, components documentation or support materials, the “Evaluation Board”), you are agreeing to be bound by the terms and conditions set forth below (“Agreement”) unless you have purchased the Evaluation Board, in which case the Analog Devices Standard Terms and Conditions of Sale shall govern. Do not use the Evaluation Board until you have read and agreed to the Agreement. Your use of the Evaluation Board shall signify your acceptance of the Agreement. This Agreement is made by and between you (“Customer”) and Analog Devices, Inc. (“ADI”), with its principal place of business at One Technology Way, Norwood, MA 02062, USA. Subject to the terms and conditions of the Agreement, ADI hereby grants to Customer a free, limited, personal, temporary, non-exclusive, non-sublicensable, non-transferable license to use the Evaluation Board FOR EVALUATION PURPOSES ONL Y. Customer understands and agrees that the Evaluation Board is provided for the sole and exclusive purpose referenced above, and agrees not to use the Evaluation Board for any other purpose. Furthermore, the license granted is expressly made subject to the following additional limitations: Customer shall not (i) rent, lease, display, sell, transfer , assign, sublicense, or distribute the Evaluation Board; and (ii) permit any Third Party to access the Evaluation Board. As used herein, the term “Third Party” includes any entity other than ADI, Customer , their employees, affiliates and in-house consultants. The Evaluation Board is NOT sold to Customer; all rights not expressly granted herein, including ownership of the Evaluation Board, are reserved by ADI. CONFIDENTIALITY. This Agreement and the Evaluation Board shall all be considered the confidential and proprietary information of ADI. Customer may not disclose or transfer any portion of the Evaluation Board to any other party for any reason. Upon discontinuation of use of the Evaluation Board or termination of this Agreement, Customer agrees to promptly return the Evaluation Board to ADI. ADDITIONAL RESTRICTIONS. Customer may not disassemble, decompile or reverse engineer chips on the Evaluation Board. Customer shall inform ADI of any occurred damages or any modifications or alterations it makes to the Evaluation Board, including but not limited to soldering or any other activity that affects the material content of the Evaluation Board. Modifications to the Evaluation Board must comply with applicable law, including but not limited to the RoHS Directive. TERMINATION. ADI may terminate this Agreement at any time upon giving written notice to Customer . Customer agrees to return to ADI the Evaluation Board at that time. LIMITATION OF LIABILITY. THE EVALUATION BOARD PROVIDED HEREUNDER IS PROVIDED “AS IS” AND ADI MAKES NO WARRANTIES OR REPRESENTATIONS OF ANY KIND WITH RESPECT TO IT . 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mipi_DSI_specification_v01-02-00_r0-07
DRAFT MIPI Alliance Specification forDisplay Serial InterfaceDraft Version 1.02.00 Revision 0.07 – 30 March 2010Further technical changes to this document are expected as work continues in the Display Working GroupNOTICE OF DISCLAIMER12The material contained herein is not a license, either expressly or impliedly, to any IPR owned or controlled by any of the authors or developers of this material or MIPI®. The material contained herein is provided on 3an “AS IS” basis and to the maximum extent permitted by applicable law, this material is provided AS IS 45AND WITH ALL FAULTS, and the authors and developers of this material and MIPI hereby disclaim all 6other warranties and conditions, either express, implied or statutory, including, but not limited to, any (ifany) implied warranties, duties or conditions of merchantability, of fitness for a particular purpose, of78accuracy or completeness of responses, of results, of workmanlike effort, of lack of viruses, and of lack of 9negligence.All materials contained herein are protected by copyright laws, and may not be reproduced, republished,1011distributed, transmitted, displayed, broadcast or otherwise exploited in any manner without the express12prior written permission of MIPI Alliance. MIPI, MIPI Alliance and the dotted rainbow arch and all related13trademarks, tradenames, and other intellectual property are the exclusive property of MIPI Alliance and14cannot be used without its express prior written permission.15ALSO, THERE IS NO WARRANTY OF CONDITION OF TITLE, QUIET ENJOYMENT, QUIET16POSSESSION, CORRESPONDENCE TO DESCRIPTION OR NON-INFRINGEMENT WITH REGARD 17TO THIS MATERIAL OR THE CONTENTS OF THIS DOCUMENT. IN NO EVENT WILL ANY18AUTHOR OR DEVELOPER OF THIS MATERIAL OR THE CONTENTS OF THIS DOCUMENT OR19MIPI BE LIABLE TO ANY OTHER PARTY FOR THE COST OF PROCURING SUBSTITUTE20GOODS OR SERVICES, LOST PROFITS, LOSS OF USE, LOSS OF DATA, OR ANY INCIDENTAL,21CONSEQUENTIAL, DIRECT, INDIRECT, OR SPECIAL DAMAGES WHETHER UNDERCONTRACT, TORT, WARRANTY, OR OTHERWISE, ARISING IN ANY WAY OUT OF THIS OR2223ANY OTHER AGREEMENT, SPECIFICATION OR DOCUMENT RELATING TO THIS MATERIAL,24WHETHER OR NOT SUCH PARTY HAD ADVANCE NOTICE OF THE POSSIBILITY OF SUCHDAMAGES.2526Without limiting the generality of this Disclaimer stated above, the user of the contents of this Document is27further notified that MIPI: (a) does not evaluate, test or verify the accuracy, soundness or credibility of the28contents of this Document; (b) does not monitor or enforce compliance with the contents of this Document;29and (c) does not certify, test, or in any manner investigate products or services or any claims of compliance30with the contents of this Document. The use or implementation of the contents of this Document may31involve or require the use of intellectual property rights ("IPR") including (but not limited to) patents,32patent applications, or copyrights owned by one or more parties, whether or not Members of MIPI. MIPI33does not make any search or investigation for IPR, nor does MIPI require or request the disclosure of any 34IPR or claims of IPR as respects the contents of this Document or otherwise.35Questions pertaining to this document, or the terms or conditions of its provision, should be addressed to: 36MIPI Alliance, Inc.c/o IEEE-ISTO3738445 Hoes Lane39Piscataway, NJ 08854Attn: Board Secretary4041Contents42Draft Version 1.02.00 Revision 0.07 – 30 March 2010 (i)431 Overview (10)44451.1 Scope (10)1.2 Purpose (10)462 Terminology (informative) (11)47482.1 Definitions (11)2.2 Abbreviations (12)492.3 Acronyms (12)50513 References (informative) (15)3.1 Display Bus Interface Standard for Parallel Signaling (DBI-2) (15)52533.2 Display Pixel Interface Standard for Parallel Signaling (DPI-2) (16)3.3 MIPI Alliance Specification for Display Command Set (DCS) (16)543.4 MIPI Alliance Standard for Camera Serial Interface 2 (CSI-2) (16)55563.5 MIPI Alliance Specification for D-PHY (D-PHY) (16)4 DSI Introduction (17)574.1 DSI Layer Definitions (18)58594.2 Command and Video Modes (19)4.2.1 Command Mode (19)604.2.2 Video Mode Operation (19)61624.2.3 Virtual Channel Capability (20)5 DSI Physical Layer (21)635.1 Data Flow Control (21)645.2 Bidirectionality and Low Power Signaling Policy (21)65665.3 Command Mode Interfaces (22)5.4 Video Mode Interfaces (22)67685.5 Bidirectional Control Mechanism (22)5.6 Clock Management (23)695.6.1 Clock Requirements (23)70715.6.2 Clock Power and Timing (24)5.7 System Power-Up and Initialization (24)726 Multi-Lane Distribution and Merging (26)73746.1 Multi-Lane Interoperability and Lane-number Mismatch (27)6.1.1 Clock Considerations with Multi-Lane (28)756.1.2 Bidirectionality and Multi-Lane Capability (28)76776.1.3 SoT and EoT in Multi-Lane Configurations (28)7 Low-Level Protocol Errors and Contention (31)787.1 Low-Level Protocol Errors (31)79807.1.1 SoT Error (31)7.1.2 SoT Sync Error (32)81827.1.3 EoT Sync Error (32)837.1.4 Escape Mode Entry Command Error (33)7.1.5 LP Transmission Sync Error (33)847.1.6 False Control Error (33)85867.2 Contention Detection and Recovery (34)7.2.1 Contention Detection in LP Mode (34)877.2.2 Contention Recovery Using Timers (34)88897.3 Additional Timers (37)7.3.1 Turnaround Acknowledge Timeout (TA_TO) (37)90917.3.2 Peripheral Reset Timeout (PR_TO) (37)7.4 Acknowledge and Error Reporting Mechanism (38)928 DSI Protocol (39)93948.1 Multiple Packets per Transmission (39)8.2 Packet Composition (40)958.3 Endian Policy (41)96978.4 General Packet Structure (41)8.4.1 Long Packet Format (41)988.4.2 Short Packet Format (43)991008.5 Common Packet Elements (43)8.5.1 Data Identifier Byte (43)1018.5.2 Error Correction Code (44)1021038.6 Interleaved Data Streams (45)8.6.1 Interleaved Data Streams and Bidirectionality (45)1048.7 Processor to Peripheral Direction (Processor-Sourced) Packet Data Types (46)1051068.8 Processor-to-Peripheral Transactions – Detailed Format Description (47)8.8.1 Sync Event (H Start, H End, V Start, V End), Data Type = XX 0001 (0xX1) (47)1078.8.2 EoTp, Data Type = 00 1000 (0x08) (47)1081098.8.3 Color Mode Off Command, Data Type = 00 0010 (0x02) (48)8.8.4 Color Mode On Command, Data Type = 01 0010 (0x12) (48)1101118.8.5 Shutdown Peripheral Command, Data Type = 10 0010 (0x22) (49)8.8.6 Turn On Peripheral Command, Data Type = 11 0010 (0x32) (49)1128.8.7 Generic Short WRITE Packet with 0, 1, or 2 parameters, Data Types = 00 0011 (0x03), 01 1131140011 (0x13), 10 0011 (0x23), Respectively (49)8.8.8 Generic READ Request with 0, 1, or 2 Parameters, Data Types = 00 0100 (0x04), 01 0100 115116(0x14), 10 0100(0x24), Respectively (49)1178.8.9 DCS Commands (50)8.8.10 Set Maximum Return Packet Size, Data Type = 11 0111 (0x37) (51)1181198.8.11 Null Packet (Long), Data Type = 00 1001 (0x09) (51)1208.8.12 Blanking Packet (Long), Data Type = 01 1001 (0x19) (51)8.8.13 Generic Long Write, Data Type = 10 1001 (0x29) (51)1218.8.14 Loosely Packed Pixel Stream, 20-bit YCbCr 4:2:2 Format, Data Type = 00 1100 (0x0C) (51)1221238.8.15 Packed Pixel Stream, 24-bit YCbCr 4:2:2 Format, Data Type = 01 1100 (0x1C) (53)8.8.16 Packed Pixel Stream, 16-bit YCbCr 4:2:2 Format, Data Type = 10 1100 (0x2C) (54)1248.8.17 Packed Pixel Stream, 30-bit Format, Long Packet, Data Type = 00 1101 (0x0D) (54)1251268.8.18 Packed Pixel Stream, 36-bit Format, Long Packet, Data Type = 01 1101 (0x1D) (55)8.8.19 Packed Pixel Stream, 12-bit YCbCr 4:2:0 Format, Data Type = 11 1101 (0x3D) (56)1271288.8.20 Packed Pixel Stream, 16-bit Format, Long Packet, Data Type 00 1110 (0x0E) (57)8.8.21 Packed Pixel Stream, 18-bit Format, Long Packet, Data Type = 01 1110 (0x1E) (58)1298.8.22 Pixel Stream, 18-bit Format in Three Bytes, Long Packet, Data Type = 10 1110 (0x2E) (60)1301318.8.23 Packed Pixel Stream, 24-bit Format, Long Packet, Data Type = 11 1110 (0x3E) (61)8.8.24 DO NOT USE and Reserved Data Types (62)1328.9 Peripheral-to-Processor (Reverse Direction) LP Transmissions (62)1331348.9.1 Packet Structure for Peripheral-to-Processor LP Transmissions (62)8.9.2 System Requirements for ECC and Checksum and Packet Format (63)1358.9.3 Appropriate Responses to Commands and ACK Requests (63)1361378.9.4 Format of Acknowledge and Error Report and Read Response Data Types (65)8.9.5 Error Reporting Format (65)1388.10 Peripheral-to-Processor Transactions – Detailed Format Description (67)1391408.10.1 Acknowledge and Error Report, Data Type 00 0010 (0x02) (68)8.10.2 Generic Short Read Response, 1 or 2 Bytes, Data Types = 01 0001 or 01 0010, Respectively 141142681438.10.3 Generic Long Read Response with Optional Checksum, Data Type = 01 1010 (0x1A) (68)8.10.4 DCS Long Read Response with Optional Checksum, Data Type 01 1100 (0x1C) (69)1448.10.5 DCS Short Read Response, 1 or 2 Bytes, Data Types = 10 0001 or 10 0010, Respectively . 69 1451468.10.6 Multiple Transmissions and Error Reporting (69)8.10.7 Clearing Error Bits (69)1478.11 Video Mode Interface Timing (69)1481498.11.1 Transmission Packet Sequences (70)8.11.2 Non-Burst Mode with Sync Pulses (71)1501518.11.3 Non-Burst Mode with Sync Events (72)8.11.4 Burst Mode (73)1528.11.5 Parameters (74)1538.12 TE Signaling in DSI (75)1541559 Error-Correcting Code (ECC) and Checksum (77)9.1 Packet Header Error Detection/Correction (77)1561579.2 Hamming Code Theory (77)1589.3 Hamming-modified Code Applied to DSI Packet Headers (78)9.4 ECC Generation on the Transmitter (81)1599.5 Applying ECC on the Receiver (82)1601619.6 Checksum Generation for Long Packet Payloads (82)10 Compliance, Interoperability, and Optional Capabilities (84)16210.1 Display Resolutions (84)16316410.2 Pixel Formats (85)10.2.1 Video Mode (85)16516610.2.2 Command Mode (85)10.3 Number of Lanes (85)16710.4 Maximum Lane Frequency (85)16816910.5 Bidirectional Communication (86)10.6 ECC and Checksum Capabilities (86)17010.7 Display Architecture (86)17117210.8 Multiple Peripheral Support (86)10.9 EoTp Support and Interoperability (86)173Annex A Contention Detection and Recovery Mechanisms (informative) (87)174175A.1 PHY Detected Contention (87)A.1.1 Protocol Response to PHY Detected Faults (87)176Annex B Checksum Generation Example (informative) (93)177178Annex C Interlaced Video Transmission Sourcing (95)179180Figures181Figure 1 DSI Transmitter and Receiver Interface (17)182Figure 2 DSI Layers (18)183184Figure 3 Basic HS Transmission Structure (21)Figure 4 Peripheral Power-Up Sequencing Example (25)185Figure 5 Lane Distributor Conceptual Overview (26)186187Figure 6 Lane Merger Conceptual Overview (27)Figure 7 Four-Lane Transmitter with Two-Lane Receiver Example (28)188Figure 8 Two Lane HS Transmission Example (29)189190Figure 9 Three Lane HS Transmission Example (30)Figure 10 HS Transmission Examples with EoTp disabled (40)191192Figure 11 HS Transmission Examples with EoTp enabled (40)Figure 12 Endian Example (Long Packet) (41)193Figure 13 Long Packet Structure (42)194195Figure 14 Short Packet Structure (43)Figure 15 Data Identifier Byte (44)196Figure 16 Interleaved Data Stream Example with EoTp disabled (45)197198Figure 17 Logical Channel Block Diagram (Receiver Case) (45)Figure 18 20-bit per Pixel – YCbCr 4:2:2 Format, Long Packet (52)199Figure 19 24-bit per Pixel – YCbCr 4:2:2 Format, Long Packet (53)200201Figure 20 16-bit per Pixel – YCbCr 4:2:2 Format, Long Packet (54)Figure 21 30-bit per Pixel (Packed) – RGB Color Format, Long Packet (55)202Figure 22 36-bit per Pixel (Packed) – RGB Color Format, Long Packet (56)203Figure 23 12-bit per Pixel – YCbCr 4:2:0 Format (Odd Line), Long Packet (57)204205Figure 24 12-bit per Pixel – YCbCr 4:2:0 Format (Even Line), Long Packet (57)Figure 25 16-bit per Pixel – RGB Color Format, Long Packet (58)206207Figure 26 18-bit per Pixel (Packed) – RGB Color Format, Long Packet (59)Figure 27 18-bit per Pixel (Loosely Packed) – RGB Color Format, Long Packet (60)208Figure 28 24-bit per Pixel – RGB Color Format, Long Packet (61)209210Figure 29 Video Mode Interface Timing Legend (71)Figure 30 Video Mode Interface Timing: Non-Burst Transmission with Sync Start and End (72)211Figure 31 Video Mode Interface Timing: Non-burst Transmission with Sync Events (73)212213Figure 32 Video Mode Interface Timing: Burst Transmission (74)Figure 33 24-bit ECC generation on TX side (81)214Figure 34 24-bit ECC on RX Side Including Error Correction (82)215216Figure 35 Checksum Transmission (83)Version 1.02.00 r0.07 30-Mar-2010 DRAFTMIPI Alliance Specification for DSI Figure 36 16-bit CRC Generation Using a Shift Register (83)217Figure 37 LP High ÅÆ LP Low Contention Case 1 (89)218219Figure 38 LP High ÅÆ LP Low Contention Case 2 (91)Figure 39 LP High ÅÆ LP Low Contention Case 3 (92)220221Figure 40 Video Mode Interface Timing: Non-burst Transmission with Sync Start and End (Interlaced 222Video) (95)Figure 41 Video Mode Interface Timing: Non-burst Transmission with Sync Events (Interlaced Video) (96)223224225Tables226Table 1 Sequence of Events to Resolve SoT Error (HS RX Side) (32)227Table 2 Sequence of Events to Resolve SoT Sync Error (HS RX Side) (32)228229Table 3 Sequence of Events to Resolve EoT Sync Error (HS RX Side) (33)Table 4 Sequence of Events to Resolve Escape Mode Entry Command Error (RX Side) (33)230Table 5 Sequence of Events to Resolve LP Transmission Sync Error (RX Side) (33)231232Table 6 Sequence of Events to Resolve False Control Error (RX Side) (34)Table 7 Low-Level Protocol Error Detection and Reporting (34)233Table 8 Required Timers and Timeout Summary (35)234235Table 9 Sequence of Events for HS RX Timeout (Peripheral initially HS RX) (35)Table 10 Sequence of Events for HS TX Timeout (Host Processor initially HS TX) (36)236237Table 11 Sequence of Events for LP TX-Peripheral Timeout (Peripheral initially LP TX) (36)Table 12 Sequence of Events for Host Processor Wait Timeout (Peripheral initially TX) (36)238Table 13 Sequence of Events for BTA Acknowledge Timeout (Peripheral initially TX) (37)239240Table 14 Sequence of Events for BTA Acknowledge Timeout (Host Processor initially TX) (37)Table 15 Sequence of Events for Peripheral Reset Timeout (37)241Table 16 Data Types for Processor-sourced Packets (46)242243Table 17 EoT Support for Host and Peripheral (48)Table 18 Error Report Bit Definitions (66)244Table 19 Data Types for Peripheral-sourced Packets (67)245246Table 20 Required Peripheral Timing Parameters (74)Table 21 ECC Syndrome Association Matrix (78)247Table 22 ECC Parity Generation Rules (79)248Table 23 Display Resolutions (84)249250Table 24 LP High ÅÆ LP Low Contention Case 1 (87)Table 25 LP High ÅÆ LP Low Contention Case 2 (90)251252Table 26 LP High ÅÆ LP Low Contention Case 3 (92)253Copyright © 2005-2010 MIPI Alliance, Inc. All rights reserved.MIPI Alliance Member Confidential.DRAFT MIPI Alliance Specification for 254Display Serial Interface255 1 Overview 256The Display Serial Interface Specification defines protocols between a host processor and peripheral 257devices that adhere to MIPI Alliance specifications for mobile device interfaces. The DSI specification 258builds on existing specifications by adopting pixel formats and command set defined in [MIPI02], 259[MIPI03], and [MIPI01]. 2601.1 Scope 261Interface protocols as well as a description of signal timing relationships are within the scope of this 262document. 263Electrical specifications and physical specifications are out of scope for this document. In addition, legacy 264interfaces such as DPI-2 and DBI-2 are also out of scope for this document. Furthermore, device usage of 265auxiliary buses such as I 2C or SPI, while not precluded by this specification, are also not within its scope. 2661.2 Purpose 267The Display Serial Interface specification defines a high-speed serial interface between a peripheral, such 268as an active-matrix display module, and a host processor in a mobile device. By standardizing this 269interface, components may be developed that provide higher performance, lower power, less EMI and 270fewer pins than current devices, while maintaining compatibility across products from multiple vendors.2712722 Terminology (informative)273274The MIPI Alliance has adopted Section 13.1 of the IEEE Standards Style Manual, which dictates use of the 275words “shall”, “should”, “may”, and “can” in the development of documentation, as follows:276The word shall is used to indicate mandatory requirements strictly to be followed in order277to conform to the standard and from which no deviation is permitted (shall equals is278required to).279The use of the word must is deprecated and shall not be used when stating mandatory280requirements; must is used only to describe unavoidable situations.281The use of the word will is deprecated and shall not be used when stating mandatory282requirements; will is only used in statements of fact.283The word should is used to indicate that among several possibilities one is recommended284as particularly suitable, without mentioning or excluding others; or that a certain course285of action is preferred but not necessarily required; or that (in the negative form) a certain286course of action is deprecated but not prohibited (should equals is recommended that).287The word may is used to indicate a course of action permissible within the limits of the288standard (may equals is permitted).289The word can is used for statements of possibility and capability, whether material,290physical, or causal (can equals is able to).All sections are normative, unless they are explicitly indicated to be informative.291292Numbers are decimal unless otherwise indicated. Hexadecimal numbers have a “0x” prefix. Binary 293numbers are prefixed by “0b”.2.1 Definitions294295Forward Direction: The signal direction is defined relative to the direction of the high-speed serial clock. 296Transmission from the side sending the clock to the side receiving the clock is the forward direction.297Half duplex: Bidirectional data transmission over a Lane allowing both transmission and reception but 298only in one direction at a time.299HS Transmission: Sending one or more packets in the forward direction in HS Mode. A HS Transmission is delimited before and after packet transmission by LP-11 states.300301Host Processor: Hardware and software that provides the core functionality of a mobile device.302Lane: Consists of two complementary Lane Modules communicating via two-line, point-to-point Lane 303Interconnects. A Lane can be used for either Data or Clock signal transmission.304Lane Interconnect: Two-line, point-to-point interconnect used for both differential high-speed signaling 305and low-power, single-ended signaling.Lane Module: Module at each side of the Lane for driving and/or receiving signals on the Lane.306Copyright © 2005-2010 MIPI Alliance, Inc. All rights reserved.Link: A connection between two devices containing one Clock Lane and at least one Data Lane. A Link 307308consists of two PHYs and two Lane Interconnects.309LP Transmission: Sending one or more packets in either direction in LP Mode or Escape Mode. A LP 310Transmission is delimited before and after packet transmission by LP-11 states.311Packet: A group of four or more bytes organized in a specified way to transfer data across the interface. All 312packets have a minimum specified set of components. The byte is the fundamental unit of data from which 313packets are made.314Payload: Application data only – with all Link synchronization, header, ECC and checksum and other 315protocol-related information removed. This is the “core” of transmissions between host processor and 316peripheral.317PHY: The set of Lane Modules on one side of a Link.318PHY Configuration: A set of Lanes that represent a possible Link. A PHY configuration consists of a 319minimum of two Lanes: one Clock Lane and one or more Data Lanes.320Reverse Direction: Reverse direction is the opposite of the forward direction. See the description for 321Forward Direction.322Transmission: Refers to either HS or LP Transmission. See the HS Transmission and LP Transmission 323definitions for descriptions of the different transmission modes.324Virtual Channel: Multiple independent data streams for up to four peripherals are supported by this 325specification. The data stream for each peripheral is a Virtual Channel. These data streams may be 326interleaved and sent as sequential packets, with each packet dedicated to a particular peripheral or channel. 327Packet protocol includes information that directs each packet to its intended peripheral.328Word Count: Number of bytes within the payload.2.2 Abbreviations329330e.g. Forexample2.3 Acronyms331332ProtocolAIP ApplicationIndependent333AM Active matrix (display technology)ASP Application Specific Protocol334335BLLP Blanking or Low Power interval336PixelBPP Bitsper337BTA BusTurn-Around338InterfaceSerialCSI Camera339DBI Display Bus InterfaceCopyright © 2005-2010 MIPI Alliance, Inc. All rights reserved.DI Data340Identifier341DMA Direct Memory AccessDPI Display Pixel Interface342343DSI Display Serial InterfaceDT Data344Type345ECC Error-CorrectingCode346EMI Electro Magnetic interference347EoTp End of Transmission Packet348DischargeESD Electrostatic349Fps Frames per second350HBP Horizontal Back PorchHFP Horizontal Front Porch351352SpeedHS High353HSA Horizontal Sync Active354HSE Horizontal Sync End355HSS Horizontal Sync Start356ISTO Industry Standards and Technology Organization357PowerLP Low358LPS Low Power State (state of serial data line when not transferring high-speed serial data) LSB Least Significant Bit359second360perMbps Megabits361MIPI Mobile Industry Processor InterfaceMSB Most Significant Bit362363PF PacketFooterHeader364PH PacketLayer365PHY Physical366InterfacePPI PHY-ProtocolCopyright © 2005-2010 MIPI Alliance, Inc. All rights reserved.367QCIF Quarter-size CIF (resolution 176x144 pixels or 144x176 pixels)368QVGA Quarter-size Video Graphics Array (resolution 320x240 pixels or 240x320 pixels) 369RGB Color presentation (Red, Green, Blue)370SLVS Scalable Low Voltage Signaling371SoT Start of Transmission372SVGA Super Video Graphics Array (resolution 800x600 pixels or 600x800 pixels)373StateULPS Ultra-lowPower374VGA Video Graphics Array (resolution 640x480 pixels or 480x640 pixels)375ActiveVSA VerticalSync376EndSyncVSE Vertical377StartSyncVSS VerticalCount378WC Word379WVGA Wide VGA (resolution 800x480 pixels or 480x800 pixels)380Copyright © 2005-2010 MIPI Alliance, Inc. All rights reserved.3 References (informative)381382[MIPI01] MIPI Alliance Specification for Display Command Set, version 1.02.00, MIPI Alliance, 383In Press384[MIPI02] MIPI Alliance Standard for Display Bus Interface (DBI-2), version 2.00, MIPI Alliance, 38529 November 2005386[MIPI03] MIPI Alliance Standard for Display Pixel Interface (DPI-2), version 2.00, MIPI Alliance, 38715 September 2005388[MIPI04] MIPI Alliance Specification for D-PHY, version 0.90.00, MIPI Alliance, 8 October 2007 389A DTV Profile for Uncompressed High Speed Digital Interfaces,[CEA01] CEA-861-E,</Standards/browseByCommittee_2641.asp>, Consumer Electronics 390Association, March 2008391Studio encoding parameters of digital television for standard 4:3 and wide 392[ITU01] BT.601-6,393screen 16:9 aspect ratios, <http://www.itu.int/rec/R-REC-BT.601-6-200701-I/en>,394International Telecommunications Union, 23 February 2007395[ITU02] BT.709-5,Parameter values for the HDTV standards for production and international 396programme exchange, <http://www.itu.int/rec/R-REC-BT.709-5-200204-I/en>,397International Telecommunications Union, 27 August 2009398Interface for digital component video signals in 525-line and 625-line [ITU03] BT.656-5,399television systems operating at the 4:2:2 level of Recommendation ITU-R BT.601,400<http://www.itu.int/rec/R-REC-BT.656-5-200712-I/en>, International401Telecommunications Union, 1 January 2008402Transformations Between Television Component Color Signals, Society for36-2000,[SMPT01] EG403Motion Picture and Television Engineers, 23 March 2000404Much of DSI is based on existing MIPI Alliance specifications as well as several MIPI Alliance 405specifications in simultaneous development. In the Application Layer, DSI duplicates pixel formats used in 406[MIPI03] when it is in Video Mode operation. For display modules with a display controller and frame 407buffer, DSI shares a common command set with [MIPI02]. The command set is documented in [MIPI01].3.1 Display Bus Interface Standard for Parallel Signaling (DBI-2)408409DBI-2 is a MIPI Alliance standard for parallel interfaces to display modules having display controllers and 410frame buffers. For systems based on these standards, the host processor loads images to the on-panel frame 411buffer through the display processor. Once loaded, the display controller manages all display refresh 412functions on the display module without further intervention from the host processor. Image updates 413require the host processor to write new data into the frame buffer.414DBI-2 specifies a parallel interface where data can be sent to the peripheral over an 8-, 9- or 16-bit-wide 415data bus, with additional control signals. DBI-2 supports a 1-bit data bus interface mode as well.416The DSI specification supports a Command Mode of operation. Like the parallel DBI, a DSI-compliant 417interface sends commands and parameters to the display. However, all information in DSI is first serializedCopyright © 2005-2010 MIPI Alliance, Inc. All rights reserved.。
高中物理教学仪器配备标准精选全文
多频率：0.01s、0.02s、0.05s，有同步释放功能
个
13～25
*
JY/T 0390
J01207
12006
电磁打点计时器
个
13～25
*
JY 38-84
J01203
12007
数字计时器
四位及以上，数据存贮，显示：10个挡光间隔时间、10周振动、n次振动时间总和、加速度计时三个时间、自由落体时间不少于二个、二路光电门分别计二个挡光时间(对碰、追碰)，有光电门接口和电磁铁接口，统一接口
个
1～2
“稳定值”指在牛顿第二定律实验中，小车释放后平稳运动中所受的力
14015
学生数字测力计
量程2N，分辨率0.01N，误差≤0。2%，满量程±1/2字，有调零、内置校准、记忆（能显示定值）功能
个
13～25
15
电
15003
高中数字演示电表
直流/交流电压、电流，检流；4-1/2位数码管，不小于5cm
台
13～25
√
√
J14457
15023
示波器
通用二踪。采样频率不低于20MHz
台
1
*
J14457
15026
电阻箱
四位9999Ω，0.5级
个
13～25
√
JY/T 0399
J01424
15026
电阻箱
六位99999.9Ω，0.1级
个
1
√
J01424
15027
台
1
*
J02405
04013
电子起电机
输入DC6V，输出电压范围-17.5 kV～+17.5 kV，短路电流不大于500µA
AB-PLC中文指令集
继电器型指令数据存贮区内的I/O映象文件常开节点（XIC）继电器型指令XIC,XIO,OTE,OTL,OUT,IIN,IOT使用继电器型指令监控和控制数据表中的位状态,如输入位或者计时器控制字的位，继电器型指令包括：利用这些指令，用户可以寻址存贮器所有空间上的位，但是本章中的例子仅表示如何在I/O映象文件内寻址。
处理器中输入映象文件存放的是与输入模板端子相连接输入设备的状态。
在梯形逻辑中,用户可编程这些指令去监控位状态,对于位使用逻辑地址。
输出映象文件是控制与输出模板端子相连接输出设备的状态。
在梯形逻辑中，用户可编程该指令以便控制位。
阶梯逻辑当每个状态指令执行时，寻址位被检测，看它是否达到肯定的状态（ON或OFF）。
如果找到一条被检测状态的连续通路，则阶梯被置主真。
从阶梯开始到输出，阶梯必须保持指令为真的连续通路。
描述当一个外部输入设备接通它的电路时，输入端子与外部设备相连的输入模板检查这个节点，处理器的数据表上反映为接通（ON）状态。
当处理器找到一条寻址位与输入端子相对应的XIC指令时，处理器将确定外部设备是否接通（ON）。
如果处理器检查到接通（ON）状态,则该指令是逻辑将被设定为真(ture)；如果处理器检查到断电（OFF）状态，则该指令的逻辑将被设定为假（false）。
例：I ：012该指令告诉处理器，若发现数据表中的位I ：012/7是接通（ON ）状态，则指令设定为真。
该位与I/O 机架1组2输入模板的端子7相对应。
若输入电路为真，则指令为真。
常闭节点（XIO ）例：I ：01207该指令告诉处理器，若发现数据表中I ：012/7位是OFF 状态，则设定指令为真。
该位与I/O 机架1组2模板中的端子7相对应。
若输入电路为假，则指令为真。
输出线圈(OET)( )例：O ：013( )01若阶梯为真，则该指令使处理器把输出映象表中的O ：013/01位置为ON 状态；若阶梯是假，则置为OFF 。