NiosII_SOPCBuilder_Labs

Designing with the Nios II Processor and SOPC Builder Exercise ManualSoftware and Hardware Requirements to Complete All ExercisesSoftware Requirements:Quartus II 7.1 ModelSim 6.1g Nios II 7.1 Altera Megacores IP 7.1Exercise ManualDesigning with the Nios II Processor and SOPC Builder2Copyright © 2007 Altera Corporation A-MNL-NIIHW-EX-7-1-v1Exercise ManualDesigning with the Nios II Processor and SOPC BuilderLab 1 Creating a Nios II Processor System3Copyright © 2007 Altera Corporation A-MNL-NIIHW-EX-7-1-v1Exercise ManualDesigning with the Nios II Processor and SOPC Builder4Copyright © 2007 Altera Corporation A-MNL-NIIHW-EX-7-1-v1Exercise ManualDesigning with the Nios II Processor and SOPC Builder1. Unless the following step has already been done for you, create a sub-directory path called “altera_trn\NiosII” on the C-drive of your computer. Copy the self-extracting zip file, “NIIHW_Class.exe” into that directory from the CD Rom provided in the class packet. 2. Then double click on NIIHW_Class.exe, and select unzip. This will create all the lab files you will need to get started inside a directory called NIIHW_class. Herein, you will find several sub-directories for each of the different types of development boards supported for this class. Inside each respective project folder is a sub-directory called niosII_lab that contains the partially completed Quartus II project that you will use as your starting point today.5Copyright © 2007 Altera Corporation A-MNL-NIIHW-EX-7-1-v1Exercise ManualDesigning with the Nios II Processor and SOPC Builder3. Navigate into the appropriate project folder for your particular development kit: (Refer to the illustrated directory structure below for help or consult instructor.) You will have to check the part on your board to confirm this. Also, please note whether your part ends with ES or not.DSP Kits FolderNios Kits FoldersEP2S60ES FolderLab Directory Structure and Working Areafor Stratix II 2S60ES kit Nios II Processor Development Kit6Copyright © 2007 Altera Corporation A-MNL-NIIHW-EX-7-1-v1Exercise ManualDesigning with the Nios II Processor and SOPC Builder4. Change directory into nios_II_lab located inside your particular kit’s project folder. Start the Quartus II Software by double-clicking on the project file located therein: (ie. niosII_lab.qpf)5. Assign device family and pinout settings to your Quartus II project by sourcing the TCL script provided in your working directory. From the Tools menu select Tcl Scripts, and then from the Project folder choose the setup script for your development board (eg. Setup_Cyclone_1C20.tcl, etc.), and click Run. (If you are unsure about which kit you are using, please check FPGA on development board or consult your instructor.) This will automatically assign the relevant device settings and pin-outs to the Quartus II project for the particular FPGA development board you are using. niosII Note: As an alternative, you may also source the TCl script from the TCL command prompt in Quartus II by typing “source” followed by the name of the script. For example: “source Setup_StratixII_2S60_rohs.tcl”.6. Save your project File > Save Project. 7. Now build your embedded system! Start SOPC Builder from Tools => SOPC Builder… and enter the system name, niosII, when the next window pops up. You can choose VHDL or Verilog (whichever you prefer) as the implementation language. The blank SOPC builder window will open.7Copyright © 2007 Altera Corporation A-MNL-NIIHW-EX-7-1-v1Exercise ManualDesigning with the Nios II Processor and SOPC Builder8. Set the Device Family to match the FPGA you are using (eg. Stratix II EP2S60. Ensure the External Clock frequency is set to 50 MHz for all kits (except the Stratix II DSP kits, whose input frequency is to be set to 100 MHz).8Copyright © 2007 Altera Corporation A-MNL-NIIHW-EX-7-1-v1Exercise ManualDesigning with the Nios II Processor and SOPC Builder9. From the left hand window pane select Nios II Processor and click Add. Select Nios II/s for the processor core. Select DSP Block as the Hardware Multiply option for all Stratix & Stratix II boards, Embedded Multipliers for all Cyclone II boards or Logic Elements for Cyclone boards.9Copyright © 2007 Altera Corporation A-MNL-NIIHW-EX-7-1-v1Exercise ManualDesigning with the Nios II Processor and SOPC Builder10. Click on the Caches and Tightly Coupled Memories tab. Set the Instruction Cache size to 4Kbytes and include one tightly coupled memory instruction master port.10Copyright © 2007 Altera Corporation A-MNL-NIIHW-EX-7-1-v1Copyright © 2007 Altera Corporation1111. Now, click on the JTAG Debug Module tab. Select the JTAG Target ConnectionDownload Level 3 option. This will provide us with all the debug options listed on that tab.12. Click Finish. This will add it to the SOPC Builder system.Copyright © 2007 Altera Corporation1213. Rename the processor, if necessary, by right clicking on it and selecting Rename . Type in cpu and hit enter.Note: It is essential for you to enter thenames of all peripherals and memories EXACTLY as shown in the lab guide since these components will be referenced later on in the C–code. Also, be sure that you type each name using the correct CASE.14. You will now add the appropriate Avalon-to-tri-state bus-bridging peripheral/s requiredto let you access the various memory chips on your board. (After this you will add the appropriate memory interface controllers, themselves.)You will find the Avalon Tri-State Bridge peripheral in the Bridges section of the SOPC Builder pick-list under Memory-Mapped components. For all the boards, you will add at least one tri-state bridge. Others will require two tri-state bridges. Follow the upcoming steps to see what is required of your board.Copyright © 2007 Altera Corporation13For all boards , add an Avalon-MM Tri-State Bridge peripheral to the design. Select the Registered option, and click Finish . Then, re-name the peripheral to, ext_ram_bus .Copyright © 2007 Altera Corporation1415. From the left hand window pane go to the Memory and Memory Controllers > Flashfolder, highlight the Flash Memory (CFI) component, and click Add . Then, choose the appropriate type of flash memory from the Presets category (see below for choises):For all other Stratix and Cyclone Development Kits add:AMD29LV065D-120R presetaddress width of 23 and a data width of 8Eg.Click Finish . Rename the memory to ext_flash.Copyright © 2007 Altera Corporation1516. For all boards, now add an SRAM memory controller. (For the Cyclone II board andStratix II rohs boards, you will instead add an SSRAM component in the next step.)From the Memories and Memory Controller > SRAM folder in the SOPC Builder pick list, select IDT71V416 SRAM , and click Add . (You can increase the width of the pick-list window to help you find the components if you want to.) Select a memory size of 1024 kB . Click Finish , and rename the memory ext_ram.17. Ensure that the appropriate master slave connections are set in the connections panel inSOPC Builder. That is, the “ext_ram_bus” peripheral tri-state master should master the “ext_ram” (or “ext_ssram”) memory, and the “ext_flash_bus” , if present, should master “ext_flash” memory.Go to the View menu in SOPC Builder, and unless it is already done so for you , turn on Show Connections Column . (A check mark will appear beside your selection.)Copyright © 2007 Altera Corporation16Move your mouse over the connection panel the view will change to highlight either the interconnects or the master-slave connections. Click on the circles in the interconnect to make or sever the connections. Black dots mean that the connection will be made.For Example:move mouse to change connection view as shownCopyright © 2007 Altera Corporation1718. From the left hand window pane find the JTAG UART from the Interface Protocols >Serial folder and click Add. Accept the defaults. (The screen should appear as shown.)Copyright © 2007 Altera Corporation1819. From the pick list, look in the Peripherals > Microcontroller Peripherals folder, selectPIO (Parallel I/O), and click Add . Enter a width of 16 bits, with output ports only . Click Finish . Rename this peripheral seven_seg_pio .Copyright © 2007 Altera Corporation1920. Add a second PIO (Parallel I/O) peripheral with a width of 8 bits, with output portsonly set. Click Finish . Rename this peripheral led_pio .Copyright © 2007 Altera Corporation2021. Select yet one more PIO (Parallel I/O) and Add it to your system. Choose width 4 bitsthis time, with Input ports only selected, and click Finish . Rename the peripheral button_pio .Exercise ManualDesigning with the Nios II Processor and SOPC Builder22. Select the Interval Timer from the Microcontroller Peripherals folder and click Add. Select the Full-Featured Preset, and click Finish. After the timer has been added to your system, rename it to sys_clk_timer.21Copyright © 2007 Altera Corporation A-MNL-NIIHW-EX-7-1-v1Exercise ManualDesigning with the Nios II Processor and SOPC Builder23. From the left hand window pane add another Interval Timer to the system. Change the Preset to Full-featured and the period to usec,. Then click Finish. (You are going to use this later when you time the speed of some of our software functions.)Rename the timer to high_res_timer.22Copyright © 2007 Altera Corporation A-MNL-NIIHW-EX-7-1-v1Exercise ManualDesigning with the Nios II Processor and SOPC Builder24. Locate the System ID Peripheral from the Peripherals > Debug and Performance folder in the pick list, and Add it to your system. (Note: it is recommended that every SOPC Builder design that you create has a system ID peripheral!)23Copyright © 2007 Altera Corporation A-MNL-NIIHW-EX-7-1-v1Exercise ManualDesigning with the Nios II Processor and SOPC Builder25. Now, Add the Altera PLL component to the project from the PLL folder. Then launch the ALTPLL MegaWizard and configure the PLL using the settings shown below. (Note: You navigate through the Wizard using the Next button.)For all Nios II Kits choose from the following:Stratix II rohs and all Cyclone II Boards 50 MHz ON Normal 17 10 0 50% 17 10 -4.80 50% Other Nios II Boards (inc. regular Stratix II) 50 MHz ON Normal 1 1 0 50% N/AInput Clock Freq Auto PLL Selection Mode Output Tap Settings: C0: Mult Factor = Div factor = Phase shift (ns) Duty Cycle = C1: Mult Factor = Div factor = Phase shift (ns) Duty Cycle =Note: to enable PLL output tap C1, check the “Use this clock” check boxFor Stratix II DSP Kits choose from the following:Input Clock Freq Auto PLL Selection Mode Output Tap Settings: C0: Mult Factor = Div factor = Phase shift (ns) Duty Cycle = SII DSP Board 100 ON Normal 1 2 0 50%(Leave all other settings as default)*Please consult with instructor if you are confused as to which board you are using and the settings you need to choose24Copyright © 2007 Altera Corporation A-MNL-NIIHW-EX-7-1-v1Exercise ManualDesigning with the Nios II Processor and SOPC BuilderAfter you configure the PLL to match the setting shown above, the final page of the PLL Wizard should resemble the following: (Note: there will be some minor differences depending on what language you have chosen or development kit you are using for your project.)Select Finish again and then Finish one more time to add the component to the SOPC Builder system; then re-name it, pll.25Copyright © 2007 Altera Corporation A-MNL-NIIHW-EX-7-1-v1Exercise ManualDesigning with the Nios II Processor and SOPC BuilderDouble click on “pll_c0”in the Name column in the Clock Settings window in the top right corner of the SOPC Builder tool, and type over the text to re-name it sys_clk. (For the Cyclone II kits, also re-name pll_c1 to ssram_clk, as well.) The system Clock window should appear as follows:26. Now, click in the Input Clock column for all peripherals except the pll, and change their driving clocks to sys_clk. ie.27. Assign the IRQ numbers: Go to the System menu and select Auto-Assign IRQs to establish some basic IRQ assignments. Take a look at the IRQ values that result. Edit them to ensure that the sys_clk_timer gets priority 0 and JTAG_UART gets priority 2.26Copyright © 2007 Altera Corporation A-MNL-NIIHW-EX-7-1-v1Exercise ManualDesigning with the Nios II Processor and SOPC Builder28. Now, add the tightly coupled on-chip memory to attach to the processor. From the pick list, look inside the Memories and Memory Controllers > On-Chip folder, and select On Chip Memory (RAM or ROM) and click Add. Enable Dual-Port Access.27Copyright © 2007 Altera Corporation A-MNL-NIIHW-EX-7-1-v1Exercise ManualDesigning with the Nios II Processor and SOPC BuilderEg.Click Finish, and rename the peripheral tightly_coupled_instruction_memory. 29. To ensure that all base addresses are valid, right click on any one of the base addresses in the table and select Auto-Assign Base Addresses.28Copyright © 2007 Altera Corporation A-MNL-NIIHW-EX-7-1-v1Exercise ManualDesigning with the Nios II Processor and SOPC Builder30. Change the clock driving the tightly coupled memory to sys_clk, if necessary, and using the Move up button, move the peripheral up in the system contents page until it resides directly underneath the cpu. 31. Now, you must ensure that the appropriate master/slave connections are made between the cpu and the Tightly Coupled Memory. Toggling Avalon Bus Connections: Click your mouse on the appropriate dots in the tightly coupled memory’s connectivity diagram in order to toggle the connections as shown below: (Note: the connected state is solid; while the disconnected state is white.) Port S1 of the tightly_coupled_instruction_memory should be connected to the cpu’s tightly_coupled_instruction_master_0 master port, and port S2 should connect to the cpu’s data_master port.32. Next, change the base addresses of the tightly coupled master ports (S1 and S2) so that they do not overlap any of the other peripherals in the design. Choose 0x02400000 for both by double-clicking in the Base address box and editing the values there.29Copyright © 2007 Altera Corporation A-MNL-NIIHW-EX-7-1-v1Exercise ManualDesigning with the Nios II Processor and SOPC Builder33. Your SOPC Builder System Contents page should now appear as follows:34. Now, you will go back and set the exception and reset addresses for the Nios II processor. Double-click on the “cpu” peripheral, and look at the bottom of the Core configuration page: This is where you can establish the reset and exception addresses of the CPU. Select: ext_flash for the Reset Address and ext_ram (or ext_ssram) for the Exception Address30Copyright © 2007 Altera Corporation A-MNL-NIIHW-EX-7-1-v1Exercise ManualDesigning with the Nios II Processor and SOPC BuilderClick Finish. 35. In the System Contents tab Warning and Message area, check to see if you have any memory address violations. If you do, then go to the System Menu, and select AutoAssign Base Addresses on more time. This should get rid of them.31Copyright © 2007 Altera Corporation A-MNL-NIIHW-EX-7-1-v1Exercise ManualDesigning with the Nios II Processor and SOPC Builder36. In SOPC Builder, click Next to go to the System Generation tab, and uncheck the Simulation checkbox if it is checked.32Copyright © 2007 Altera Corporation A-MNL-NIIHW-EX-7-1-v1Exercise ManualDesigning with the Nios II Processor and SOPC Builder37. Save your SOPC Builder system (File > Save). 38. Next, click Generate. SOPC Builder will now create the parameterized SOPC system. Note: If you happen to receive a warning message in SOPC Builder that prevents you from generating the system, check to make sure that all the peripherals are connected to sys_clk. For example, you might encounter a message like: the cpu/tightly_coupled_instruction_master_0 may connect to 1 slave only If setting sys_clk does not solve your problem, you may have to close SOPC Builder and then re-open it again in order to register the change you just made.39. After SOPC Builder has finished generating your embedded sub-system, open the niosII_lab.bdf schematic in Quartus II using File->Open so that you can add the system to your project: 40. Zoom in or out in the schematic, as needed, using the magnifying glass utility. The schematic editor should resemble the following:33Copyright © 2007 Altera Corporation A-MNL-NIIHW-EX-7-1-v1Exercise ManualDesigning with the Nios II Processor and SOPC Builder41. Then switch back to the Selection Tool arrow, and double-click anywhere on the schematic editor to open the Symbol viewer.Once in Symbol viewer, Open the Project folder, and click on the niosII symbol.34Copyright © 2007 Altera Corporation A-MNL-NIIHW-EX-7-1-v1Exercise ManualDesigning with the Nios II Processor and SOPC Builder42. The block symbols for each, respective, system should appear as follows: Cyclone II and Stratix II rohs Nios II development kit systems:NiosIIclk reset_n in_port_to_the_button_pio[3..0] address_to_the_ext_flash[23..0] data_to_and_from_the_ext_flash[7..0] read_n_to_the_ext_flash select_n_to_the_ext_flash w rite_n_to_the_ext_flash address_to_the_ext_ssram[20..0] adsc_n_to_the_ext_ssram bw _n_to_the_ext_ssram[3..0] bw e_n_to_the_ext_ssram chipenable1_n_to_the_ext_ssram data_to_and_from_the_ext_ssram[31..0] outputenable_n_to_the_ext_ssram out_port_from_the_led_pio[7..0] ssram_clk sys_clkDSP board systems:NiosIIclk reset_n in_port_to_the_button_pio[3..0] sys_clkout_port_from_the_seven_seg_pio[15..0]instaddress_to_the_ext_flash[23..0] data_to_and_from_the_ext_flash[7..0] read_n_to_the_ext_flash select_n_to_the_ext_flash w rite_n_to_the_ext_flash address_to_the_ext_ram[19..0] be_n_to_the_ext_ram[3..0] data_to_and_from_the_ext_ram[31..0] read_n_to_the_ext_ram select_n_to_the_ext_ram w rite_n_to_the_ext_ram out_port_from_the_led_pio[7..0] out_port_from_the_seven_seg_pio[15..0]All other Nios II development kit systems:niosIIclk reset_n in_port_to_the_button_pio[3..0] be_n_to_the_ext_ram[3..0] ext_ram_bus_address[22..0] ext_ram_bus_data[31..0] read_n_to_the_ext_flash read_n_to_the_ext_ram select_n_to_the_ext_flash select_n_to_the_ext_ram w rite_n_to_the_ext_flash w rite_n_to_the_ext_ram out_port_from_the_led_pio[7..0] out_port_from_the_seven_seg_pio[15..0]instsys_clkinst35Copyright © 2007 Altera Corporation A-MNL-NIIHW-EX-7-1-v1Exercise ManualDesigning with the Nios II Processor and SOPC Builder43. Add the niosII component to your Quartus II project by pressing OK; then drop the symbol into your schematic so that it’s pins line up exactly with the pin placements as shown below. Note: If the pins do not all line up exactly, then you will need to go back to SOPC Builder and re-check your work. (Please refer to the schematic that corresponds to your particular development kit.)Cyclone II and Stratix II rohs Nios II Development Kit systems will resemble this figure:36Copyright © 2007 Altera Corporation A-MNL-NIIHW-EX-7-1-v1Exercise ManualDesigning with the Nios II Processor and SOPC BuilderAll other Nios II Development Kit systems will resemble this figure:Exception: For the regular non-rohs Stratix II Nios II development kits: where the bus width of the flash address is actually 24 bits. (ie. ext_ram_bus_address[23..0])While Stratix II DSP Development Kit systems will look like this:37Copyright © 2007 Altera Corporation A-MNL-NIIHW-EX-7-1-v1Exercise ManualDesigning with the Nios II Processor and SOPC Builder44. Save the schematic (File > Save). 45. Save the Quartus II project (File > Save Project). 46. .Start compilation in Quartus II. by selecting Start Compilation from the Processing menu. 47. When compilation completes, select OK. You will continue from this point during the next lab.END OF LAB 138Copyright © 2007 Altera Corporation A-MNL-NIIHW-EX-7-1-v1Exercise ManualDesigning with the Nios II Processor and SOPC Builder39Copyright © 2007 Altera Corporation A-MNL-NIIHW-EX-7-1-v1Exercise ManualDesigning with the Nios II Processor and SOPC BuilderLab 2 Software Flow40Copyright © 2007 Altera Corporation A-MNL-NIIHW-EX-7-1-v141Copyright © 2007 Altera CorporationCopyright © 2007 Altera Corporation421. You will now download the Nios II FPGA design created in the previous lab to the Niosdevelopment board.Within Quartus II , select the Programmer from the Tools menu. (If the .sof file foryour project does not populate the File field then click on the Add File button . Thenselect file niosII_lab.sof and click Open .)2. Tick the Program/Configure checkbox for that .sof file, and then click the StartProgramming icon .If the Start Programming button is not enabled, make sure you Hardware Setup field (atthe top of the Programmer window) reads USB-Blaster or Byteblaster. If not, click on the Hardware Setup button and choose USB-Blaster or Byteblaster from the drop-down menu, and click Close.3. Launch the Nios II IDE from SOPC Builder (see Tools > Nios II IDE ). Select OK ifthe Workspace Launcher dialog box appears.4. Go to the Nios II IDE workbench, create a new software project by selecting New->Project from the File menu. Select Nios II C/C++ Application, and press Next.Copyright © 2007 Altera Corporation435. In the second page of the wizard, type niosII_training_project as the name of theapplication to be created. Then verify that the .ptf file from your SOPC Builder session (niosII.ptf) has automatically populated the SOPC Builder System field in the Select Target Hardware pane.6. Now, select the Blank Project template from the Select Project Template panel on theleft hand side of the window. The New Project window should now resemble the following:Copyright © 2007 Altera Corporation447. Press Next , and select:Create a new system library named: niosII_training_project_syslib . Then, click Finish.8. You have now created two new projects in the Nios II IDE - a Nios II C/C++Application project and a system library project . However, the Nios II C/C++ Application project is blank and you need to add some source code to it.To add the file, simple.c , to the project, first expand the niosII_training_project folder in the Nios II IDE.Then, from within Windows, browse to~NIIHW_Class\<your_particular_kit>\nios_II_lab\software , and find simple.c.Copyright © 2007 Altera Corporation45Drag simple.c into the niosII_training_project folder in the Nios II IDE as illustrated:9. Now, highlight the niosII_training_project_syslib folder, right-click, and selectProperties .Then, choose System Library from the left hand side of the Properties window. Ensure that the stdout , stderr and stdin devices are set to jtag_uart and that the System clock timer is set to sys_clk_timer .For all boards except the Cyclone II board, set the Read-only data, Read/write memory, and Program Memory fields to ext_ram . (For Cyclone II, set it to ext_ssram .)Please refer to the figure on the next page.dragCopyright © 2007 Altera Corporation4610. Click OK .11. Compile the program by highlighting the niosII_training_project folder in the Nios IIC/C++ Projects window; then right-click and select Build Project . Note: You can choose to run this command in the background when prompted. This will free up the tool, letting you continue to use it for other tasks; whereas, running it in the foreground causes you wait for it to complete.12. After the compiler has finished, download and run the program on the development board:Highlight the niosII_training_project folder then right-click and select Run As-> Nios II Hardware .Note 1: If Run terminates before the code downloads to your board, and you get amessage pertaining to the JTAG download cable. then select Run > Run… and from the Target Connection tab choose the appropriate download cable that you are using and then press Apply and Run (or see instructor).Note 2: The Nios II IDE will actually Build the project automatically for you if youjust click Run As -> Nios II Hardware without you having to explicitly go through the Build step. You can enable or disable this option in the Window > Preferences .Copyright © 2007 Altera Corporation47This will download the program to the development board. You should observe that the console window in the Nios II IDE displays the printf statement (“Simple”) from the simple.c file.Press of any of the four SW buttons on the board to shift the LED pattern to the right.Copyright © 2007 Altera Corporation4813. Now, let’s run the debugger on this design and step through some code. Start thedebugger by once again highlighting the niosII_training_project software project folder , then right-clicking on it, and selecting Debug As-> Nios II Hardware . The debugger will launch, connect to the target, and download the program ready for debug. Choose, Yesto switch perspectives when prompted.14. Turn on line numbers in the C file editor. To do this, go to the Window menu, and selectPreferences . Open the General folder followed by the Editors sub-folder. Select Text Editor ; then check Show line numbers . Press OK .15. Set breakpoints on line 22 and line 37.To set a breakpoint, simply place the cursor on the line number or grey area next to it, and double-click. A circle should now appear next to the line number indicating that a breakpoint is set.16. Click on the resume button.Copyright © 2007 Altera Corporation4917. Now, go to the Variables window, and view the contents of the buttons variable. Noticethat the button value has been read.18. Click resume again. Since the if expression is false (ie. no buttons are pressed) thestatements within the curly braces are not executed, and thus you will not break on line 37. Instead you will break again on line 22.19. Hold down switch SW3 on the board and click resume . Notice that a new value is storedin the buttonsvariable.20. Continue to hold down SW3 and click resume again.Since a button was pressed when you advanced the debugger this time, the breakpoint on line 37 is now caught, so the if condition must be true. Notice that the illuminated LED has also changed position and the led variable has incremented.21. Release the button, and click on the resume button until the program returns to line 22.22. Within the Variables window, select and highlight the value of buttons . Then, manuallychange it to 0xe , and hit Enter . Click resume . Notice that the if statement is executed due to the change you just made.Editing the variable values in this way is useful because it gives you a way to emulate external hardware events or other conditions that may otherwise be difficult to replicate!。