可编程资料概览

大题全部写代码1.标识符value标识符格式reg，数字不能开头变量，可以%_$ 其他的不可以，关键词reg or 不行，内部有的2.阻塞非阻塞赋值=立即赋值，<=延时，例子a=b=c a=1 b=a c=b a=c=b=1a<=1 b<=a c<=b a=1 b=0 c=0阻塞赋值和非阻塞赋值的基本区别是：阻塞赋值是顺序执行语句，而非阻塞赋值是并行执行语句。

3.{} 拼接运算符作用：不同的数拼在一起例子：A=3’b101 B=6’b101101 问{A,B[3:1]}=6’b101110记得数数是从0开始的，A全部，B的1到3位宽不够高位补0；位宽过剩裁去高位1s=10^3ms=10^6us=10^9ns=10^12ps4.BCD码--B二进制D十进制O八进制H十六进制2个十六进制为1个字节，8个二进制数为1个字节例子(13)10=(00010011)BCD 考试可能问（13）8=（？）BCD转换见书本目录页5.属于可编程逻辑器件FPGA CPLD EPLD ARM C51 X86不是Assign对应wireAlways对应reg6.注解行注解// 段注解/*SDSJDKJDSLKDL*/7.%叫做取余数13%5=3/ 叫做整除13/5=28.ModelSim仿真工具，用代码生成波形，例子AlwaysBegin#10 clk=0; (#叫做延迟时间单位，单位时间是timescale 10ns/100ps，表示1单位时间=10ns，100ps代表精度，这句意思过了100ns后clk=0 （clk前200ns是0）又过100ns clk 取反) ’#10 clk=~clk;End 200NS 100NS 100NS 100NSClk占空比高电平比整个周期1/2这段测试代码的意思是：以ps为单位，0时刻是，A=B=C=D=1，表示四个安全带均没有系上，然后过了10ps，B=0，代表这个安全带系上了；再过了10ps，A=0，代表另一个安全带系上了；再过了10ps，D=0，代表另一个安全带系上了；再过了10ps，C=0，最后一个安全带系上了。

然后再过10ps，B=1，这个安全带松开了。

最后再过20ps，测试结束。

以上情况已经可以完全模拟电路的工作情况，如果仿真正确，当且仅当A=B=C=D=0的时刻，LED_OUT=0，BUZ_OUT=0，灯灭，蜂鸣器不响；其它情况LED_OUT和BUZ_OUT均为１。

9.异步复位同步复位Always@(posedge clk) posedge上升沿negedge下降沿同步异步看posedge 同步短If(rstn==1’b0)指定同步复位时，always的敏感表中仅有时钟沿信号，仅仅当时钟沿采到同步复位的有效电平时，才会在时钟沿到达时刻进行复位操作。

指定异步复位时，只需always的敏感表中加入复位信号的有效沿即可，当复位信号有效沿到达时，无论时钟沿是否有效，复位都会立即发挥其功能。

10.长信号赋值给短信号 例子A=8’b10010011 B=3’b001 B<=AB=011(取后几位)Reg[19:0]A Reg[9:0]BB<=A ，A 的低位给B 大题1.表决器 7人 （不要用卡罗图） 5人3个控制端两种方法五人表决器方法一：数据流module 5get1(b1,b2,b3,b4,b5,u); input b1,b2,b3,b4,b5; output u;wire[2:0]add_result;assign add_result=b1+b2+b3+b4+b5; assign u=add_result>=3? 1'b1:1'b0; endmodule七人表决器方法一Input[6:0 ]In; Ouput u ； Always @(in)If （in[6]+in[5]….+in[0]>4） u=1;b1 ElseOut=1’b0 方法二Case （In[0]+In[1]+……+In[6]） 3’d4:u=1’b1; 3’d5:u=1’b1; Default:u=0; Endcase;2.多路选择器（5选1）例子：4选1数据选择器⏹ reg F;⏹ always@(P0 or P1 or P2 or P3 or S) ⏹ begin⏹case(S) //用case 语句进行选择⏹ 2’b00:F=P0; //S1S0=00时选择输出数据P0⏹ 2’b01:F=P1; //S1S0=01时选择输出数据P1⏹ 2’b10:F=P2; //S1S0=10时选择输出数据P2⏹2’b11:F=P3; //S1S0=11时选择输出数据P3⏹endcase⏹end⏹endmodule2位二进制数据比较器module a1(A,B,EQ,LG,SM);input [1:0]A,B;output EQ,LG,SM;reg EQ,LG,SM;always@(A or B)begin if(A==B)beginEQ=(A==B)?1'b1:1'b0;LG=1'b0;SM=1'b0;endelse if(A>B)beginEQ=1'b0;LG=(A>B)?1'b1:1'b0;SM=1'b0;endelsebeginEQ=1'b0;LG=1'b0;SM=(A<B)?1'b1:1'b0;endendendmodule3触发器（置位，复位，上升沿，下降沿）有圆圈是下降沿negedge升沿posedge 给图写代码4.分频器分频系数=原频率/目标频率=19.44MHZ/8KHZ=2430最大计数为分频系数的一半（高低电平各一半）即1215 =10011100010B，因此二进制计数器的位数为11。

先弄分频系数直接除2430怎么知道多少位参考点2^10=1024；2^11=2048 ；2^12=4096；2^13=8192解答⏹always@(posedge clk)⏹begin⏹if(cnt==1214)⏹cnt<=0;⏹else cnt<=cnt+1;⏹end⏹always@(posedge clk)⏹begin⏹if(cnt==1214)⏹clkout<=~clkout;⏹else clkout<=1'b0;⏹end0.01s分频器（1s为25000000）module m_divider(sys_clk,div_clk);input sys_clk;output div_clk;reg[26:0]counter;reg div_clk; always@(posedge sys_clk)if (counter==27'd2500000000)begincounter<=27'b0;div_clk<=~div_clk;endelsecounter<=counter+1'b1; endmodule分频器与计数器的配合0-9 方法一模块一：分频module fenpin25(clk,rst,clk_1hz); input clk;input rst;output clk_1hz;reg clk_1hz;reg [24:0]cnt;always@(posedge clk or negedge rst) beginif(rst==1'b0)cnt<=25'd0;else if(cnt==25'd2*******)begincnt<=25'd0;clk_1hz<=~clk_1hz;endelsecnt<=cnt+1;endendmodule模块二：modulecnt74160(clk,rst,en,load,data,dout,cout);input clk,rst,en,load;input[3:0] data;output[3:0] dout;output cout;reg[3:0] q1;reg cout;assign dout=q1;always @(posedge clk or negedge rst) beginif(!rst)q1<=0;else if(en)beginif(!load)q1<=data;else if (q1<9)q1<=q1+1;elseq1<=4'b0000;endendalways @(q1)beginif(q1==4'h9)cout=1'b1;else cout=1'b0;endendmodule模块三：module qiduan(cnt,led,scan);input [3:0] c nt;output [6:0] l ed;output [3:0] s can;reg [6:0] l ed;wire [3:0] s can;assign scan=4'b0001;always@(cnt)begincase(cnt)4'b0001:led=7'b0000110;4'b0010:led=7'b1011011;4'b0011:led=7'b1001111;4'b0100:led=7'b1100110;4'b0101:led=7'b1101101;4'b0110:led=7'b1111100;4'b0111:led=7'b0000111;4'b1000:led=7'b1111111;4'b1001:led=7'b1101111;4'b1010:led=7'b1110111;default:led=7'b0111111;endcaseendendmodule顶层模块：modulecount_160(clk,rst,en,load,data,cout,scan,led);input clk,rst,en,load;input[3:0] data;output cout;output [6:0] l ed;output [3:0] s can;wire [3:0] c nt;wire [6:0] l ed;wire [3:0] s can;fenpin25 u0(clk,rst,clk_1hz);cnt74160u1(clk_1hz,rst,en,load,data,cnt,cout);qiduan u2(cnt,led,scan);endmodule方法二：模块一：module sysclk(reset,sys_clk,clk_1hz);input sys_clk;input reset;output clk_1hz;reg[24:0] cnt25m;reg clk_1hz;always@(posedge sys_clk )if (reset==1'b1)cnt25m<=25'd0;else if(cnt25m==25'd2*******)begincnt25m<=25'd0;clk_1hz<=~clk_1hz;endelsecnt25m<=cnt25m+1'b1;endmodule模块二：module cnt_10(reset,clk,cnt); input clk,reset; output [3:0]cnt; reg[3:0] cnt; always @(posedge clk or posedge reset) begin if (reset==1'b1) cnt<=4'b0000; else if (cnt==4'd9) cnt<=4'b0000; else cnt<=cnt+1; end endmodule 模块三：module ymxs(cnt,scan,data_out,); input[3:0]cnt; output [7:0]data_out; output [3:0]scan;assign scan =4'b0001;reg[7:0] data_out;wire [3:0]scan;always@(cnt) begin case (cnt) 4'b0000 : data_out<=8'b00111111; 4'b0001 : data_out<=8'b00000110; 4'b0010 : data_out<=8'b01011011; 4'b0011 : data_out<=8'b01001111; 4'b0100 : data_out<=8'b01100110; 4'b0101 : data_out<=8'b01101101; 4'b0110 : data_out<=8'b01111101; 4'b0111 : data_out<=8'b00000111; 4'b1000 : data_out<=8'b01111111; 4'b1001 : data_out<=8'b01101111; default : data_out<=8'b00000000; endcase end endmodule 顶层模块 module total (reset,sys_clk,data_out,scan); input sys_clk; input reset; output [7:0]data_out; output [3:0]scan; wire clk_1hz; wire [3:0] cnt; sysclk U1(reset,sys_clk,clk_1hz);cnt_10 U2(reset,clk_1hz,cnt); ymxs U3(cnt,scan,data_out); endmodule 占空比为1:15的分频电路设计 module clk_15_1(clk,rst,clk_div); input clk,rst; output clk_div; reg clk_div; reg [3:0] cnt; always @(posedge clk or posedge rst) begin if (rst==1'b1) cnt<=4'b0000; else cnt<=cnt+1; end always@(posedge clk or posedge rst) begin if(rst==1'b1) clk_div<=1'b0; else if (cnt==4'd15) clk_div<=1'b1; else clk_div<=1'b0;endendmodule占空比为10:6的波形设计和仿真module clk_10_6(clk,rst,clk_div);input clk,rst;output clk_div;reg clk_div;reg [3:0] cnt;always @(posedge clk or posedge rst)beginif (rst==1'b1) cnt<=4'b0000;else cnt<=cnt+1;endalways@(posedge clk or posedge rst)beginif(rst==1'b1) clk_div<=1'b0;else if (cnt>=4'd10) clk_div<=1'b1;else clk_div<=1'b0;endendmodule移位寄存器1.并入串出module myshift_3(din,clk,rst,load,dout);input clk,rst,load;input[3:0]din;output dout;reg dout;reg [3:0] q;always @(posedge clk or negedge rst)beginif (rst==1'b0)dout<=4'b0000;else if (load==1'b1)q<=din;elsebeginq<=q<<1;q[0]<=1'b0;enddout<=q[3];endendmodule2.串入并出module myshift_2(din,clk,rst,dout); input din,clk,rst;output [3:0]dout;reg [3:0]dout;always@(posedge clk or negedge rst) beginif (rst==1'b0)dout<=4'b0000;elsedout={dout[2:0],din};endendmodule3.串入串出module shift_1（din,clk,dout);input din,clk;output dout;reg dout;regtmp1,tmp2,tmp3,tmp4,tmp5,tmp6,tmp7;always@(posedge clk)begintmp1<=din;tmp2<=tmp1;tmp3<=tmp2;tmp4<=tmp3;tmp5<=tmp4;tmp6<=tmp5;tmp7<=tmp6;dout<=tmp7;endendmodule循环移位寄存器设计⏹module shift_4(clk,rst, din,dout);⏹input clk,rst;⏹input [3:0] din;⏹output [3:0] dout;⏹reg [3:0] d out;⏹always @ (posedge clk orposedge rst)⏹begin⏹if(rst == 1'b1)⏹dout<=din;⏹else begin⏹dout[3:1]<=dout[2:0];⏹dout[0]<=dout[3];⏹end⏹end⏹endmodule流水灯循环移位点亮模块一module shift_8(clk_2,rst,din,dout);input clk_2,rst;input [3:0] din;output[7:0] dout;reg[7:0] dout;always@(posedge clk_2 or posedge rst) beginif(rst==1'b1)dout<=din;elsebegindout[7:1]<=dout[6:0];dout[0]<=dout[7];endendendmodule模块二：module fenpin(rst,clk,clk_1hz);input rst,clk;output clk_1hz;reg clk_1hz;reg[24:0] counter;always@(posedge clk or posedge rst)beginif(rst==1)counter<=0;else if(counter==25'd2*******)begincounter<=0;clk_1hz<=~clk_1hz;endelsecounter<=counter+1'b1;endendmodule顶层模块：module zong(rst,clk,din,dout);input rst,clk;input [3:0] din;output[7:0] dout;wire clk_1hz;fenpin U1(rst,clk,clk_1hz);shift_8 U2(clk_1hz,rst,din,dout); endmodule数码管段轮流点亮模块一：module fenpin(rst,clk,clk_1hz);input rst,clk;output clk_1hz;reg clk_1hz;reg[24:0] counter;always@(posedge clk or posedge rst) beginif(rst==1)counter<=0;else if(counter==25'd2*******)begincounter<=0;clk_1hz<=~clk_1hz;endelsecounter<=counter+1'b1;endendmodule模块二：module shift_8(clk_2,rst,din,scan,dout); input clk_2,rst;input [3:0] din;output [3:0] scan;output[7:0] dout;reg[7:0] dout;assign scan=4'b0001;always@(posedge clk_2 or posedge rst) beginif(rst==1'b1)dout<=din;elsebegindout[7:1]<=dout[6:0];dout[0]<=dout[7];endendendmodule顶层模块：module zong(rst,clk,din,scan,dout);input rst,clk;input [3:0] din;output[7:0] dout;output [3:0] scan;wire clk_1hz;fenpin U1(rst,clk,clk_1hz);shift_8 U2(clk_1hz,rst,din,scan,dout);endmodule时钟module digc_0379 (sys_clk,reset,pause,scan,data_out);input sys_clk,reset,pause;output[3:0]scan;output[7:0]data_out;reg [24:0]cnt25m;reg [19:0]cnt20n;reg sec_1s;reg msec_1ms;reg [5:0]counts;reg [5:0]countm;reg [1:0]state;reg [3:0]scan;reg [14:0]cnt;reg [7:0]data_out;wire [3:0]ge;wire [3:0]shi;wire [3:0]bai;wire [3:0]qian;always@(posedge sys_clk )//1sif(cnt25m==25'd2*******)begincnt25m<=25'd0;sec_1s<=~sec_1s;endelsecnt25m<=cnt25m+1'b1;always@(posedge sys_clk )//1msif(cnt20n==20'd25000)begincnt20n<=20'd0;msec_1ms<=~msec_1ms;endelsecnt20n<=cnt20n+1'b1;always@(posedge sec_1s ) //计数秒beginif (reset==1'b1)counts<=6'd0;else if (pause==1'b1)counts<=counts;else if (counts<6'd59)counts=counts+1;else counts<=6'd0;endalways@(posedge sec_1s ) //计数分beginif (reset==1'b1)countm<=6'd0;else if (pause==1'b1)countm<=countm;else if (counts==6'd59)if (countm<6'd59)countm=countm+1;elsecountm=6'd0;else countm<=countm;endassign ge=counts%10;assign shi=counts/10;assign bai=countm%10;assign qian=countm/10;always@(posedge msec_1ms)state<=state+1'b1;always@(state)begincase (state)2'b00:scan<=4'b1000;2'b01:scan<=4'b0100;2'b10:scan<=4'b0010;2'b11:scan<=4'b0001;default:scan<=4'b0000;endcaseendalways @(scan)begincase(scan)4'b1000:cnt<=ge;4'b0100:cnt<=shi;4'b0010:cnt<=bai;4'b0001:cnt<=qian;default:cnt=4'b0000;endcaseendalways@(cnt)begincase (cnt)4'b0000 : data_out<=8'b00111111;4'b0001 : data_out<=8'b00000110;4'b0010 : data_out<=8'b01011011;4'b0011 :data_out<=8'b01001111;4'b0100 : data_out<=8'b01100110;4'b0101 : data_out<=8'b01101101;4'b0110 : data_out<=8'b01111101;4'b0111 : data_out<=8'b00000111;4'b1000 : data_out<=8'b01111111;4'b1001 : data_out<=8'b01101111;default : data_out<=8'b00000000;endcaseendendmoduleBCD码的转换module shi10_BCD(data_in,led);input [5:0]data_in;output[7:0]led;reg[3:0]ge,shi;always@(data_in)beginif (data_in<4'd10)shi<=4'b0000;else if (data_in<8'd20)shi<=4'b0001;else if (data_in<8'd30)shi<=4'b0010;else if (data_in<8'd40)shi<=4'b0011;else if (data_in<8'd50)shi<=4'b0100;else if (data_in<8'd60)shi<=4'b0101;else if (data_in<8'd70)shi<=4'b0110;else if (data_in<8'd80)shi<=4'b0111;else if (data_in<8'd90)shi<=4'b1000;elseshi<=4'b1001;endalways @(data_in or shi)ge<=(data_in-shi*4'd10); assign led={shi,ge};endmodule0000-9999显示模块一：modulesysclk(reset,sys_clk,sec_1s,msec_1ms);input sys_clk;input reset;output reg sec_1s,msec_1ms;reg[25:0] cnt25m;reg[25:0] cnt20n;if(cnt25m==25'd25000)begincnt25m<=25'd0;msec_1ms<=~msec_1ms;endelsecnt25m<=cnt25m+1'b1;always@(posedge sys_clk )//1sif(cnt20n==27'd2500000)begincnt20n<=27'd0;sec_1s<=~sec_1s;endelsecnt20n<=cnt20n+1'b1;endmodule模块二：module cnt_10(reset,sec_1s,ge,shi,bai,qian);input sec_1s,reset;output reg [3:0]ge;output reg [3:0]shi;output reg [3:0]bai;output reg [3:0]qian;always @(posedge sec_1s or posedge reset) beginif (reset==1'b1)beginge<=4'b0000;shi<=4'b0000;bai<=4'b0000;qian<=4'b0000;endelse if (ge==4'd9)beginge<=4'b0000;shi=shi+1'b1;if (shi==4'd10)beginshi<=4'b0000;bai=bai+1'b1;if(bai==4'd10)beginbai<=4'b0000;qian=qian+1'b1;if (qian==4'd10)beginqian<=4'b0000;endendendendelsege<=ge+1'b1;endendmodule模块三：moduleymxs(ge,shi,bai,qian,msec_1ms,scan,data_out);input [3:0]ge;input [3:0]shi;input [3:0]bai;input [3:0]qian;input msec_1ms;output [7:0]data_out;output [3:0]scan;reg[7:0]data_out;reg[1:0]state;reg[3:0]scan;reg[3:0]cnt;always@(posedge msec_1ms)state<=state+1'b1;always@(state)begincase (state)2'b00:scan<=4'b1000;2'b01:scan<=4'b0100;2'b10:scan<=4'b0010;2'b11:scan<=4'b0001;default:scan<=4'b0000;endcaseendalways @(scan)begincase(scan)4'b0001:cnt<=ge;4'b1000:cnt<=shi;4'b0100:cnt<=bai;4'b0010:cnt<=qian;default:cnt=4'b0000;endcaseendalways@(cnt)begincase (cnt)4'b0000 : data_out<=8'b00111111;4'b0001 : data_out<=8'b00000110;4'b0010 : data_out<=8'b01011011;4'b0011 : data_out<=8'b01001111;4'b0100 : data_out<=8'b01100110;4'b0101 :data_out<=8'b01101101;4'b0110 : data_out<=8'b01111101;4'b0111 : data_out<=8'b00000111;4'b1000 : data_out<=8'b01111111;4'b1001 : data_out<=8'b01101111;default : data_out<=8'b00000000;endcaseendendmodule顶层模块：module total (reset,sys_clk,data_out,scan);input sys_clk;input reset;output [7:0]data_out;output [3:0]scan;wire msec_1ms;wire sec_1s;wire [3:0] ge;wire [3:0] shi;wire [3:0] bai;wire [3:0] qian; sysclk U1(reset,sys_clk,sec_1s,msec_1ms); cnt_10 U2(reset,sec_1s,ge,shi,bai,qian); ymxsU3(ge2,shi,bai,qian,msec_1ms,scan,data_out);endmodule边沿触发module bianyuanjiance(din,clk,dout);input din,clk;output dout;reg din_dly;wire din_dly_n;reg din_dly2_n;always@(posedge clk)begindin_dly<=din;endassign din_dly_n=~din_dly;always@(posedge clk)din_dly2_n<=din_dly_n;assign dout=din_dly&din_dly2_n;endmodule。