单片机文献中英对照
单片机英文文献及翻译)
Validation and Testing of Design Hardening for Single Event Effects Using the 8051 MicrocontrollerAbstractWith the dearth of dedicated radiation hardened foundries, new and novel techniques are being developed for hardening designs using non-dedicated foundry services. In this paper, we will discuss the implications of validating these methods for the single event effects (SEE) in the space environment. Topics include the types of tests that are required and the design coverage (i.e., design libraries: do they need validating for each application?). Finally, an 8051 microcontroller core from NASA Institute of Advanced Microelectronics (IAμE) CMOS Ultra Low Power Radiation Tolerant (CULPRiT) design is evaluated for SEE mitigative techniques against two commercial 8051 devices.Index TermsSingle Event Effects, Hardened-By-Design, microcontroller, radiation effects.I. INTRODUCTIONNASA constantly strives to provide the best capture of science while operating in a space radiation environment using a minimum of resources [1,2]. With a relatively limited selection of radiation-hardened microelectronic devices that are often two or more generations of performance behind commercialstate-ofthe-art technologies, NASA’s performance of this task is quite challenging. One method of alleviating this is by the use of commercial foundry alternatives with no or minimally invasive design techniques for hardening. This is often called hardened-by-design (HBD).Building custom-type HBD devices using design libraries and automated design tools may provide NASA the solution it needs to meet stringent science performance specifications in a timely,cost-effective, and reliable manner.However, one question still exists: traditional radiation-hardened devices have lot and/or wafer radiation qualification tests performed; what types of tests are required for HBD validation?II. TESTING HBD DEVICES CONSIDERATIONSTest methodologies in the United States exist to qualify individual devices through standards and organizations such as ASTM, JEDEC, and MIL-STD- 883. Typically, TID (Co-60) and SEE (heavy ion and/or proton) are required for device validation. So what is unique to HBD devices?As opposed to a “regular” commercial-off-the-shelf (COTS) device or application specific integrated circuit (ASIC) where no hardening has been performed, one needs to determine how validated is the design library as opposed to determining the device hardness. That is, by using test chips, can we “qualify” a future device using the same library?Consider if Vendor A has designed a new HBD library portable to foundries B and C. A test chip is designed, tested, and deemed acceptable. Nine months later a NASA flight project enters the mix by designing a new device using Vendor A’s library. Does this device require complete radiation qualification testing? To answer this, other questions must be asked.How complete was the test chip? Was there sufficient statistical coverage of all library elements to validate each cell? If the new NASA design uses a partially or insufficiently characterized portion of the design library, full testing might be required. Of course, if part of the HBD was relying on inherent radiation hardness of a process, some of the tests (like SEL in the earlier example) may be waived.Other considerations include speed of operation and operating voltage. For example, if the test chip was tested statically for SEE at a power supply voltage of 3.3V, is the data applicable to a 100 MHz operating frequency at 2.5V? Dynamic considerations (i.e., nonstatic operation) include the propagated effects of Single Event Transients (SETs). These can be a greater concern at higher frequencies.The point of the considerations is that the design library must be known, the coverage used during testing is known, the test application must be thoroughly understood and the characteristics of the foundry must be known. If all these are applicable or have been validated by the test chip, then no testing may be necessary. A task within NASA’s Electronic Parts and Packaging (NEPP) Program was performed to explore these types of considerations.III. HBD TECHNOLOGY EVALUATION USING THE 8051 MICROCONTROLLERWith their increasing capabilities and lower power consumption, microcontrollers are increasingly being used in NASA and DOD system designs. There are existing NASA and DoD programs that are doing technology development to provide HBD. Microcontrollers are one such vehicle that is being investigated to quantify the radiation hardness improvement. Examples of these programs are the 8051 microcontroller being developed by Mission Research Corporation (MRC) and the IAμE (the focus of this study). As these HBD technologies become available, validation of the technology, in the natural space radiation environment, for NASA’s use in spaceflight systems is required.The 8051 microcontroller is an industry standard architecture that has broad acceptance, wide-ranging applications and development tools available. There are numerous commercial vendors that supply this controller or have it integrated into some type of system-on-a-chip structure. Both MRC and IAμE chose this device to demonstrate two distinctly different technologies for hardening. The MRC example of this is to use temporal latches that require specific timing to ensure that single event effects are minimized. The IAμE technology uses ultra low power, and layout and architecture HBD design rules to achieve their results. These are fundamentally different than the approach by Aeroflex-United Technologies Microelectronics Center (UTMC), the commercial vendor of a radiation–hardened 8051, that built their 8051 microcontroller using radiationhardened processes. This broad range of technology within one device structure makes the 8051an ideal vehicle for performing this technology evaluation.The objective of this work is the technology evaluation of the CULPRiT process [3] from IAμE. The process has been baselined against two other processes, the standard 8051 commercial device from Intel and a version using state-of-the-art processing from Dallas Semiconductor. By performing this side-by-side comparison, the cost benefit, performance, and reliability trade study can be done.In the performance of the technology evaluation, this task developed hardware and software for testing microcontrollers. A thorough process was done to optimize the test process to obtain as complete an evaluation as possible. This included taking advantage of the available hardware and writing software that exercised the microcontroller such that all substructures of the processor were evaluated. This process is also leading to a more complete understanding of how to test complex structures, such as microcontrollers, and how to more efficiently test these structures in the future.IV. TEST DEVICESThree devices were used in this test evaluation. The first is the NASA CULPRiT device, which is the primary device to be evaluated. The other two devices are two versions of a commercial 8051, manufactured by Intel and Dallas Semiconductor, respectively.The Intel devices are the ROMless, CMOS version of the classic 8052 MCS-51 microcontroller. They are rated for operation at +5V, over a temperature range of 0 to 70 °C and at a clock speeds of 3.5 MHz to 24 MHz. They are manufactured in Intel’s P629.0 CHMOS III-E process.The Dallas Semiconductor devices are similar in that they are ROMless 8052 microcontrollers, but they are enhanced in various ways. They are rated for operation from 4.25 to 5.5 Volts over 0 to 70 °C at clock speeds up to 25 MHz. They have a second full serial port built in, seven additional interrupts, a watchdog timer, a power fail reset, dual data pointers and variable speed peripheral access. In addition, the core is redesigned so that the machine cycle is shortened for most instructions, resulting in an effective processing ability that is roughly 2.5 times greater (faster) than the standard 8052 device. None of these features, other than those inherent in the device operation, were utilized in order to maximize the similarity between the Dallas and Intel test codes.The CULPRiT technology device is a version of the MSC-51 family compatible C8051 HDL core licensed from the Ultra Low Power (ULP) process foundry. The CULPRiT technology C8051 device is designed to operate at a supply voltage of 500 mV and includes an on-chip input/output signal level-shifting interface with conventional higher voltage parts. The CULPRiT C8051 device requires two separate supply voltages; the 500 mV and the desired interface voltage. The CULPRiT C8051 is ROMless and is intended to be instruction set compatible with the MSC-51 family.V. TEST HARDWAREThe 8051 Device Under Test (DUT) was tested as a component of a functional computer. Aside from DUT itself, the other componentsof the DUT computer were removed from the immediate area of the irradiation beam.A small card (one per DUT package type) with a unique hard-wired identifier byte contained the DUT, its crystal, and bypass capacitors (and voltage level shifters for the CULPRiT DUTs). This "DUT Board" was connected to the "Main Board" by a short 60-conductor ribbon cable. The Main Board had all other components required to complete the DUT Computer, including some which nominally are not necessary in some designs (such as external RAM, external ROM and address latch). The DUT Computer and the Test Control Computer were connected via a serial cable and communications were established between the two by the Controller (that runs custom designed serial interface software). This Controller software allowed for commanding of the DUT, downloading DUT Code to the DUT, and real-time error collection from the DUT during and post irradiation. A 1 Hz signal source provided an external watchdog timing signal to the DUT, whose watchdog output was monitored via an oscilloscope. The power supply was monitored to provide indication of latchup.VI. TEST SOFTWAREThe 8051 test software concept is straightforward. It was designed to be a modular series of small test programs each exercising a specific part of the DUT. Since each test was stand alone, they were loaded independently of each other for execution on the DUT. This ensured that only the desired portion of the 8051 DUT was exercised during the test and helped pinpoint location of errors that occur during testing. All test programs resided on the controller PC until loaded via the serial interface to the DUT computer. In this way, individual tests could have been modified at any time without the necessity of burning PROMs. Additional tests could have also been developed and added without impacting the overall test design. The only permanent code, which was resident on the DUT, was the boot code and serial code loader routines that established communications between the controller PC and the DUT.All test programs implemented:• An external Universal Asynchronous Receive and Transmit device (UART) for transmission of error information and communication to controller computer.• An external real-time clock for data error tag.•A watchdog routine designed to provide visual verification of 8051 health and restart test code if necessary.• A "foul-up" routine to reset program counter if it wanders out of code space.• An external telemetry data storage memory to provide backup of data in the event of an interruption in data transmission.The brief description of each of the software tests used is given below. It should be noted that for each test, the returned telemetry (including time tag) was sent to both the test controller and the telemetry memory, giving the highest reliability that all data is captured.Interrupt –This test used 4 of 6 available interrupt vectors (Serial, External, Timer0 Overflow, and Timer1 Overflow) to trigger routines that sequentially modified a value in the accumulator which was periodically compared to a known value. Unexpected values were transmitted with register information.Logic –This test performed a series of logic and math computations and provided three types of error identifications: 1) addition/subtraction, 2) logic and 3) multiplication/division. All miscompares of computations and expected results were transmitted with other relevant register information.Memory – This test loaded internal data memory at locations D:0x20 through D:0xff (or D:0x20 through D:0x080 for the CULPRiT DUT), indirectly, with an 0x55 pattern. Compares were performed continuously and miscompares were corrected while error information and register values were transmitted.Program Counter -The program counter was used to continuously fetch constants at various offsets in the code. Constants were compared with known values and miscompares were transmitted along with relevant register information. Registers – This test loaded each of four (0,1,2,3) banks of general-purpose registers with either 0xAA (for banks 0 and 2) or 0x55 (for banks 1 and 3). The pattern was alternated in order to test the Program Status Word (PSW) special function register, which controls general-purpose register bank selection. General-purpose register banks were then compared with their expected values. All miscompares were corrected and error information was transmitted.Special Function Registers (SFR) – This test used learned static values of 12 out 21 available SFRs and then constantly compared the learned value with the current one. Miscompares were reloaded with learned value and error information was transmitted.Stack – This test performed arithmetic by pushing and popping operands on the stack. Unexpected results were attributed to errors on the stack or to the stack pointer itself and were transmitted with relevant register information.VII. TEST METHODOLOGYThe DUT Computer booted by executing the instruction code located at address 0x0000. Initially, the device at this location was an EPROM previously loaded with "Boot/Serial Loader" code. This code initialized the DUT Computer and interface through a serial connection to the controlling computer, the "Test Controller". The DUT Computer downloaded Test Code and put it into Program Code RAM (located on the Main Board of the DUT Computer). It then activated a circuit which simultaneously performed two functions: held the DUT reset line active for some time (~10 ms); and, remapped the Test Code residing in the Program Code RAM to locate it to address 0x0000 (the EPROM will no longer be accessible in the DUT Computer's memory space). Upon awaking from the reset, the DUT computer again booted by executing the instruction code at address 0x0000, except this time that code was not be the Boot/Serial Loader code but the Test Code.The Test Control Computer always retained the ability to force the reset/remap function, regardless of the DUT Computer's functionality. Thus, if the test ran without a Single Event Functional Interrupt (SEFI) either the DUT Computer itselfor the Test Controller could have terminated the test and allowed the post-test functions to be executed. If a SEFI occurred, the Test Controller forced a reboot into Boot/Serial Loader code and then executed the post-test functions. During any test of the DUT, the DUT exercised a portion of its functionality (e.g., Register operations or Internal RAM check, or Timer operations) at the highest utilization possible, while making a minimal periodic report to the Test Control Computer to convey that the DUT Computer was still functional. If this reportceased, the Test Controller knew that a SEFI had occurred. This periodic data was called "telemetry". If the DUT encountered an error that was not interrupting the functionality (e.g., a data register miscompare) it sent a more lengthy report through the serial port describing that error, and continued with the test.VIII.DISCUSSIONA. Single Event LatchupThe main argument for why latchup is not an issue for the CULPRiT devices is that the operating voltage of 0.5 volts should be below the holding voltage required for latchup to occur. In addition to this, the cell library used also incorporates the heavy dual guard-barring scheme [4]. This scheme has been demonstrated multiple times to be very effective in rendering CMOS circuits completely immune to SEL up to test limits of 120 MeV-cm2/mg. This is true in circuits operating at 5, 3.3, and 2.5 Volts, as well as the 0.5 Volt CULPRiT circuits. In one case, a 5 Volt circuit fabricated on noncircuits wafers even exhibited such SEL immunity.B. Single Event UpsetThe primary structure of the storage unit used in the CULPRiT devices is the Single Event Resistant Topology (SERT) [5]. Given the SERT cell topology and a single upset node assumption, it is expected that the SERT cell will be completely immune to SEUs occurring internal to the memory cell itself. Obviously there are other things going on. The CULPRiT 8051 results reported here are quite similar to some resultsobtained with a CULPRiT CCSDS lossless compression chip (USES) [6]. The CULPRiT USES was synthesized using exactly the same tools and library as the CULPRiT 8051.With the CULPRiT USES, the SEU cross section data [7] was taken as a function of frequency at two LET values, 37.6 and 58.5 MeV-cm2/mg. In both cases the data fit well to a linear model where cross section is proportional to clock. In the LET 37.6 case, the zero frequency intercept occurred essentially at the zero cross section point, indicating that virtually all of these SEUs are captured SETs from the combinational logic. The LET 58.5 data indicated that the SET (frequency dependent) component is sitting on top of a "dc-bias" component –presumably a second upset mechanism is occurring internal to the SERT cells only at a second, higher LET threshold.The SET mitigation scheme used in the CULPRiT devices is based on the SERT cell's fault tolerant input property when redundant input data is provided to separate storage nodes. The idea is that the redundant input data is provided through a total duplication of combinational logic (referred to as “dual rail design”) such that a simple SET on one rail cannot produce an upset. Therefore, some other upset mechanism must be happening. It is possible that a single particle strike is placing an SET on both halves of the logic streams, allowing an SET to produce an upset. Care was taken to separate the dual sensitive nodes in the SERT cell layouts but the automated place-and-route of the combinatorial logic paths may have placed dual sensitive nodes close enough.At this point, the theory for the CULPRiT SEU response is that at about an LET of 20, the energy deposition is sufficiently wide enough (and in the right locations) to produce an SET in both halves of the combinatorial logic streams. Increasing LET allows for more regions to be sensitive to this effect, yielding a larger cross section. Further, the second SEU mechanism that starts at an LET of about 40-60 has to do with when the charge collection disturbance cloud gets large enough to effectively upset multiples of the redundant storage nodes within the SERT cell itself. In this 0.35 μm library, the node separation is several microns. However, since it takes less charge to upset a node operating at 0.5 Volts, with transistors having effective thresholds around 70 mV, this is likely the effect being observed. Also the fact that the per-bit memory upset cross section for the CULPRiT devices and the commercial technologies are approximately equal, as shown in Figure 9, indicates that the cell itself has become sensitive to upset.IX. SUMMARYA detailed comparison of the SEE sensitivity of a HBD technology (CULPRiT) utilizing the 8051 microcontroller as a test vehicle has been completed. This paper discusses the test methodology used and presents a comparison of the commercial versus CULPRiT technologies based on the data taken. The CULPRiT devices consistently show significantly higher threshold LETs and an immunity to latchup. In all but the memory test at the highest LETs, the cross section curves for all upset events is one to two orders of magnitude lower than the commercial devices. Additionally, theory is presented, based on the CULPRiT technology, that explain these results.This paper also demonstrates the test methodology for quantifying the level of hardness designed into a HBD technology. By using the HBD technology in a real-world device structure (i.e., not just a test chip), and comparing results to equivalent commercial devices, one can have confidence in the level of hardness that would be available from that HBD technology in any circuit application.ACKNOWLEDGEMENTSThe authors of this paper would like to acknowledge the sponsors of this work. These are the NASA Electronic Parts and Packaging Program (NEPP), NASA Flight Programs, and the Defense Threat Reduction Agency (DTRA).。
单片机英文参考文献
单片机英文参考文献篇一：5-单片机+外文文献+英文文献+外文翻译中英对照AT89C51的介绍（原文出处：http：///resource/）描述AT89C51是一个低电压，高性能CMOS8位单片机带有4K字节的可反复擦写的程序存储器（PENROM）。
和128字节的存取数据存储器（RAM），这种器件采用ATMEL公司的高密度、不容易丢失存储技术生产，并且能够与MCS-51系列的单片机兼容。
片内含有8位中央处理器和闪烁存储单元，有较强的功能的AT89C51单片机能够被应用到控制领域中。
功能特性AT89C51提供以下的功能标准：4K字节闪烁存储器，128字节随机存取数据存储器，32个I/O口，2个16位定时/计数器，1个5向量两级中断结构，1个串行通信口，片内震荡器和时钟电路。
另外，AT89C51还可以进行0HZ的静态逻辑操作，并支持两种软件的节电模式。
闲散方式停止中央处理器的工作，能够允许随机存取数据存储器、定时/计数器、串行通信口及中断系统继续工作。
掉电方式保存随机存取数据存储器中的内容，但震荡器停止工作并禁止其它所有部件的工作直到下一个复位。
引脚描述VCC：电源电压 GND：地 P0口：P0口是一组8位漏极开路双向I/O口，即地址/数据总线复用口。
作为输出口时，每一个管脚都能够驱动8个TTL电路。
当“1”被写入P0口时，每个管脚都能够作为高阻抗输入端。
P0口还能够在访问外部数据存储器或程序存储器时，转换地址和数据总线复用，并在这时激活内部的上拉电阻。
P0口在闪烁编程时，P0口接收指令，在程序校验时，输出指令，需要接电阻。
沈阳航空工业学院电子工程系毕业设计（外文翻译）P1口：P1口一个带内部上拉电阻的8位双向I/O口，P1的输出缓冲级可驱动4个TTL电路。
对端口写“1”，通过内部的电阻把端口拉到高电平，此时可作为输入口。
因为内部有电阻，某个引脚被外部信号拉低时输出一个电流。
闪烁编程时和程序校验时，P1口接收低8位地址。
单片机英文文献及翻译
附录A英文文献翻译原文Temperature Control Using a Microcontroller:An Interdisciplinary Undergraduate Engineering Design ProjectJames S. McDonaldDepartment of Engineering ScienceTrinity UniversitySan Antonio, TX 78212AbstractThis paper describes an interdisc iplinary design project which was done under the author’s supervision by a group of four senior students in the Department of Engineering Science at Trinity University. The objective of the project was to develop a temperature control system for an air-filled chamber. The system was to allow entry of a desired chamber temperature in a prescribed range and to exhibit overshoot and steady-state temperature error of less than 1 degree Kelvin in the actual chamber temperature step response. The details of the design developed by this group of students, based on a Motorola MC68HC05 family microcontroller, are described. The pedagogical value of the problem is also discussed through a description of some of the key steps in the design process. It is shown that the solution requires broad knowledge drawn from several engineering disciplines including electrical, mechanical, and control systems engineering.1 IntroductionThe design project which is the subject of this paper originated from a real-world application.A prototype of a microscope slide dryer had been developed around an OmegaTM modelCN-390 temperature controller, and the objective was to develop a custom temperature control system to replace the Omega system. The motivation was that a custom controller targeted specifically for the application should be able to achieve the same functionality at a much lower cost, as the Omega system is unnecessarily versatile and equipped to handle a wide variety of applications.The mechanical layout of the slide dryer prototype is shown in Figure 1. The main element of the dryer is a large, insulated, air-filled chamber in which microscope slides, each with a tissue sample encased in paraffin, can be set on caddies. In order that the paraffin maintain the proper consistency, the temperature in the slide chamber must be maintained at a desired (constant) temperature. A second chamber (the electronics enclosure) houses a resistive heater and the temperature controller, and a fan mounted on the end of the dryer blows air across theheater, carrying heat into the slide chamber. This design project was carried out during academic year 1996–97 by four students under the author’s supervision as a Senior Design project in the Department of Engineering Science at Trinity University. The purpose of this paper isto describe the problem and the students’ solution in some detail, and to discuss some of the pedagogical opportunities offered by an interdisciplinary design project of this type. The students’ own report was presented a t the 1997 National Conference on Undergraduate Research [1]. Section 2 gives a more detailed statement of the problem, including performance specifications, and Section 3 describes the students’ design. Section 4 makes up the bulk of the paper, and discusses in some detail several aspects of the design process which offer unique pedagogical opportunities. Finally, Section 5 offers some conclusions.2 Problem StatementThe basic idea of the project is to replace the relevant parts of the functionality of an Omega CN-390 temperature controller using a custom-designed system. The application dictates that temperature settings are usually kept constant for long periods of time, but it’s nonetheless important that step changes be tracked in a “reasonable” manner. Thus the main requirements boil down to·allowing a chamber temperature set-point to be entered,·displaying both set-point and actual temperatures, and·tracking step changes in set-point temperature with acceptable rise time, steady-state error, and overshoot.Although not explicitly a part of the specifications in Table 1, it was clear that the customer desired digital displays of set-point and actual temperatures, and that set-point temperature entry should be digital as well (as opposed to, say, through a potentiometer setting).3 System DesignThe requirements for digital temperature displays and setpoint entry alone are enough to dictate that a microcontrollerbased design is likely the most appropriate. Figure 2 shows a block diagram of the stude nts’ design.The microcontroller, a MotorolaMC68HC705B16 (6805 for short), is the heart of the system. It accepts inputs from a simple four-key keypad which allow specification of the set-point temperature, and it displays both set-point and measured chamber temperatures using two-digit seven-segment LED displays controlled by a display driver. All these inputs and outputs are accommodated by parallel ports on the 6805. Chamber temperature is sensed using apre-calibrated thermistor and input via one of the 6805’s analog-to-digital inputs. Finally, a pulse-width modulation (PWM) output on the 6805 is used to drive a relay which switches line power to the resistive heater off and on.Figure 3 shows a more detailed schematic of the electronics and their interfacing to the 6805. The keypad, a Storm 3K041103, has four keys which are interfaced to pins PA0{ PA3 of Port A, configured as inputs. One key functions as a mode switch. Two modes are supported: set mode and run mode. In set mode two of the other keys are used to specify the set-point temperature: one increments it and one decrements. The fourth key is unused at present. The LED displays are driven by a Harris Semiconductor ICM7212 display driver interfaced to pins PB0{PB6 of Port B, configured as outputs. The temperature-sensing thermistor drives, through a voltage divider, pin AN0 (one of eight analog inputs). Finally, pin PLMA (one of two PWM outputs) drives the heater relay.Software on the 6805 implements the temperature control algorithm, maintains the temperature displays, and alters the set-point in response to keypad inputs. Because it is not complete at this writing, software will not be discussed in detail in this paper. The control algorithm in particular has not been determined, but it is likely to be a simple proportional controller and certainly not more complex than a PID. Some control design issues will be discussed in Section 4, however.4 The Design ProcessAlthough essentially the project is just to build a thermostat, it presents many nice pedagogical opportunities. The knowledge and experience base of a senior engineering undergraduate are just enough to bring him or her to the brink of a solution to various aspects of the problem. Yet, in each case, realworld considerations complicate the situation significantly.Fortunately these complications are not insurmountable, and the result is a very beneficial design experience. The remainder of this section looks at a few aspects of the problem which present the type of learning opportunity just described. Section 4.1 discusses some of the features of a simplified mathematical model of the thermal properties of the system and how it can beeasily validated experimentally. Section 4.2 describes how realistic control algorithm designs can be arrived at using introductory concepts in control design. Section 4.3 points out some important deficiencies of such a simplified modeling/control design process and how they can be overcome through simulation. Finally, Section 4.4 gives an overview of some of the microcontroller-related design issues which arise and learning opportunities offered.4.1 MathematicalModelLumped-element thermal systems are described in almost any introductory linear control systems text, and just this sort of model is applicable to the slide dryer problem. Figure 4 shows a second-order lumped-element thermal model of the slide dryer. The state variables are the temperatures Ta of the air in the box and Tb of the box itself. The inputs to the system are the power output q(t) of the heater and the ambient temperature T¥. ma and mb are the masses of the air and the box, respectively, and Ca and Cb their specific heats. μ1 and μ2 are heat transfer coefficients from the air to the box and from the box to the external world, respectively.It’s not hard to show that the (linearized) state equationscorresponding to Figure 4 areTaking Laplace transforms of (1) and (2) and solving for Ta(s), which is the output of interest, gives the following open-loop model of the thermal system:where K is a constant and D(s) is a second-order polynomial.K, tz, and the coefficients ofD(s) are functions of the variousparameters appearing in (1) and (2).Of course the various parameters in (1) and (2) are completely unknown, but it’s not hard to show that, regardless of their values, D(s) has two real zeros. Therefore the main transfer function of interest (which isthe one from Q(s), since we’ll assume constant ambient temperature) can be writtenMoreover, it’s not too hard to show that 1=tp1 <1=tz <1=tp2, i.e., that the zero lies between the two poles. Both of these are excellent exercises for the student, and the result is the openloop pole-zero diagram of Figure 5.Obtaining a complete thermal model, then, is reduced to identifying the constant K and the three unknown time constants in (3). Four unknown parameters is quite a few, but simple experiments show that 1=tp1 _ 1=tz;1=tp2 so that tz;tp2 _ 0 are good approximations. Thus the open-loop system is essentially first-order and can therefore be written(where the subscript p1 has been dropped).Simple open-loop step response experiments show that,for a wide range of initial temperatures and heat inputs, K _0:14 _=W and t _ 295 s.14.2 Control System DesignUsing the first-order model of (4) for the open-loop transfer function Gaq(s) and assuming for the moment that linear control of the heater power output q(t) is possible, the block diagram of Figure 6 represents the closed-loop system. Td(s) is the desired, or set-point, temperature,C(s) is the compensator transfer function, and Q(s) is the heater output in watts.Given this simple situation, introductory linear control design tools such as the root locus method can be used to arrive at a C(s) which meets the step response requirements on rise time, steady-state error, and overshoot specified in Table 1. The upshot, of course, is that a proportional controller with sufficient gain can meet all specifications. Overshoot is impossible, and increasing gains decreases both steady-state error and rise time.Unfortunately, sufficient gain to meet the specifications may require larger heat outputs than the heater is capable of producing. This was indeed the case for this system, and the result is that the rise time specification cannot be met. It is quite revealing to the student how useful such an oversimplified model, carefully arrived at, can be in determining overall performance limitations.4.3 Simulation ModelGross performance and its limitations can be determined using the simplified model of Figure 6, but there are a number of other aspects of the closed-loop system whose effects on performance are not so simply modeled. Chief among these are·quantization error in analog-to-digital conversion of the measured temperature and· the use of PWM to control the heater.Both of these are nonlinear and time-varying effects, and the only practical way to study them is through simulation (or experiment, of course).Figure 7 shows a SimulinkTM block diagram of the closed-loop system which incorporates these effects. A/D converter quantization and saturation are modeled using standard Simulink quantizer and saturation blocks. Modeling PWM is more complicated and requires a customS-function to represent it.This simulation model has proven particularly useful in gauging the effects of varying thebasic PWM parameters and hence selecting them appropriately. (I.e., the longer the period, the larger the temperature error PWM introduces. On the other hand, a long period is desirable to avoid excessiv e relay “chatter,” among other things.) PWM is often difficult for students to grasp, and the simulation model allows an exploration of its operation and effects which is quite revealing.4.4 The MicrocontrollerSimple closed-loop control, keypad reading, and display control are some of the classic applications of microcontrollers, and this project incorporates all three. It is therefore an excellent all-around exercise in microcontroller applications. In addition, because the project isto produce an actua l packaged prototype, it won’t do to use a simple evaluation board with theI/O pins jumpered to the target system. Instead, it’s necessary to develop a complete embedded application. This entails the choice of an appropriate part from the broad range offered in a typical microcontroller family and learning to use a fairly sophisticated development environment. Finally, a custom printed-circuit board for the microcontroller and peripherals must be designed and fabricated.Microcontroller Selection. In view of existing local expertise, the Motorola line of microcontrollers was chosen for this project. Still, this does not narrow the choice down much. A fairly disciplined study of system requirements is necessary to specify which microcontroller, out of scores of variants, is required for the job. This is difficult for students, as they generally lack the experience and intuition needed as well as the perseverance to wade through manufacturers’ selection guides.Part of the problem is in choosing methods for interfacing the various peripherals (e.g., what kind of display driver should be used?). A study of relevant Motorola application notes [2, 3, 4] proved very helpful in understandingwhat basic approaches are available, and what microcontroller/peripheral combinations should be considered.The MC68HC705B16 was finally chosen on the basis of its availableA/D inputs and PWMoutputs as well as 24 digital I/O lines. In retrospect this is probably overkill, as only oneA/D channel, one PWM channel, and 11 I/O pins are actually required (see Figure 3). The decision was made to err on the safe side because a complete development system specific to the chosen part was necessary, and the project budget did not permit a second such system to be purchased should the firstprove inadequate.Microcontroller Application Development. Breadboarding of the peripheral hardware, development of microcontroller software, and final debugging and testing of a customprinted-circuit board for the microcontroller and peripherals all require a development environment of some kind. The choice of a development environment, like that of themicrocontroller itself, can be bewildering and requires some faculty expertise. Motorola makes three grades of development environment ranging from simple evaluation boards (at around $100) to full-blown real-time in-circuit emulators (at more like $7500). The middle option was chosen for this project: the MMEVS, which consists of _ a platform board (which supports all 6805-family parts), _ an emulator module (specific to B-series parts), and _ a cable and target head adapter (package-specific). Overall, the system costs about $900 and provides, with some limitations, in-circuit emulation capability. It also comes with the simple but sufficient software development environment RAPID [5].Students find learning to use this type of system challenging, but the experience they gain in real-world microcontroller application development greatly exceeds the typical first-course experience using simple evaluation boards.Printed-Circuit Board. The layout of a simple (though definitely not trivial) printed-circuit board is another practical learning opportunity presented by this project. The final board layout, with package outlines, is shown (at 50% of actual size) in Figure 8. The relative simplicity of the circuit makes manual placement and routing practical—in fact, it likely gives better results than automatic in an application like this—and the student is therefore exposed to fundamental issues of printed-circuit layout and basic design rules. The layout software used was the very nice package pcb,2 and the board was fabricated in-house with the aid of our staff electronics technician.5 ConclusionThe aim of this paper has been to describe an interdisciplinary, undergraduate engineering design project: a microcontroller- based temperature control system with digital set-point entry and set-point/actual temperature display. A particular design of such a system has been described, and a number of design issues which arise—from a variety of engineering disciplines—have been discussed. Resolution of these issues generally requires knowledge beyond that acquired in introductory courses, but realistically accessible to advance undergraduate students, especiallywith the advice and supervision of faculty.Desirable features of the problem, from a pedagogical viewpoint, include the use of a microcontroller with simple peripherals, the opportunity to usefully apply introductorylevel modeling of physical systems and design of closed-loop controls, and the need for relatively simple experimentation (for model validation) and simulation (for detailed performance prediction). Also desirable are some of the technologyrelated aspects of the problem including practical use of resistive heaters and temperature sensors (requiring knowledge of PWM and calibration techniques, respectively), microcontroller selection and use of development systems, and printedcircuit design.AcknowledgementsThe author would like to acknowledge the hard work, dedication, and ability shown by the students involved in this project: Mark Langsdorf, Matt Rall, PamRinehart, and David Schuchmann. It is their project, and credit for its success belongs to them.References[1] M. Langsdorf, M. Rall, D. Schuchmann, and P. Rinehart,“Temperature control of a microscope slide dryer,” in1997 National Conference on Undergraduate Research,(Austin, TX), April 1997. Poster presentation.[2] Motorola, Inc., Phoenix, AZ, Temperature Measurementand Display Using the MC68HC05B4 and the MC14489,1990. Motorola SemiconductorApplicationNote AN431.[3] Motorola, Inc., Phoenix, AZ, HC05 MCU LED DriveTechniques Using the MC68HC705J1A, 1995. MotorolaSemiconductor Application Note AN1238.[4] Motorola, Inc., Phoenix, AZ, HC05MCU Keypad DecodingTechniques Using the MC68HC705J1A, 1995. MotorolaSemiconductor Application Note AN1239.[5] Motorola, Inc., Phoenix, AZ, RAPID Integrated DevelopmentEnvironment User’s Manual, 1993. (RAPID wasdeveloped by P & E Microcomputer Systems, Inc.).附录B英文文献翻译中文单片机温度控制：一个跨学科的本科生工程设计项目JamesS.McDonald工程科学系三一大学德克萨斯州圣安东尼奥市78212摘要本文所描述的是作者领导由四个三一大学高年级学生组成的团队进行的一个跨学科工程项目的设计。
单片机基础外文翻译参考文献
单片机基础外文翻译参考文献(文档含中英文对照即英文原文和中文翻译)原文:Fundamentals of Single-chip MicrocomputerDr. Dobbs MacintoshJournalAbstractT h e s i n gl e-chi p m i c r o com pu t er i s t h e cul m i na t i on of bo t h t h e d e v el opm e nt o f t h e di gi t al c om p ut e r a nd t h e i nt e gra t e d c i r c ui t a rgu a b l y t h e t ow m o s t s i gn i fi c ant i nv en t i on s of t h e 20t h ce n t u r y .T h es e t o w t yp e s o f a rc hi t e c t u r e a r e fo un d i n s i n gl e-c hi pm i c r o com pu t e r.S om e e m p l o y t h e s pl i t p ro gr a m/d at a m em o r y o f t h e H a r v a rd a r ch i t e ct u r e, s ho wn i n F i g.3-5A-1, ot h er s f o l l o w t h e p hi l o so ph y,w i d e l y a d a p t ed f o r ge n e r al-pu rp os e com p ut e rs an d m i c r op r oc e s s o rs,of m ak i n g n o l o gi c al di s t i nc t i on be t w ee n p ro gr a m a n d d at a m em o r y a s i n t h e P r i n c et on ar c hi t e ct u r e.In ge n e r a l t er m s a si n gl e-c hi p m i cro c om put e r i s c ha r ac t e ri z ed b y t h e i n co r po r at i o n o f al l t h e u ni t s o f a c om put e r i n t o a s i n gl e d e vi c e.Keyword: Single-chip Microcomputer ROM RAM Programming Algorithm Features• Compatible with MCS-51™ Products• 4K Bytes of In-System Reprogrammable Flash Memory– Endurance: 1,000 Write/Erase Cycles• Fully Static Operation: 0 Hz to 24 MHz• Three-level Program Memory Lock• 128 x 8-bit Internal RAM• 32 Programmable I/O Lines• Two 16-bit Timer/Counters• Six Interrupt Sources• Programmable Serial Channel• Low-power Idle and Power-down ModesDescriptionThe AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer with 4Kbytes of Flash programmable and erasable read only memory (PEROM). The deviceis manufactured using Atmel’s high-density nonvolatile memory technology and iscompatible with the industry-standard MCS-51 instruction set and pinout. Theon-chipFlash allows the program memory to be reprogrammed in-system or by a conventionalnonvolatile memory programmer. By combining a versatile 8-bit CPU with Flashon a monolithic chip, the Atmel AT89C51 is a powerful microcomputer which providesa highly-flexible and cost-effective solution to many embedded controlapplications.The AT89C51 provides the following standard features: 4Kbytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bittimer/counters, a five vector two-level interrupt architecture,a full duplex serial port, on-chip oscillator and clock circuitry.In addition, the AT89C51 is designed with static logicfor operation down to zero frequency and supports twosoftware selectable power saving modes. The Idle Modestops the CPU while allowing the RAM, timer/counters,serial port and interrupt system to continue functioning. ThePower-down Mode saves the RAM contents but freezesthe oscillator disabling all other chip functions until the nexthardware reset.Pin ConfigurationsBlock DiagramPin DescriptionVCCSupply voltage.GNDGround.Port 0Port 0 is an 8-bit open-drain bi-directional I/O port. As anoutput port, each pin can sink eight TTL inputs. When 1sare written to port 0 pins, the pins can be used as highimpedanceinputs.Port 0 may also be configured to be the multiplexed loworderaddress/data bus during accesses to external programand data memory. In this mode P0 has internalpullups.Port 0 also receives the code bytes during Flash programming,and outputs the code bytes during programverification. External pullups are required during program verification.Port 1Port 1 is an 8-bit bi-directional I/O port with internal pullups.The Port 1 output buffers can sink/source four TTL inputs.When 1s are written to Port 1 pins they are pulled high bythe internal pullups and can be used as inputs. As inputs,Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pullups.Port 1 also receives the low-order address bytes during Flash programming and verification.Port 2Port 2 is an 8-bit bi-directional I/O port with internal pullups.The Port 2 output buffers can sink/source four TTL inputs.When 1s are written to Port 2 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pullups.Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application, it uses strong internal pullups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register.Port 2 also receives the high-orderaddress bits and some control signals during Flash programming and verification.Port 3Port 3 is an 8-bit bi-directional I/O port with internal pullups.The Port 3 output buffers can sink/source four TTL inputs.When 1s are written to Port 3 pins they are pulled high by the internal pullups and can be used as inputs. As inputs,Port 3 pins that are externally being pulled low will source current (IIL) because of the pullups.Port 3 also serves the functions of various special features of the AT89C51 as listed below:Port 3 also receives some control signals for Flash programmingand verification.ALE/PROGAddress Latch Enable output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming.In normal operation ALE is emitted at a constant rate of 1/6the oscillator frequency, and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory.If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.PSENProgram Store Enable is the read strobe to external program memory.When theAT89C51 is executing code from external programmemory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory.EA/VPPExternal Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH.Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to VCC for internal program executions. This pin also receives the 12-volt programming enable voltage (VPP) during Flash programming, for parts that require 12-volt VPP.XTAL1Input to the inverting oscillator amplifier and input to the internal clock operating circuit.XTAL2Output from the inverting oscillator amplifier.Oscillator CharacteristicsXTAL1 and XTAL2 are the input and output, respectively,of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Figure 1. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed.Idle ModeIn idle mode, the CPU puts itself to sleep while all the onchip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset. It should be noted that when idle is terminated by a hard ware reset, the device normally resumes programexecution,from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory.Figure 1. Oscillator ConnectionsFigure 2. External Clock Drive ConfigurationPower-down ModeIn the power-down mode, the oscillator is stopped, and the instruction that invokes power-down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the power-down mode is terminated. The only exit from power-down is a hardware reset. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize.Program Memory Lock BitsOn the chip are three lock bits which can be left unprogrammed (U) or can be programmed (P) to obtain the additional features listed in the table below.When lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset. If the device is powered up without a reset, the latch initializes to a random value, and holds that value until reset is activated. It is necessary that the latched value of EA be in agreement with the current logic level at that pin in order for the device to function properly.Programming the FlashThe AT89C51 is normally shipped with the on-chip Flash memory array in the erased state (that is, contents = FFH) and ready to be programmed. The programming interface accepts either a high-voltage (12-volt) or a low-voltage (VCC) program enable signal. The low-voltage programming mode provides a convenient way to program theAT89C51 inside the user’s system, while the high-voltage programming mode is compatible with conventional thirdparty Flash or EPROM programmers. The AT89C51 is shipped with either the high-voltage or low-voltage programming mode enabled. The respective top-side marking and device signature codes are listed in the following table.The AT89C51 code memory array is programmed byte-bybyte in either programming mode. To program any nonblank byte in the on-chip Flash Memory, the entire memory must be erased using the Chip Erase Mode.Programming Algorithm: Before programming the AT89C51, the address, data and control signals should be set up according to the Flash programming mode table and Figure 3 and Figure 4. To program the AT89C51, take the following steps.1. Input the desired memory location on the address lines.2. Input the appropriate data byte on the data lines.3. Activate the correct combination of control signals.4. Raise EA/VPP to 12V for the high-voltage programming mode.5. Pulse ALE/PROG once to program a byte in the Flash array or the lock bits. The byte-write cycle is self-timed and typically takes no more than 1.5 ms.Repeat steps 1 through 5, changing the address and data for the entire array or until the end of the object file is reached.Data Polling: The AT89C51 features Data Polling to indicate the end of a write cycle. During a write cycle, an attempted read of the last byte written will result in the complement of the written datum on PO.7. Once the write cycle has been completed, true data are valid on all outputs, and the next cycle may begin. Data Polling may begin any time after a write cycle has been initiated.Ready/Busy: The progress of byte programming can also be monitored by theRDY/BSY output signal. P3.4 is pulled low after ALE goes high during programming to indicate BUSY. P3.4 is pulled high again when programming is done to indicate READY.Program Verify: If lock bits LB1 and LB2 have not been programmed, the programmed code data can be read back via the address and data lines for verification. The lock bits cannot be verified directly. Verification of the lock bits is achieved by observing that their features are enabled.Chip Erase: The entire Flash array is erased electrically by using the proper combination of control signals and by holding ALE/PROG low for 10 ms. The code array is written with all “1”s. The chip erase operatio n must be executed before the code memory can be re-programmed.Reading the Signature Bytes: The signature bytes are read by the same procedure as a normal verification of locations 030H, 031H, and 032H, except that P3.6 and P3.7 must be pulled to a logic low. The values returned are as follows.(030H) = 1EH indicates manufactured by Atmel(031H) = 51H indicates 89C51(032H) = FFH indicates 12V programming(032H) = 05H indicates 5V programmingProgramming InterfaceEvery code byte in the Flash array can be written and the entire array can be erasedby using the appropriate combination of control signals. The write operation cycle is selftimed and once initiated, will automatically time itself to completion. All major programming vendors offer worldwide support for the Atmel microcontroller series. Please contact your local programming vendor for the appropriate software revision.译文:单片机基础摘要：单片机是电脑和集成电路发展的巅峰，有据可查的是它们也是20世纪最意义的两大发明。
plc单片机 毕业论文文献翻译 中英文对照
外文翻译：The monolithic In order to prevent without authorization the visit or the copy monolithic integrated circuit machine in the procedure, the majority of monolithic integrated circuits all has the encryption to lock the localization or the encryption byte, by protects the internal procedure. If in programming time encrypts locks the localization to enable (locking), is unable with the ordinary programming directly reading in the monolithic integrated circuit the procedure, this is the so-called copy protection or says the fixed function. In fact, such protective measures are very frail, is very easily explained. The monolithic integrated circuit aggressor with the aid of the special purpose equipment or the self-made equipment, using the monolithic integrated circuit chip design in loophole or the software flaw, through the many kinds of technical method, may withdraw the essential information from the chip, gains in the monolithic integrated circuit the procedure. Therefore, has the newest technology extremely as electronic products project engineer which the essential understanding current monolithic integrated circuit attacks, achieves knows oneself and the other side, knows fairly well, can effectively prevent oneself spends the product which the massive moneys and the time laboriously designs the matter occurrence which is counterfeited by a others night between.monolithic integrated circuits attacks technology：At present, attacks the monolithic integrated circuit mainly to have four kind of technologies, respectively is:This technical usual use processor correspondence connection and in the use agreement, the encryption algorithm or these algorithm security loophole carries on the attack. The software attack obtains the success a case in point is to early A T M E L A the T 89 C series monolithic integrated circuit attack. The aggressor has used in this series monolithic integrated circuit cleaning operation succession design loophole, uses from arranges the procedure to lock the localization after the cleaning encryption, stops the next step of cleaning internal program memory data the operation, thus makes to add the dense monolithic integrated circuit not to turn the encryption monolithic integrated circuit, then use programming read-out internal procedure.This technology usually monitors the processor by the high time resolution when the normal operation all power sources and the connection connection simulation characteristic, and through monitors its electromagnetic radiation characteristic to implement the attack. Because the monolithic integrated circuit is an active electronic device, when it carries out the different instruction, the corresponding mains input consumption also correspondingly changes. Like this analyzes and examines these changes through the use special electronic surveying instrument and mathematics statistical method, then gains in the monolithic integrated circuit the specific essential information.the mistake has the technology This technical use exceptionally working condition causes the processor to make a mistake, then provides the extra visit to carry on the attack. Uses the most widespread mistake to have the attack method including the voltage impact and the clock impact. The low voltage and the high voltage attack may usefor to forbid the protection circuit work or to fortected the information. The power source and the clock transient state jump may affect the single scroll instruction in certain processors the decoding and the ece the processor to carry out the misoperation. Perhaps the clock transient state jump can reposition the protection circuit but not to be able to destroy is proxecution.This technology is the direct exposed chip interior segment, then the observation, holds controls, disturbs the monolithic integrated circuit by to achieve the attack goal.In order to facilitate in order to, the people divide into above four kind of attacks technology two kinds, a kind is the invasion attack (physical attack), this kind of attack needs to destroy the seal, then with the aid of the semiconductor test facility, the microscope and the micro locator, several hours even several week time can complete on the special laboratory flower. All micro probes technology all belongs to the invasion attack. Moreover three methods belong to the non- invasion attack, the monolithic integrated circuit which attacks cannot by the physical damage. In certain situation non- invasion attacks is specially dangerous, this is because the non- invasion attack needs the equipment usually to be possible the self-restraint and the promotion, therefore is extremely inexpensive.The majority of non- invasions attack needs the aggressor to have the good processor knowledge and the software knowledge. Is opposite with it, the invasion probe attack then does not need too many initial knowledge,moreover usually may use the one whole set similar technology to cope with the width scope the product. Therefore, the attack often starts to the monolithic integrated circuit from the invasion reverse engineering, the accumulation experience is helpful to the development more inexpensive and the fast non- invasion attack technology.Last step will be seeks the protection melt silk the position and protects the melt silk to expose under the ultraviolet ray. With enlargement factor at least 100 time of microscopes, inputs the foot from the programming voltage the segment to track generally, seeks the protection melt silk.This technical use exceptionally working condition causes the processor to make a mistake, then provides the extra visit to carry on the attack. Uses the most widespread mistake to have the attack method including the voltage impact and the clock impact. The low voltage and the high voltage attack may use for to forbid the protection circuit work or to force the processor to carry out the misoperation. Perhaps the clock transient state jump can reposition the protection circuit but not to be able to destroy is protected the information. The power source and the clock transient state jump may affect the single scroll instruction in certain processors the decoding and the execution.(4) probe technologyThis technology is the direct exposed chip interior segment, then the observation, holds controls, disturbs the monolithic integrated circuit by to achieve the attack goal.In order to facilitate in order to, the people divide into above four kindof attacks technology two kinds, a kind is the invasion attack (physical attack), this kind of attack needs to destroy the seal, then with the aid of the semiconductor test facility, the microscope and the micro locator, several hours even several week time can complete on the special laboratory flower. All micro probes technology all belongs to the invasion attack. Moreover three methods belong to the non- invasion attack, the monolithic integrated circuit which attacks cannot by the physical damage. In certain situation non- invasion attacks is specially dangerous, this is because the non- invasion attack needs the equipment usually to be possible the self-restraint and the promotion, therefore is extremely inexpensive.The majority of non- invasions attack needs the aggressor to have the good processor knowledge and the software knowledge. Is opposite with it, the invasion probe attack then does not need too many initial knowledge,moreover usually may use the one whole set similar technology to cope with the width scope the product. Therefore, the attack often starts to the monolithic integrated circuit from the invasion reverse engineering, the accumulation experience is helpful to the development more inexpensive and the fast non- invasion attack technology.3 invasions attacks general process：The invasion attack first step uncovers the chip seal. Some two methods may achieve this goal: The first kind is dissolves the chip seal completely, the exposed metal segment. The second kind is only moves above the silicon nucleus plastic seal. The first method needs the chip to tests on the jig, with the aid of Taiwan to operate. The second method except needs to have the aggressor certain knowledge and Wants outside skill, but also needs individual wisdom and the patience, but operates relatively quite is convenient.Above the chip plastic may use the knife to open, around the chip epoxy resin may use the aqua fortis perish. The hot aqua fortis can dissolve the chip seal but not to be able to affect the chip and the segment. This process carries on generally under the extremely dry condition, because the water existence possibly can corrode already the aluminum wire connection which exposes.Then first uses the acetone in the supersonic pond to clean this chip by except the remaining nitric acid, then cleans with the clear water by and is dry except the salinity. Not the supersonic pond, jumps over generally this step. In this kind of situation, the chip surface can a little dirty, but not too affects the ultraviolet ray to the chip operation effect.Last step will be seeks the protection melt silk the position and protects the melt silk to expose under the ultraviolet ray. With enlargement factor at least 100 time of microscopes, inputs the foot from the programming voltage the segment to track generally, seeks the protection melt silk.If does not have the microscope, then uses the chip different partially exposes to the ultraviolet ray under and the observed result way carries on the simple search. When operation applies not the opaque slip of paper cover chipby to protect the program memory not by the ultraviolet ray cleaning. Will protect the melt silk to expose in the ultraviolet ray next 5 ~ 10 minutes can broken the protection position protective function, afterwards, will use the simple programming to be possible the direct readout program memory content.Regarding used the protective layer to protect E E P R O the M unit the monolithic integrated circuit to say that, the use ultraviolet ray repositioned the protection circuit is not feasible. Regarding this kind of type monolithic integrated circuit, uses the micro probe technology reading the memory content generally. Opens after the chip seal, puts in the chip under the microscope to be able very easy finding中文翻译单片机为了防止未经授权访问或拷贝单片机的机内程序，大部分单片机都带有加密锁定位或者加密字节，以保护片内程序。
(完整版)MCS-51系列单片机中英文资料对照外文翻译文献综述
MCS-51系列单片机中英文资料对照外文翻译文献综述Structure and function of the MCS-51 seriesStructure and function of the MCS-51 series one-chip computer MCS-51 is a name of a piece of one-chip computer series which Intel Company produces. This company introduced 8 top-grade one-chip computers of MCS-51 series in 1980 after introducing 8 one-chip computers of MCS-48 series in 1976. It belong to a lot of kinds this line of one-chip computer the chips have, such as 8051, 8031, 8751, 80C51BH, 80C31BH,etc., their basic composition, basic performance and instruction system are all the same.8051 daily representatives-51 serial one-chip computers.A one-chip computer system is made up of several following parts: (1) One microprocessor of 8 (CPU). ( 2) At slice data memory RAM (128B/256B),it use not depositing not can reading /data that write, such as result not middle of operation, final result and data wanted to show, etc. (3) Procedure memory ROM/EPROM (4KB/8KB ), is used to preserve theprocedure , some initial data and form in slice. But does not take ROM/EPROM within some one-chip computers, such as 8031, 8032.(4) Four 8 run side by side I/O interface P0 four P3, each mouth can use as introduction , may use as exporting too. (5) Two timer / counter, each timer / counter may set up and count in the way, used to count to the external incident, can set up into a timing way too, and can according to count or result of timing realize the control of the computer. (6) Five cut off cutting off the control system of the source. (7) One all duplex serial I/O mouth of UART (universal asynchronous receiver/transmitter (UART) ), is it realize one-chip computer or one-chip computer and serial communication of computer to use for. (8) Stretch oscillator and clock produce circuit, quartz crystal finely tune electric capacity need outer. Allow oscillation frequency as 12 megahertz now at most. Every the above-mentioned part was joined through the inside data bus .Among them, CPU is a core of the one-chip computer, it is the control of the computer and command centre, made up of such parts as arithmetic unit and controller , etc.. The arithmetic unit can carry on 8 persons of arithmetic operation and unit ALU of logic operation while including one, the 1 storing device temporaries of 8, storing device 2 temporarily, 8's accumulation device ACC, register B and procedure state register PSW, etc. Person who accumulate ACC count by 2 input ends entered of checking etc. temporarily as one operation often, come from person who store 1 operation is it is it make operation to go on to count temporarily , operation result and loop back ACC with another one. Inaddition, ACC is often regarded as the transfer station of data transmission on 8051 inside. The same as general microprocessor, it is the busiest register. Help remembering that agreeing with a express in the order. The controller includes the procedure counter, the order is deposited, the order deciphering, the oscillator and timing circuit, etc. The procedure counter is made up of counter of 8 for two, amounts to 16. It is a byte address counter of the procedure in fact, the content is the next IA that will carried out in PC. The content which changes it can change the direction that the procedure carries out. Shake the circuit in 8051 one-chip computers, only need outer quartz crystal and frequency to finely tune the electric capacity, its frequency range is its 12MHZ of 1.2MHZ. This pulse signal, as 8051 basic beats of working, namely the minimum unit of time. 8051 is the same as other computers, the work in harmony under the control of the basic beat, just like an orchestra according to the beat play that is commanded.There are ROM (procedure memory , can only read ) and RAM in 8051 slices (data memory, can is it can write ) two to read, they have each independent memory address space, dispose way to be the same with general memory of computer. Procedure 8051 memory and 8751 slice procedure memory capacity 4KB, address begin from 0000H, used for preserving the procedure and form constant. Data 8051- 8751 8031 of memory data memory 128B, address false 00FH, using for middle result to deposit operation, the data are stored temporarily and the data are buffered. In RAM of this 128B, there is unit of 32 bytes that can be appointed as the jobregister, this and general microprocessor is different, 8051 slice RAM and job register rank one formation the same to arrange the location. It is not very the same that the memory of MCS-51 series one-chip computer and general computer disposes the way in addition. General computer for first address space, ROM and RAM can arrange in different space within the range of this address at will, namely the addresses of ROM and RAM, with distributing different address space in a formation. While visiting the memory, corresponding and only an address Memory unit, can ROM, it can be RAM too, and by visiting the order similarly. This kind of memory structure is called the structure of Princeton. 8051 memories are divided into procedure memory space and data memory space on the physics structure, there are four memory spaces in all: The procedure stores in one and data memory space outside data memory and one in procedure memory space and one outside one, the structure forms of this kind of procedure device and data memory separated form data memory, called Harvard structure. But use the angle from users, 8051 memory address space is divided into three kinds: (1) In the slice, arrange blocks of FFFFH, 0000H of location, in unison outside the slice (use 16 addresses). (2) The data memory address space outside one of 64KB, the address is arranged from 0000H 64KB FFFFH (with 16 addresses) too to the location. (3) Data memory address space of 256B (use 8 addresses). Three above-mentioned memory space addresses overlap, for distinguishing and designing the order symbol of different data transmission in the instruction system of 8051: CPU visit slice, ROM orderspend MOVC , visit block RAM order uses MOVX outside the slice, RAM order uses MOV to visit in slice.8051 one-chip computer have four 8 walk abreast I/O ports, call P0, P1, P2 and P3. Each port is 8 accurate two-way mouths, accounts for 32 pins altogether. Every one I/O line can be used as introduction and exported independently. Each port includes a latch (namely special function register), one exports the driver and a introduction buffer. Make data can latch when outputting, data can buffer when making introduction, but four function of pass away these self-same. Expand among the system of memory outside having slice, four ports these may serve as accurate two-way mouth of I/O in common use. Expand among the system of memory outside having slice, P2 mouth see high 8 address off; P0 mouth is a two-way bus, send the introduction of 8 low addresses and data / export in timesharing The circuit of 8051 one-chip computers and four I/O ports is very ingenious in design. Familiar with I/O port logical circuit, not only help to use port correctly and rationally, and will inspire to designing the peripheral logical circuit of one-chip computer to some extent. Load ability and interface of port have certain requirement, because output grade, P0 of mouth and P1 end output, P3 of mouth grade different at structure, so, the load ability and interface of its door demand to have nothing in common with each other. P0 mouth is different from other mouth, its output grade draws the resistance supremely. When using it as the mouth in common use, output grade is it leak circuit to turn on, is it urge NMOS draw the resistanceon taking to be outer with it while inputting to go out to fail. When being used as introduction, should write"1" to a latch first. Every one with P0 mouth can drive 8 Model LS TTL load to export. P1 mouth is an accurate two-way mouth too, used as I/O in common use. Different from P0 mouth output of circuit its, draw load resistance link with power on inside have. In fact, the resistance is that two effects are in charge of FET and together: One FET is in charge of load, its resistance is regular. Another one can is it lead to work with close at two state, make its President resistance value change approximate 0 or group value heavy two situation very. When it is 0 that the resistance is approximate, can draw the pin to the high level fast; when resistance value is very large, P1 mouth high electricity at ordinary times, can is it draw electric current load to offer outwards, draw electric current load to offer outwards, draw the resistance on needn't answer and thinking. Here when the port is used as introduction, must write into 1 to the corresponding latch first too, make FET end relatively about 20,000 ohms because of load resistance in scene and because 40,000 ohms, will not exert an influence on the data that are input. The structure of P2 some mouth is similar to P0 mouth, there are MUX switches. Is it similar to mouth partly to urge, but mouth large a conversion controls some than P1.P3 mouth one multi-functional port, mouth getting many than P1 it have "3 doors and 4 buffers". Two parts there, make her besides accurate two-way function with P1 mouth just, can also use the second function of every pin, "and" door 3 functions one switch in fact, it determines to be to output data of latch tooutput second signal of function. Act as W=At 1 o'clock, output Q end signal; act as Q=At 1 o'clock, can output W line signal. At the time of programming, it is that the first function is still the second function but needn't have software that set up P3 mouth in advance .It hardware not inside is the automatic to have two function outputted when CPU carries on SFR and seeks the location to visit to P3 mouth/at not lasting lining, there are inside hardware latch Qs=1. The operation principle of P3 mouth is similar to P1 mouth.Output grade, P3 of mouth, P1 of P1, connect with inside have load resistance of drawing, every one of they can drive 4 Model LS TTL load to output. As while inputting the mouth, any TTL or NMOS circuit can drive P1 of 8051 one-chip computers as P3 mouth in a normal way. Because draw resistance on output grade of them have, can open a way collector too or drain-source resistance is it urge to open a way, do not need to have the resistance of drawing outer. Mouths are all accurate two-way mouths too. When the conduct is input, must write the corresponding port latch with 1 first. As to 80C51 one-chip computer, port can only offer milliampere of output electric currents, is it output mouth go when urging one ordinary basing of transistor to regard as, should contact a resistance among the port and transistor base, in order to the electricity while restraining the high level from exporting P1~P3 Being restored to the throne is the operation of initializing of an one-chip computer. Its main function is to turn PC into 0000H initially, make the one-chip computer begin to hold the conductprocedure from unit 0000H. Except that the ones that enter the system are initialized normally, as because procedure operate it make mistakes or operate there aren't mistake, in order to extricate oneself from a predicament , need to be pressed and restored to the throne the key restarting too. It is an input end which is restored to the throne the signal in 8051 China RST pin. Restore to the throne signal high level effective, should sustain 24 shake cycle (namely 2 machine cycles) the above its effective times. If 6 of frequency of utilization brilliant to shake, restore to the throne signal duration should exceed 4 delicate to finish restoring to the throne and operating. Produce the logic picture of circuit which is restored to the throne the signal: restore to the throne the circuit and include two parts outside in the chip entirely. Outside that circuit produce to restore to the throne signal (RST) hand over to Schmitt's trigger, restore to the throne circuit sample to output , Schmitt of trigger constantly in each S5P2 , machine of cycle in having one more , then just got and restored to the throne and operated the necessary signal inside. Restore to the throne resistance of circuit generally, electric capacity parameter suitable for 6 brilliant to shake, can is it restore to the throne signal high level duration greater than 2 machine cycles to guarantee. Being restored to the throne in the circuit is simple, its function is very important. Pieces of one-chip computer system could normal running, should first check it can restore to the throne not succeeding. Checking and can pop one's head and monitor the pin with the oscilloscope tentatively, push and is restored to the throne the key, the wave form that observes andhas enough range is exported (instantaneous), can also through is it restore to the throne circuit group holding value carry on the experiment to change.MCS-51系列单片机的功能和结构MSC-51系列单片机具有一个单芯片电脑的结构和功能，它是英特尔公司的系列产品的名称。
单片机设计外文文献翻译(含中英文)
附录A 外文翻译——AT89S52/AT89S51技术手册AT89S52译文主要性能与MCS-51单片机产品兼容8K字节在系统可编程Flash存储器1000次擦写周期全静态操作：0Hz～33Hz三级加密程序存储器32个可编程I/O口线三个16位定时器/计数器八个中断源全双工UART串行通道低功耗空闲和掉电模式掉电后中断可唤醒看门狗定时器双数据指针掉电标识符功能特性描述AT89S52是一种低功耗、高性能CMOS8位微控制器，具有8K在系统可编程Flash 存储器。
使用Atmel公司高密度非易失性存储器技术制造，与工业80C51产品指令和引脚完全兼容。
片上Flash 允许程序存储器在系统可编程，亦适于常规编程器。
在单芯片上，拥有灵巧的8位CPU和在系统可编程Flash，使得AT89S52为众多嵌入式控制应用系统提供高灵活、超有效的解决方案。
AT89S52具有以下标准功能：8k字节Flash，256字节RAM，32位I/O口线，看门狗定时器，2个数据指针，三个16位定时器/计数器，一个6向量2级中断结构，全双工串行口，片内晶振及时钟电路。
另外，AT89S52可降至0Hz静态逻辑操作，支持2种软件可选择节电模式。
空闲模式下，CPU停止工作，允许RAM、定时器/计数器、串口、中断继续工作。
掉电保护方式下，RAM内容被保存，振荡器被冻结，单片机一切工作停止，直到下一个中断或硬件复位为止。
引脚结构方框图VCC : 电源GND :地P0口：P0口是一个8位漏极开路的双向I/O口。
作为输出口，每位能驱动8个TTL逻辑电平。
对P0端口写“1”时，引脚用作高阻抗输入。
当访问外部程序和数据存储器时，P0口也被作为低8位地址/数据复用。
在这种模式下，P0具有内部上拉电阻。
在flash编程时，P0口也用来接收指令字节；在程序校验时，输出指令字节。
程序校验时，需要外部上拉电阻。
P1口：P1 口是一个具有内部上拉电阻的8位双向I/O 口，p1 输出缓冲器能驱动4个TTL 逻辑电平。
单片机的外文文献及中文翻译
SCM is an integrated circuit chip，is the use of large scale integrated circuit technology to a data processing capability of CPU CPU random access memory RAM，read—only memory ROM，a variety of I / O port and interrupt system, timers / timer functions (which may also include display driver circuitry，pulse width modulation circuit，analog multiplexer, A / D converter circuit) integrated into a silicon constitute a small and complete computer systems。
SCM is also known as micro—controller （Microcontroller)，because it is the first to be used in industrial control. Only a single chip by the CPU chip developed from a dedicated processor。
The first design is by a large number of peripherals and CPU on a chip in the computer system，smaller, more easily integrated into a complex and demanding on the volume control device which. The Z80 INTEL is the first designed in accordance with this idea processor, then on the development of microcontroller and dedicated processors will be parting ways。
单片机论文外文文献和中文翻译(有出处)
微机发展简史IEEE的论文剑桥大学，2004/2/5莫里斯威尔克斯计算机实验室剑桥大学第一台存储程序的计算开始出现于1950前后，它就是1949年夏天在剑桥大学，我们创造的延迟存储自动电子计算机（EDSAC）。
最初实验用的计算机是由象我一样有着广博知识的人构造的。
我们在电子工程方面都有着丰富的经验，并且我们深信这些经验对我们大有裨益。
后来，被证明是正确的，尽管我们也要学习很多新东西。
最重要的是瞬态一定要小心应付，虽然它只会在电视机的荧幕上一起一个无害的闪光，但是在计算机上这将导致一系列的错误。
在电路的设计过程中，我们经常陷入两难的境地。
举例来说，我可以使用真空二级管做为门电路，就象在EDSAC中一样，或者在两个栅格之间用带控制信号的五级管，这被广泛用于其他系统设计，这类的选择一直在持续着直到逻辑门电路开始应用。
在计算机领域工作的人都应该记得TTL，ECL和CMOS，到目前为止，CMOS已经占据了主导地位。
在最初的几年，IEE（电子工程师协会）仍然由动力工程占据主导地位。
为了让IEE 认识到无线工程和快速发展的电子工程并行发展是它自己的一项权利，我们不得不面对一些障碍。
由于动力工程师们做事的方式与我们不同，我们也遇到了许多困难。
让人有些愤怒的是，所有的IEE出版的论文都被期望以冗长的早期研究的陈述开头，无非是些在早期阶段由于没有太多经验而遇到的困难之类的陈述。
60年代的巩固阶段60年代初，个人英雄时代结束了，计算机真正引起了重视。
世界上的计算机数量已经增加了许多，并且性能比以前更加可靠。
这些我认为归因与高级语言的起步和第一个操作系统的诞生。
分时系统开始起步，并且计算机图形学随之而来。
综上所述，晶体管开始代替正空管。
这个变化对当时的工程师们是个不可回避的挑战。
他们必须忘记他们熟悉的电路重新开始。
只能说他们鼓起勇气接受了挑战，尽管这个转变并不会一帆风顺。
小规模集成电路和小型机很快，在一个硅片上可以放不止一个晶体管，由此集成电路诞生了。
单片机英文参考文献(精选120个)
我国的单片机起步虽然较晚，但经过几十年的发展，也取得了巨大的成就。
不论是工业生产还是社会生活的各个方面都离不开单片机的使用。
下面是搜素整理的单片机英文参考文献的分享，以供参考。
单片机英文参考文献一： [1]Hui Wang. Optimal Design of Single Chip Microcomputer Multi-machine Serial Communication based on Signal VerificationTechnology[J]. International Journal of Intelligent Information and Management Science,2020,9（1）。
[2]Philip J. Basford,Steven J. Johnston,Colin S. Perkins,Tony Garnock-Jones,Fung Po Tso,Dimitrios Pezaros,Robert D. Mullins,Eiko Yoneki,Jeremy Singer,Simon J. Cox. Performance analysis of single board computer clusters[J]. Future Generation ComputerSystems,2020,102. [3]. Computers; Reports from University of Southampton Describe Recent Advances in Computers （Performance Analysis of Single Board Computer Clusters）[J]. Computers, Networks & Communications,2020. [4]Yunyu Cao,Jinjin Dang,Chenxu Cao. Design of Automobile Digital Tire Pressure Detector[J]. Journal of Scientific Research and Reports,2019. [5]Sudad J. Ashaj,Ergun Er?elebi. Reduce Cost Smart Power Management System by Utilize Single Board Computer Artificial Neural Networks for Smart Systems[J]. International Journal of Computational Intelligence Systems,2019. [6]Hanhong Tan*, Yanfei Teng. Design of PWM Lighting brightness Control based on LAN QIAO Cup single Chip Microcomputer[J]. International Journal of Computational and Engineering,2019,4（3）。
单片机STM32外文文献翻译、中英文翻译
外文译英文原文：STM32 MicrocontrollerIntroductionRequirements based STM32 family is designed for high-performance, low-cost, low-power embedded applications designed specifically for ARM Cortex-M3 core. According to the performance into two different series: STM32F103 "Enhanced〞 series and STM32F101 "Basic" series. Enhanced Series clock frequency of 72MHz, the highest performance of similar products product; basic clock frequency of 36MHz, 16-bit product prices get more than 16 products significantly enhance the performance and is 16 product users the best choice. Both series have built-in 32K to 128K of flash memory, the difference is the maximum capacity of the SRAM and peripheral combinations. At 72MHz, executing from Flash, STM32 power consumption 36mA, are 32 products on the market s lowest power, the equivalent of 0.5niA/MHz.STM32F103 Performance Characteristics1)Kernel. ARM32 bit CPU, the maximum operating frequency of 72MHz,1.25DMIPS/MHz. Single-cycle multiply and hardware divide.2)Memory. Integrated on-chip 32-512KB of Flash memory. 6-64KB SRAM memory.3)Clock, reset, and power management. 2.0-3.6V power supply and I/O interface, the drive voltage. POR, PDR and programmable voltage detector. 4-16MHz crystal. Embedded factory tuned 8MHz RC oscillator circuit. 40 kHz internal RC oscillator circuit. CPU clock for the PLL. With calibration for the RTC 32kHz crystal.4)Low power consumption. Three kinds of low-power mode. Sleep, stop, standby mode. For RTC and backup registers supply VBAT.5)Debug mode. Serial debugging and JTAG interface.6)Direct data storage. 12-channel direct data storage controller. Supported peripherals: timers, ADC, DAC, SPI, IIC and USART.7)Up to a maximum of 112 fast I / O ports. Depending on the modeL there are 26,37,51,80, and 112 I/O ports, all ports can be mapped to 16 external interrupt vectors. In addition to the analog input, all of them can accept the input of 5V or less.8)Up to a maximum of 11 timers. Four 16-bit timers, each with 4 IC / OC / PWM orpulse counter. 2 16 6-channel advanced control timer: up to 6 channels can be used for PWM output. 2 watchdog timer. Systick tinier: 24 down counter. Two 16-bit basic timer for driving DAC.9)Up to a maximum of 13 communication interfaces. 2 IIC interface. 5 USART interfaces. 3 SPI interface, two and IIS reuse. CAN interface. USB 2.0 full-speed interface. SDIO interface.System Function1)Integration of embedded Flash and SRAM memory ARM Cortex-M3 core. And 8/16 equipment compared, ARM Cortex-M3 32-bit RISC processor provides a higher code efficiency. STM32F103xx microcontrollers with an embedded ARM core, so it can be compatible with all ARM tools and software.2)Embedded Flash memory and RAM memory. Built up to 512KB embedded Flash, can be used to store programs and data. Up to 64KB of embedded SRAM clock speed of the CPU can read and write.3)Variable static memory. Variable static memory with 4 chip selects, supports four modes: Flash, RAM, PSRAM, NOR and NAND. After three FSMC interrupt lines connected to the OR after the nested vector interrupt controller. No read / write FIFO, except PCCARD, the code is executed from external memory is not supported Boot, the target frequency is equal to SYSCLK / 2, so the time when the system clock is 72MHz, 36MHz conducted in accordance with external access.4)Nested Vectored Internipt Controller. Can handle 43 maskable interrupt channels, providing 16 interrupt priority levels. Tightly coupled nested vectored intenupt controller to achieve lower latency interrupt handling directly passed to the kernel interrupt vector table entry address, tightly coupled nested vectored interrupt controller kernel interface, allowing early treatment interruption, the latter to be more high-priority interrupt processing, support tail chain, auto-save processor state terrupts automatically restored on interrupt exit, no instructions intervention.5)External internipt / event controller. External interrupt / event controller consists for 19 to generate interrupt / event requests edge detector lines. Each line can be individually configured to select the trigger event, it can be individually masked. There is a pending interrupt request registers to maintain state. When an external line appear longer than the internal APB2 clock-cycle pulse, the external interrupt / event controller is able to detect. Up to 112 GPIO connected to the 16 external internipt lines.6)Clocks and startup. At boot time or to the system clock selection, but the reset whenthe internal 8MHz crystal oscillator is selected as the CPU clock. Can choose a 4-16MHz external clock, and will be monitored to determine the success. During this time, the interrupt controller is disabled and the software management is subsequently disabled. Also, if there is a need, PLL clock internipt management fully available. Comparator can be used more pre-configuration of the AHB frequency, including high-speed and low-speed APB APB, APB highest frequency of high-speed 72MHz, low-speed APB highest frequency of 36MHz.Architectural AdvantagesIn addition to the new features Enhanced peripheral interfaces, STM32 series also interconnect with other STM32 microcontrollers offer the same standard interface, such sharing of peripherals to enhance the entire product family, application flexibility, so that developers can a plurality of design reuse the same software. New STM32 standard peripherals include 10 timers, two 12-bit ADC, two 12-bit DAC, two I2C interfaces, five USART interfaces and three SPI ports. There are 12 new products peripherals direct data storage channel, there is a CRC calculation unit, like other STM32 microcontrollers, the supports 96 unique identifier.New series also has followed the STM32 microcontroller family of products low voltage and energy saving are two advantages. 2.0V to 3.6V operating voltage range compatible with the mainstream of battery technologies such as lithium batteries and nickel-metal hydride batteries, the package also features a battery operation mode dedicated pin Vbat. 72MHz frequency to execute code from flash consumes only 27mA current. There are four low-power mode, the current consumption can be reduced to two microamps. Quick Start from low power mode to save energy too; starting circuit using STM32 internally generated 8MHz signal, the microcontroller from stop mode when you wake up with less than 6 microseconds.中文译:单片机STM321STM32的介绍STM32系列基于专为要求高性能、低本钱、低功耗的嵌入式应用专门设计的ARMCortex-M3内核.按性能分成两个不同的系列：STM32F103 “增强型〞系列和STM32F101 “根本型〞系列.增强型系列时钟频率到达72MHz,是同类产品中性能最高的产品；根本型时钟频率为36MHz,以16位产品的价格得到比16位产品大幅提升的性能,是16位产品用户的最正确选择.两个系列都内置32K 到128K 的闪存,不同的是SRAM的最大容量和外设接口的组合.时钟频率72MHz时,从闪存执行代码,STM32功耗36mA,是32位市场上功耗最低的产品,相当于0.5mA/MHz.2STM32F103性能特点1〕内核.ARM32位CPU,最高工作频率72MHz, 1.25DMIPS/MHzo单周期乘法和硬件除法.2〕存储器.片上集成32-512KB的Flash存储器.6-64KB的SRAM存储器.3〕时钟、复位和电源治理.2.0-3.6V的电源供电和I/O接口的驱动电压. POR、PDR和可编程的电压探测器.4-16MHZ的晶振.内嵌出厂前调校的8MHz RC振荡电路.内部40 kHz的RC振荡电路.用于CPU时钟的PLL.带校准用于RTC的32kHz的晶振.4〕低功耗.3种低功耗模式：休眠,停止,待机模式.为RTC和备份存放器供电的VBAT.5〕调试模式.串行调试和JTAG接口.6〕直接数据存储.12通道直接数据存储限制器.支持的外设：定时器,ADC, DAC, SPI, IIC 和USART.7〕最多高达112个的快速I/O端口.根据型号的不同,有26, 37, 51, 80, 和112的I/O端口,所有的端口都可以映射到16个外部中断向量.除了模拟输入,所有的都可以接受5V以内的输入.8〕最多多达11个定时器.4个16位定时器,每个定时器有4个IC/OC/PWM 或者脉冲计数器.2个16位的6通道高级限制定时器:最多6个通道可用于PWM 输出.2个看门狗定时器.Systick定时器：24位倒计数器.2个16位根本定时器用于驱动DACo9〕最多多达13个通信接口.2个HC接口.5个USART接口.3个SPI接口,两个和IIS复用.CAN接口.USB 2.0全速接口.SDIO接口.3系统作用1〕集成嵌入式Hash和SRAM存储器的ARM Cortex-M3内核.和8/16位设备相比,ARM Cortex-M3 32位RISC处理器提供了更高的代码效率. STM32F103xx微限制器带有一个嵌入式的ARM核,所以可以兼容所有的ARM 工具和软件.2〕嵌入式Flash存储器和RAM存储器.内置多达512KB的嵌入式Flash, 可用于存储程序和数据.多达64KB的嵌入式SRAM可以以CPU的时钟速度进行读写.3〕可变静态存储器.可变静态存储器带有4个片选,支持四种模式：Flash, RAM, PSRAM, NOR和NANDo 3个FSMC中断线经过OR后连接到嵌套矢量中断限制器.没有读/写FIFO,除PCCARD之外,代码都是从外部存储器执行, 不支持Boot,目标频率等于SYSCLK/2,所以当系统时钟是72MHz时' 外部访问根据36MHz进行.4〕嵌套矢量中断限制器.可以处理43个可屏蔽中断通道,提供16个中断优先级.紧密耦合的嵌套矢量中断限制器实现了更低的中断处理延迟,直接向内核传递中断入口向量表地址,紧密耦合的嵌套矢量中断限制器内核接口,允许中断提前处理,对后到的更高优先级的中断进行处理,支持尾链,自动保存处理器状态,中断入口在中断退出时自动恢复,不需要指令干预.5〕外部中断/事件限制器.外部中断/事件限制器由用于19条产生中断/事件请求的边沿探测器线组成.每条线可以被单独配置用于选择触发事件,也可以被单独屏蔽.有一个挂起存放器来维护中断请求的状态.当外部线上出现长度超过内部APB2时钟周期的脉冲时,外部中断/事件限制器能够探测到.多达112个GPIO连接到16个外部中断线.6〕时钟和启动.在启动的时候还是要进行系统时钟选择,但复位的时候内部8MHz的晶振被选用作CPU时钟.可以选择一个外部的4-16MHZ的时钟,并且会被监视来判定是否成功.在这期间,限制器被禁止并且软件中断治理也随后被禁止.同时,如果有需要,PLL时钟的中断治理完全可用.多个预比拟器可以用于配置AHB频率,包括高速APB和低速APB,高速APB最高的频率为72MHz, 低速APB最高的频率为36MHzo4架构优势除新增的功能强化型外设接口外,STM32互连系列还提供与其它STM32微限制器相同的标准接口,这种外设共用性提升了整个产品家族的应用灵活性,使开发人员可以在多个设计中重复使用同一个软件.新STM32的标准外设包括10 个定时器、两个12位模数转换器、两个12位数模转换器、两个12c接口、五个USART接口和三个SPI端口.新产品外设共有12条直接数据存储通道,还有一个CRC计算单元,像其它STM32微限制器一样,支持96位唯一标识码.新系列微限制器还沿续了STM32产品家族的低电压和节能两大优点.2.0V 到3.6V的工作电压范围兼容主流的电池技术,如锂电池和银氢电池,封装还设有一个电池工作模式专用引脚Vbato以72MHz频率从闪存执行代码,仅消耗27mA 电流.低功耗模式共有四种,可将电流消耗降至两微安.从低功耗模式快速启动也同样节省电能；启动电路使用STM32内部生成的8MHz信号,将微控制器从停止模式唤醒用时小于6微秒.。
单片机STM32外文文献翻译、中英文翻译
外文翻译英文原文：STM32 MicrocontrollerIntroductionRequirements based STM32 family is designed for high-performance, low-cost, low-power embedded applications designed specifically for ARM Cortex-M3 core. According to the performance into two different series: STM32F103 "Enhanced" series and STM32F101 "Basic" series. Enhanced Series clock frequency of 72MHz, the highest performance of similar products product; basic clock frequency of 36MHz, 16-bit product prices get more than 16 products significantly enhance the performance and is 16 product users the best choice. Both series have built-in 32K to 128K of flash memory, the difference is the maximum capacity of the SRAM and peripheral combinations. At 72MHz, executing from Flash, STM32 power consumption 36mA, are 32 products on the market's lowest power, the equivalent of 0.5mA/MHz.STM32F103 Performance Characteristics1)Kernel. ARM32 bit CPU, the maximum operating frequency of 72MHz,1.25DMIPS/MHz. Single-cycle multiply and hardware divide.2)Memory. Integrated on-chip 32-512KB of Flash memory. 6-64KB SRAM memory.3)Clock, reset, and power management. 2.0-3.6V power supply and I / O interface, the drive voltage. POR, PDR and programmable voltage detector. 4-16MHz crystal. Embedded factory tuned 8MHz RC oscillator circuit. 40 kHz internal RC oscillator circuit. CPU clock for the PLL. With calibration for the RTC 32kHz crystal.4)Low power consumption. Three kinds of low-power mode. Sleep, stop, standby mode. For RTC and backup registers supply VBAT.5)Debug mode. Serial debugging and JTAG interface.6)Direct data storage. 12-channel direct data storage controller. Supported peripherals: timers, ADC, DAC, SPI, IIC and USART.7)Up to a maximum of 112 fast I / O ports. Depending on the model, there are 26,37,51,80, and 112 I / O ports, all ports can be mapped to 16 external interruptvectors. In addition to the analog input, all of them can accept the input of 5V or less.8)Up to a maximum of 11 timers. Four 16-bit timers, each with 4 IC / OC / PWM or pulse counter. 2 16 6-channel advanced control timer: up to 6 channels can be used for PWM output. 2 watchdog timer. Systick timer: 24 down counter. Two 16-bit basic timer for driving DAC.9)Up to a maximum of 13 communication interfaces. 2 IIC interface. 5 USART interfaces. 3 SPI interface, two and IIS reuse. CAN interface. USB 2.0 full-speed interface. SDIO interface.System Function1)Integration of embedded Flash and SRAM memory ARM Cortex-M3 core. And 8/16 equipment compared, ARM Cortex-M3 32-bit RISC processor provides a higher code efficiency. STM32F103xx microcontrollers with an embedded ARM core, so it can be compatible with all ARM tools and software.2)Embedded Flash memory and RAM memory. Built up to 512KB embedded Flash, can be used to store programs and data. Up to 64KB of embedded SRAM clock speed of the CPU can read and write.3)Variable static memory. Variable static memory with 4 chip selects, supports four modes: Flash, RAM, PSRAM, NOR and NAND. After three FSMC interrupt lines connected to the OR after the nested vector interrupt controller. No read / write FIFO, except PCCARD, the code is executed from external memory is not supported Boot, the target frequency is equal to SYSCLK / 2, so the time when the system clock is 72MHz, 36MHz conducted in accordance with external access.4)Nested Vectored Interrupt Controller. Can handle 43 maskable interrupt channels, providing 16 interrupt priority levels. Tightly coupled nested vectored interrupt controller to achieve lower latency interrupt handling directly passed to the kernel interrupt vector table entry address, tightly coupled nested vectored interrupt controller kernel interface, allowing early treatment interruption, the latter to be more high-priority interrupt processing, support tail chain, auto-save processor state terrupts automatically restored on interrupt exit, no instructions intervention.5)External interrupt / event controller. External interrupt / event controller consists for 19 to generate interrupt / event requests edge detector lines. Each line can be individually configured to select the trigger event, it can be individually masked. There is a pending interrupt request registers to maintain state. When an external line appear longer than the internal APB2 clock-cycle pulse, the external interrupt / eventcontroller is able to detect. Up to 112 GPIO connected to the 16 external interrupt lines.6)Clocks and startup. At boot time or to the system clock selection, but the reset when the internal 8MHz crystal oscillator is selected as the CPU clock. Can choose a 4-16MHz external clock, and will be monitored to determine the success. During this time, the interrupt controller is disabled and the software management is subsequently disabled. Also, if there is a need, PLL clock interrupt management fully available. Comparator can be used more pre-configuration of the AHB frequency, including high-speed and low-speed APB APB, APB highest frequency of high-speed 72MHz, low-speed APB highest frequency of 36MHz.Architectural AdvantagesIn addition to the new features Enhanced peripheral interfaces, STM32 series also interconnect with other STM32 microcontrollers offer the same standard interface, such sharing of peripherals to enhance the entire product family, application flexibility, so that developers can a plurality of design reuse the same software. New STM32 standard peripherals include 10 timers, two 12-bit ADC, two 12-bit DAC, two I2C interfaces, five USART interfaces and three SPI ports. There are 12 new products peripherals direct data storage channel, there is a CRC calculation unit, like other STM32 microcontrollers, the supports 96 unique identifier.New series also has followed the STM32 microcontroller family of products low voltage and energy saving are two advantages. 2.0V to 3.6V operating voltage range compatible with the mainstream of battery technologies such as lithium batteries and nickel-metal hydride batteries, the package also features a battery operation mode dedicated pin Vbat. 72MHz frequency to execute code from flash consumes only 27mA current. There are four low-power mode, the current consumption can be reduced to two microamps. Quick Start from low power mode to save energy too; starting circuit using STM32 internally generated 8MHz signal, the microcontroller from stop mode when you wake up with less than 6 microseconds.中文翻译：单片机STM321 STM32的介绍STM32系列基于专为要求高性能、低成本、低功耗的嵌入式应用专门设计的ARM Cortex-M3内核。
单片机英文文献外文翻译
单片机英文文献Principle of MCUSingle-chip is an integrated on a single chip a complete computer system. Even though most of his features in a small chip, but it has a need to complete the majority of computer components: CPU, memory, internal and external bus system, most will have the Core. At the same time, such as integrated communication interfaces, timers, real-time clock and other peripheral equipment. And now the most powerful single-chip microcomputer system can even voice, image, networking, input and output complex system integration on a single chip.Also known as single-chip MCU (Microcontroller), because it was first used in the field of industrial control. Only by the single-chip CPU chip developed from the dedicated processor. The design concept is the first by a large number of peripherals and CPU in a single chip, the computer system so that smaller, more easily integrated into the complex and demanding on the volume control devices. INTEL the Z80 is one of the first design in accordance with the idea of the processor, From then on, the MCU and the development of a dedicated processor parted ways.Early single-chip 8-bit or all of the four. One of the most successful is INTEL's 8031, because the performance of a simple and reliable access to a lot of good praise. Since then in 8031 to develop a single-chip microcomputer system MCS51 series. Based on single-chip microcomputer system of the system is still widely used until now. As the field of industrial control requirements increase in the beginning of a 16-bit single-chip, but not ideal because the price has not been very widely used. After the 90's with the big consumer electronics product development, single-chip technology is a huge improvement. INTEL i960 Series with subsequent ARM in particular, a broad range of applications, quickly replaced by 32-bit single-chip 16-bit single-chip high-end status, and enter the mainstream market. Traditional 8-bit single-chip performance has been the rapid increase in processing power compared to the 80's to raise a few hundred times. At present, the high-end 32-bit single-chip frequency over 300MHz, the performance of the mid-90's close on the heels of a special processor, while the ordinary price of the model dropped to one U.S. dollars, the most high-end models, only 10 U.S. dollars. Contemporary single-chip microcomputer system is no longer only the bare-metal environment in the development and use of a large number of dedicated embedded operating system is widely used in the full range of single-chip microcomputer. In PDAs and cell phones as the core processing of high-end single-chip or even a dedicated direct access to Windows and Linux operating systems.More than a dedicated single-chip processor suitable for embedded systems, so it was up to the application. In fact the number of single-chip is the world's largest computer. Modern human life used in almost every piece of electronic and mechanical products will have a single-chip integration. Phone, telephone, calculator, home appliances, electronic toys, handheld computers and computer accessories such as a mouse in the Department are equipped with 1-2 single chip. And personal computers also have a large number of single-chip microcomputer in the workplace. Vehicles equipped with more than 40 Department of the general single-chip, complex industrial control systems and even single-chip may have hundreds of work at the same time! SCM is not only far exceeds the number of PC and other integrated computing, even more than the numberof human beings.Hardwave introductionThe 8051 family of micro controllers is based on an architecture which is highly optimized for embedded control systems. It is used in a wide variety of applications from military equipment to automobiles to the keyboard on your PC. Second only to the Motorola 68HC11 in eight bit processors sales, the 8051 family of microcontrollers is available in a wide array of variations from manufacturers such as Intel, Philips, and Siemens. These manufacturers have added numerous features and peripherals to the 8051 such as I2C interfaces, analog to digital converters, watchdog timers, and pulse width modulated outputs. Variations of the 8051 with clock speeds up to 40MHz and voltage requirements down to 1.5 volts are available. This wide range of parts based on one core makes the 8051 family an excellent choice as the base architecture for a company's entire line of products since it can perform many functions and developers will only have to learn this one platform.The basic architecture consists of the following features:·an eight bit ALU·32 descrete I/O pins (4 groups of 8) which can be individually accessed·two 16 bit timer/counters·full duplex UART· 6 interrupt sources with 2 priority levels·128 bytes of on board RAM·separate 64K byte address spaces for DA TA and CODE memoryOne 8051 processor cycle consists of twelve oscillator periods. Each of the twelve oscillator periods is used for a special function by the 8051 core such as op code fetches and samples of the interrupt daisy chain for pending interrupts. The time required for any 8051 instruction can be computed by dividing the clock frequency by 12, inverting that result and multiplying it by the number of processor cycles required by the instruction in question. Therefore, if you have a system which is using an 11.059MHz clock, you can compute the number of instructions per second by dividing this value by 12. This gives an instruction frequency of 921583 instructions per second. Inverting this will provide the amount of time taken by each instruction cycle (1.085 microseconds).单片机原理单片机是指一个集成在一块芯片上的完整计算机系统。
单片机英文文献及翻译)
Validation and Testing of Design Hardening for Single Event Effects Using the 8051 MicrocontrollerAbstractWith the dearth of dedicated radiation hardened foundries, new and novel techniques are being developed for hardening designs using non-dedicated foundry services. In this paper, we will discuss the implications of validating these methods for the single event effects (SEE) in the space environment. Topics include the types of tests that are required and the design coverage (i.e., design libraries: do they need validating for each application?). Finally, an 8051 microcontroller core from NASA Institute of Advanced Microelectronics (IAμE) CMOS Ultra Low Power Radiation Tolerant (CULPRiT) design is evaluated for SEE mitigative techniques against two commercial 8051 devices.Index TermsSingle Event Effects, Hardened-By-Design, microcontroller, radiation effects.I. INTRODUCTIONNASA constantly strives to provide the best capture of science while operating in a space radiation environment using a minimum of resources [1,2]. With a relatively limited selection of radiation-hardened microelectronic devices that are often two or more generations of performance behind commercialstate-ofthe-art technologies, NASA’s performance of this task is quite challenging. One method of alleviating this is by the use of commercial foundry alternatives with no or minimally invasive design techniques for hardening. This is often called hardened-by-design (HBD).Building custom-type HBD devices using design libraries and automated design tools may provide NASA the solution it needs to meet stringent science performance specifications in a timely,cost-effective, and reliable manner.However, one question still exists: traditional radiation-hardened devices have lot and/or wafer radiation qualification tests performed; what types of tests are required for HBD validation?II. TESTING HBD DEVICES CONSIDERATIONSTest methodologies in the United States exist to qualify individual devices through standards and organizations such as ASTM, JEDEC, and MIL-STD- 883. Typically, TID (Co-60) and SEE (heavy ion and/or proton) are required for device validation. So what is unique to HBD devices?As opposed to a “regular” commercial-off-the-shelf (COTS) device or application specific integrated circuit (ASIC) where no hardening has been performed, one needs to determine how validated is the design library as opposed to determining the device hardness. That is, by using test chips, can we “qualify” a future device using the same library?Consider if Vendor A has designed a new HBD library portable to foundries B and C. A test chip is designed, tested, and deemed acceptable. Nine months later a NASA flight project enters the mix by designing a new device using Vendor A’s library. Does this device require complete radiation qualification testing? To answer this, other questions must be asked.How complete was the test chip? Was there sufficient statistical coverage of all library elements to validate each cell? If the new NASA design uses a partially or insufficiently characterized portion of the design library, full testing might be required. Of course, if part of the HBD was relying on inherent radiation hardness of a process, some of the tests (like SEL in the earlier example) may be waived.Other considerations include speed of operation and operating voltage. For example, if the test chip was tested statically for SEE at a power supply voltage of 3.3V, is the data applicable to a 100 MHz operating frequency at 2.5V? Dynamic considerations (i.e., nonstatic operation) include the propagated effects of Single Event Transients (SETs). These can be a greater concern at higher frequencies.The point of the considerations is that the design library must be known, the coverage used during testing is known, the test application must be thoroughly understood and the characteristics of the foundry must be known. If all these are applicable or have been validated by the test chip, then no testing may be necessary. A task within NASA’s Electronic Parts and Packaging (NEPP) Program was performed to explore these types of considerations.III. HBD TECHNOLOGY EVALUATION USING THE 8051 MICROCONTROLLERWith their increasing capabilities and lower power consumption, microcontrollers are increasingly being used in NASA and DOD system designs. There are existing NASA and DoD programs that are doing technology development to provide HBD. Microcontrollers are one such vehicle that is being investigated to quantify the radiation hardness improvement. Examples of these programs are the 8051 microcontroller being developed by Mission Research Corporation (MRC) and the IAμE (the focus of this study). As these HBD technologies become available, validation of the technology, in the natural space radiation environment, for NASA’s use in spaceflight systems is required.The 8051 microcontroller is an industry standard architecture that has broad acceptance, wide-ranging applications and development tools available. There are numerous commercial vendors that supply this controller or have it integrated into some type of system-on-a-chip structure. Both MRC and IAμE chose this device to demonstrate two distinctly different technologies for hardening. The MRC example of this is to use temporal latches that require specific timing to ensure that single event effects are minimized. The IAμE technology uses ultra low power, and layout and architecture HBD design rules to achieve their results. These are fundamentally different than the approach by Aeroflex-United Technologies Microelectronics Center (UTMC), the commercial vendor of a radiation–hardened 8051, that built their 8051 microcontroller using radiationhardened processes. This broad range of technology within one device structure makes the 8051an ideal vehicle for performing this technology evaluation.The objective of this work is the technology evaluation of the CULPRiT process [3] from IAμE. The process has been baselined against two other processes, the standard 8051 commercial device from Intel and a version using state-of-the-art processing from Dallas Semiconductor. By performing this side-by-side comparison, the cost benefit, performance, and reliability trade study can be done.In the performance of the technology evaluation, this task developed hardware and software for testing microcontrollers. A thorough process was done to optimize the test process to obtain as complete an evaluation as possible. This included taking advantage of the available hardware and writing software that exercised the microcontroller such that all substructures of the processor were evaluated. This process is also leading to a more complete understanding of how to test complex structures, such as microcontrollers, and how to more efficiently test these structures in the future.IV. TEST DEVICESThree devices were used in this test evaluation. The first is the NASA CULPRiT device, which is the primary device to be evaluated. The other two devices are two versions of a commercial 8051, manufactured by Intel and Dallas Semiconductor, respectively.The Intel devices are the ROMless, CMOS version of the classic 8052 MCS-51 microcontroller. They are rated for operation at +5V, over a temperature range of 0 to 70 °C and at a clock speeds of 3.5 MHz to 24 MHz. They are manufactured in Intel’s P629.0 CHMOS III-E process.The Dallas Semiconductor devices are similar in that they are ROMless 8052 microcontrollers, but they are enhanced in various ways. They are rated for operation from 4.25 to 5.5 Volts over 0 to 70 °C at clock speeds up to 25 MHz. They have a second full serial port built in, seven additional interrupts, a watchdog timer, a power fail reset, dual data pointers and variable speed peripheral access. In addition, the core is redesigned so that the machine cycle is shortened for most instructions, resulting in an effective processing ability that is roughly 2.5 times greater (faster) than the standard 8052 device. None of these features, other than those inherent in the device operation, were utilized in order to maximize the similarity between the Dallas and Intel test codes.The CULPRiT technology device is a version of the MSC-51 family compatible C8051 HDL core licensed from the Ultra Low Power (ULP) process foundry. The CULPRiT technology C8051 device is designed to operate at a supply voltage of 500 mV and includes an on-chip input/output signal level-shifting interface with conventional higher voltage parts. The CULPRiT C8051 device requires two separate supply voltages; the 500 mV and the desired interface voltage. The CULPRiT C8051 is ROMless and is intended to be instruction set compatible with the MSC-51 family.V. TEST HARDWAREThe 8051 Device Under Test (DUT) was tested as a component of a functional computer. Aside from DUT itself, the other componentsof the DUT computer were removed from the immediate area of the irradiation beam.A small card (one per DUT package type) with a unique hard-wired identifier byte contained the DUT, its crystal, and bypass capacitors (and voltage level shifters for the CULPRiT DUTs). This "DUT Board" was connected to the "Main Board" by a short 60-conductor ribbon cable. The Main Board had all other components required to complete the DUT Computer, including some which nominally are not necessary in some designs (such as external RAM, external ROM and address latch). The DUT Computer and the Test Control Computer were connected via a serial cable and communications were established between the two by the Controller (that runs custom designed serial interface software). This Controller software allowed for commanding of the DUT, downloading DUT Code to the DUT, and real-time error collection from the DUT during and post irradiation. A 1 Hz signal source provided an external watchdog timing signal to the DUT, whose watchdog output was monitored via an oscilloscope. The power supply was monitored to provide indication of latchup.VI. TEST SOFTWAREThe 8051 test software concept is straightforward. It was designed to be a modular series of small test programs each exercising a specific part of the DUT. Since each test was stand alone, they were loaded independently of each other for execution on the DUT. This ensured that only the desired portion of the 8051 DUT was exercised during the test and helped pinpoint location of errors that occur during testing. All test programs resided on the controller PC until loaded via the serial interface to the DUT computer. In this way, individual tests could have been modified at any time without the necessity of burning PROMs. Additional tests could have also been developed and added without impacting the overall test design. The only permanent code, which was resident on the DUT, was the boot code and serial code loader routines that established communications between the controller PC and the DUT.All test programs implemented:• An external Universal Asynchronous Receive and Transmit device (UART) for transmission of error information and communication to controller computer.• An external real-time clock for data error tag.•A watchdog routine designed to provide visual verification of 8051 health and restart test code if necessary.• A "foul-up" routine to reset program counter if it wanders out of code space.• An external telemetry data storage memory to provide backup of data in the event of an interruption in data transmission.The brief description of each of the software tests used is given below. It should be noted that for each test, the returned telemetry (including time tag) was sent to both the test controller and the telemetry memory, giving the highest reliability that all data is captured.Interrupt –This test used 4 of 6 available interrupt vectors (Serial, External, Timer0 Overflow, and Timer1 Overflow) to trigger routines that sequentially modified a value in the accumulator which was periodically compared to a known value. Unexpected values were transmitted with register information.Logic –This test performed a series of logic and math computations and provided three types of error identifications: 1) addition/subtraction, 2) logic and 3) multiplication/division. All miscompares of computations and expected results were transmitted with other relevant register information.Memory – This test loaded internal data memory at locations D:0x20 through D:0xff (or D:0x20 through D:0x080 for the CULPRiT DUT), indirectly, with an 0x55 pattern. Compares were performed continuously and miscompares were corrected while error information and register values were transmitted.Program Counter -The program counter was used to continuously fetch constants at various offsets in the code. Constants were compared with known values and miscompares were transmitted along with relevant register information. Registers – This test loaded each of four (0,1,2,3) banks of general-purpose registers with either 0xAA (for banks 0 and 2) or 0x55 (for banks 1 and 3). The pattern was alternated in order to test the Program Status Word (PSW) special function register, which controls general-purpose register bank selection. General-purpose register banks were then compared with their expected values. All miscompares were corrected and error information was transmitted.Special Function Registers (SFR) – This test used learned static values of 12 out 21 available SFRs and then constantly compared the learned value with the current one. Miscompares were reloaded with learned value and error information was transmitted.Stack – This test performed arithmetic by pushing and popping operands on the stack. Unexpected results were attributed to errors on the stack or to the stack pointer itself and were transmitted with relevant register information.VII. TEST METHODOLOGYThe DUT Computer booted by executing the instruction code located at address 0x0000. Initially, the device at this location was an EPROM previously loaded with "Boot/Serial Loader" code. This code initialized the DUT Computer and interface through a serial connection to the controlling computer, the "Test Controller". The DUT Computer downloaded Test Code and put it into Program Code RAM (located on the Main Board of the DUT Computer). It then activated a circuit which simultaneously performed two functions: held the DUT reset line active for some time (~10 ms); and, remapped the Test Code residing in the Program Code RAM to locate it to address 0x0000 (the EPROM will no longer be accessible in the DUT Computer's memory space). Upon awaking from the reset, the DUT computer again booted by executing the instruction code at address 0x0000, except this time that code was not be the Boot/Serial Loader code but the Test Code.The Test Control Computer always retained the ability to force the reset/remap function, regardless of the DUT Computer's functionality. Thus, if the test ran without a Single Event Functional Interrupt (SEFI) either the DUT Computer itselfor the Test Controller could have terminated the test and allowed the post-test functions to be executed. If a SEFI occurred, the Test Controller forced a reboot into Boot/Serial Loader code and then executed the post-test functions. During any test of the DUT, the DUT exercised a portion of its functionality (e.g., Register operations or Internal RAM check, or Timer operations) at the highest utilization possible, while making a minimal periodic report to the Test Control Computer to convey that the DUT Computer was still functional. If this reportceased, the Test Controller knew that a SEFI had occurred. This periodic data was called "telemetry". If the DUT encountered an error that was not interrupting the functionality (e.g., a data register miscompare) it sent a more lengthy report through the serial port describing that error, and continued with the test.VIII.DISCUSSIONA. Single Event LatchupThe main argument for why latchup is not an issue for the CULPRiT devices is that the operating voltage of 0.5 volts should be below the holding voltage required for latchup to occur. In addition to this, the cell library used also incorporates the heavy dual guard-barring scheme [4]. This scheme has been demonstrated multiple times to be very effective in rendering CMOS circuits completely immune to SEL up to test limits of 120 MeV-cm2/mg. This is true in circuits operating at 5, 3.3, and 2.5 Volts, as well as the 0.5 Volt CULPRiT circuits. In one case, a 5 Volt circuit fabricated on noncircuits wafers even exhibited such SEL immunity.B. Single Event UpsetThe primary structure of the storage unit used in the CULPRiT devices is the Single Event Resistant Topology (SERT) [5]. Given the SERT cell topology and a single upset node assumption, it is expected that the SERT cell will be completely immune to SEUs occurring internal to the memory cell itself. Obviously there are other things going on. The CULPRiT 8051 results reported here are quite similar to some resultsobtained with a CULPRiT CCSDS lossless compression chip (USES) [6]. The CULPRiT USES was synthesized using exactly the same tools and library as the CULPRiT 8051.With the CULPRiT USES, the SEU cross section data [7] was taken as a function of frequency at two LET values, 37.6 and 58.5 MeV-cm2/mg. In both cases the data fit well to a linear model where cross section is proportional to clock. In the LET 37.6 case, the zero frequency intercept occurred essentially at the zero cross section point, indicating that virtually all of these SEUs are captured SETs from the combinational logic. The LET 58.5 data indicated that the SET (frequency dependent) component is sitting on top of a "dc-bias" component –presumably a second upset mechanism is occurring internal to the SERT cells only at a second, higher LET threshold.The SET mitigation scheme used in the CULPRiT devices is based on the SERT cell's fault tolerant input property when redundant input data is provided to separate storage nodes. The idea is that the redundant input data is provided through a total duplication of combinational logic (referred to as “dual rail design”) such that a simple SET on one rail cannot produce an upset. Therefore, some other upset mechanism must be happening. It is possible that a single particle strike is placing an SET on both halves of the logic streams, allowing an SET to produce an upset. Care was taken to separate the dual sensitive nodes in the SERT cell layouts but the automated place-and-route of the combinatorial logic paths may have placed dual sensitive nodes close enough.At this point, the theory for the CULPRiT SEU response is that at about an LET of 20, the energy deposition is sufficiently wide enough (and in the right locations) to produce an SET in both halves of the combinatorial logic streams. Increasing LET allows for more regions to be sensitive to this effect, yielding a larger cross section. Further, the second SEU mechanism that starts at an LET of about 40-60 has to do with when the charge collection disturbance cloud gets large enough to effectively upset multiples of the redundant storage nodes within the SERT cell itself. In this 0.35 μm library, the node separation is several microns. However, since it takes less charge to upset a node operating at 0.5 Volts, with transistors having effective thresholds around 70 mV, this is likely the effect being observed. Also the fact that the per-bit memory upset cross section for the CULPRiT devices and the commercial technologies are approximately equal, as shown in Figure 9, indicates that the cell itself has become sensitive to upset.IX. SUMMARYA detailed comparison of the SEE sensitivity of a HBD technology (CULPRiT) utilizing the 8051 microcontroller as a test vehicle has been completed. This paper discusses the test methodology used and presents a comparison of the commercial versus CULPRiT technologies based on the data taken. The CULPRiT devices consistently show significantly higher threshold LETs and an immunity to latchup. In all but the memory test at the highest LETs, the cross section curves for all upset events is one to two orders of magnitude lower than the commercial devices. Additionally, theory is presented, based on the CULPRiT technology, that explain these results.This paper also demonstrates the test methodology for quantifying the level of hardness designed into a HBD technology. By using the HBD technology in a real-world device structure (i.e., not just a test chip), and comparing results to equivalent commercial devices, one can have confidence in the level of hardness that would be available from that HBD technology in any circuit application.ACKNOWLEDGEMENTSThe authors of this paper would like to acknowledge the sponsors of this work. These are the NASA Electronic Parts and Packaging Program (NEPP), NASA Flight Programs, and the Defense Threat Reduction Agency (DTRA).。
(完整版)_毕业设计英文文献51单片机中英文文献翻译_
AT89C51的概况The General Situation of AT89C51Chapter 1 The application of AT89C51Microcontrollers are used in a multitude of commercial applications such as modems, motor-control systems, air conditioner control systems, automotive engine and among others. The domains also require that these microcontrollers are be ensured by a robust testing process and a proper tools environment for the validation of these microcontrollers both at the component and at the system level. Intel Plaform Engineering department developed anobject-oriented multi-threaded test environment for the validation of its AT89C51 automotive microcontrollers. The goals of thisenvironment was not only to provide a robust testing environment for the AT89C51 automotive microcontrollers, but to develop an environment which can be easily extended and reused for the validation of several other future microcontrollers. The environment was developed in conjunction with Microsoft Foundation Classes (AT89C51). The paper describes the design and mechanism of this test environment, its interactions with variousThe 8-bit AT89C51 CHMOS microcontrollers are designed to engine-control systems, airbags, suspension systems, and antilock braking systems (ABS). The AT89C51 is especially well suited to applications that benefit from its processing speed and enhancedon-chip peripheral functions set, such as automotive power-train control, vehicle dynamic suspension, antilock braking, and stability control applications. Because of these critical applications, the market requires a reliable cost-effective controller with a low interrupt latency response, ability to service the integrated peripherals needed in real time applications, and a CPU with above average processing power in a single package. The financial and legal risk of the market, particularly in mission criticalapplications such as an autopilot or anti-lock braking system, mistakes are financiallyprohibitive. Redesign costs can run as flaw. In addition, field replacements of components is extremely expensive, as the devices are typically sealed in modules with a total value several times that of the component. To mitigate these problems, it is essential that comprehensive testing of the controllers be carried out at both the component level and system level under worst case environmental and voltage conditions.This complete and thorough validation necessitates not only a well-defined process but also a proper environment and tools to facilitate and execute the mission successfully.Intel Chandler Platform Engineering group provides post silicon system validation (SV) of various micro-controllers and processors. The system validation process can be broken into three major parts.The type of the device and its application requirements determine which types of testing are performed on the device.1.2 The AT89C51 provides the following standard features:4Kbytes of Flash, 128 bytes of RAM, 32 IO lines, two 16-bittimercounters, a five vector two-level interrupt architecture,a full duple ser -ial port, on-chip oscillator and clock circuitry.In addition, the AT89C51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timercounters,serial port and interrupt sys -tem to continue functioning. The Power-down Mode saves the RAM contents but freezes the oscil –lator disabling all other chip functions until the next DescriptionVCC Supply voltage.GND Ground.Port 0：Port 0 is an 8-bit open-drain bi-directional IO port. As an output port, each pin cansink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as this mode P0 . External pullups are required during programverification.Port 1：Port 1 is an 8-bit bi-directional IO port with internal pullups.The Port 1 output buffers can sinkso -urce four TTL inputs.When 1s are written to Port 1 pins they are pulled be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pullups.Port 1 also receives the low-order address bytes during Flash programming and verification.Port 2：Port 2 is an 8-bit bi-directional IO port with internal pullups.The Port 2 outputbuffers can sinksource four TTL inputs.When 1s are written to Port 2 pins they arepulled be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pullups. Port 2 emits the this application, it uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register.Port 2 also receives the Flash programming and verification.Port 3：Port 3 is an 8-bit bi-directional IO port with internal pullups.The Port 3 outputbuffers can sinksou -rce four TTL inputs.When 1s are written to Port 3 pins they are pulled be used as inputs. As inputs,Port 3 pins that are externally being pulled low will source current (IIL) because of the pullups.Port 3 also serves the functions of various special featuresof the AT89C51 as listed below:RST：Reset input. A this pin for two machine cycles while the oscillator is running resets the device.ALEPROG：Address Latch Enable output pulse for latching the low byte of the address duringaccesses to external memory.This pin is also the program pulse input (PROG) during Flash programming.In normal operation ALE is emitted at a constant rate of 16 the oscillator frequency,and may be used for external timing or clocking purposes. Note, be disabled by setting bit 0 of SFR location 8EH.With the bit set, ALE is active onlyduring a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled external execution mode.PSEN：Program Store Enable is the read strobe to external program memory. When theAT89C51 is executing code from external program memory, PSEN is activated twiceeach machine cycle, except that two PSEN activations are skipped during each access toexternal data memory.EAVPP：External Access Enable. EA must be strapped to GND in order to enable the deviceto fetch code from external program memory locations starting at 0000H up to FFFFH.Note, alsreceives the 12-volt programming enable voltage (VPP) during Flash programming, forparts that require 12-volt VPP.XTAL1：Input to the inverting oscillator amplifier and input to the internal clock operatingcircuit.XTAL2：Output from the inverting oscillator amplifier.Oscillator CharacteristicsXTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifierwhich can be configured for use as an on-chip oscillator, as shown in Figure 1. Either aquartz crystal or ceramic resonator may be used. To drive the device from an externalclock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2.There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage idle mode, the CPU puts itself to sleep while all the onchip peripherals remainactive. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a idle is terminated by a ,from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory.Power-down ModeIn the power-down mode, the oscillator is stopped, and the instruction that invokes power-down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the power-down mode is terminated. The only exit from power-down is a -chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be either programming mode. To program any nonblank byte in the on-chip Flash Memory, the entire memory must be erased using the Chip Erase Mode.2 Programming AlgorithmBefore programming the AT89C51, the address, data and control signals should be set up according to the Flash programming mode table and Figure 3 and Figure 4. To program the AT89C51, take the following steps.1. Input the desired memory location on the addresslines.2. Input the appropriate data byte on the data lines. 3. Activate the correct combination of control signals. 4. Raise EAVPP to 12V for the the Flash array or the lock bits. The byte-write cycle is self-timed and typically takes no more than 1.5 ms. Repeat steps 1 through 5, changing the address and data for the entire array or until the end of the object file is reached. Data Polling: The AT89C51 features Data Polling to indicate the end of a write cycle. During a write cycle, an attempted read of the last byte written will result in the complement of the written datum on PO.7. Once the write cycle completed, true data are valid on all outputs, and the next cycle may begin. Data Polling may begin any time after a write cycle initiated.2.1ReadyBusy:The progress of byte programming can also be monitored by the RDYBSY output signal. P3.4 is pulled low after ALE goes when programming is done to indicate READY.Program Verify:If lock bits LB1 and LB2 programmed, the programmed code data can be read back via the address and data lines for verification. The lock bits cannot be verified directly. Verification of the lock bits is achieved by observing that their features are enabled.Figure 2-1-1 Programming the Flash Figure 2-2-2 Verifying the Flash2.2 Chip Erase:The entire Flash array is erased electrically by using the proper combination of control signals and by with all “1”s. The chip erase operation must be executed before the code memory can be re-programmed.2.3 Reading the Signature Bytes:The signature bytes are read by the same procedure as a normal verification of locations 030H, 031H, and 032H, except that P3.6 and P3.7 must be pulled to a logic low. The values returned areas follows.(030H) = 1EH indicates manufactured by Atmel(031H) = 51H indicates 89C51(032H) = FFH indicates 12V programming(032H) = 05H indicates 5V programming2.4 Programming InterfaceEvery code byte in the Flash array can be written and the entire array can be erased by using the appropriate combination of control signals. The write operation cycle is selftimed and once initiated, will automatically time itself to completion. A microcomputer interface converts information between two forms. Outside the microcomputer the information electronic system exists as a physical signal, but within the program, it is represented numerically. The function of any interface can be broken down into a number of operations which modify the data in some way, so that the process of conversion between the external and internal forms is carried out in a number of steps. An analog-to-digital converter(ADC) is used to convert a continuously variable signal to a corresponding digital form which can take any one of a fixed number of possible binary values. If the output of the transducer does not vary continuously, no ADC is necessary. In this case the signal conditioning section must convert the incoming signal to a form which can be connected directly to the next part of the interface, the inputoutput section of the microcomputer itself. Output interfaces take a similar form, the obvious difference being that is in the opposite direction; it is passed from the program to the outside world. In this case the program may call an output subroutine which supervises the operation of the interface andperforms the scaling numbers which may be needed for digital-to-analog converter(DAC). This subroutine passesinformation in turn to an output device which produces a corresponding electrical signal, which could be converted into analog form using a DAC. Finally the signal is conditioned(usually amplified) to a form suitable for operating an actuator.The signals used within microcomputer circuits are almost always too small to be connected directly to the outside world” and some kind of interface must be used to translate them to a more appropriate form. The design of section of interface circuits is one of the most important tasks facing the engineer wishing to apply microcomputers. We that in microcomputers information is represented as discrete patterns of bits; this digital form is most useful when the microcomputer is to be connected to equipment which can only be switched on or off, where each bit might represent the state of a switch or actuator. To solve real-world problems, a microcontroller must just a CPU, a program, and a data memory. In addition, it must contain from the outside world. Once the CPU gathers information and processes the data, it must also be able to effect change on some portion of the outside world. These microcontrollers is the general purpose I70 port. Each of the IO pins can be used as either an input or an output. The function of each pin is determined by setting or clearing corresponding bits in a corresponding data direction register during the initialization stage of a program. Each output pin may be driven to either a logic one or a logic zeroby using CPU instructions to pin may be viewed (or read.) by the CPU using program instructions. Some type of serial unit is included on microcontrollers to allow the CPU to communicate bit-serially with external devices. Using a bit serial format instead of bit-parallel format requires fewer IO pins to perform the communication function, which makes it less expensive, but slower.Serial transmissions are performed either synchronously orasynchronously.翻译AT89C51的概况1 AT89C51应用单片机广泛应用于商业：诸如调制解调器，电动机控制系统，空调控制系统，汽车发动机和其他一些领域。
单片机 外文翻译 外文文献 英文文献 中英对照 基于C51兼容微(宝典)
附录A 英文原文Design of PWM Controller in a MCS-51 Compatible MCUAuthor . Yue-Li Hu Wei Wang Microelectronic Research Development Center CampusP.O.B.221 149 Yanchang Rd Shanghai 200072 China Introduction PWM technology is a kind of voltage regulation method by controlling the switchfrequency of DC power with fixed voltage to modify the two-end voltage of load. Thistechnology can be used for a variety of applications including motor control temperaturecontrol and pressure control and so on. In the motor control system shown as Fig. 1 throughadjusting the duty cycle of power switch the speed of motor can be controlled. As shown inFig. 2 under the control of PWM signal the average of voltage that controls the speed ofmotor changes with Duty-cycle D t1/T in this Figure thus the motor speed can beincreased when motor power turn on decreased when power turn off.Fig.1: The Relationship between Voltage of Armature and Fig.2 Architecture of PWM Module Therefore the motor speed can be controlled with regularly adjusting the time of turn-onand turn-off. There are three methods could achieve the adjustment of duty cycle: 1 Adjustfrequency with fixed pulse-width. 2 Adjust both frequency and pulse-width. 3 Adjustpulse-width with fixed frequency. Generally there are four methods to generate the PWM signals as the following: 1Generated by the device composed of separate logic components. This method is the originalmethod which now has been discarded. 2 Generated by software. This method need CPU tocontinuously operate instructions to control I/O pins for generating PWM output signals sothat CPU can not do anything other. Therefore the method also has been discarded gradually.3 Generated by ASIC. The ASIC makes a decrease of CPU burden and steady workgenerally has several functions such as over-current protection dead-time adjustment and soon. Then the method has been widely used in many kinds of occasion now. 4 Generated byPWM function module of MCU. Through embedding PWM function module in MCU andinitializing the function PWM pins of MCU can also automatically generate PWM outsignals without CPU controlling only when need to change duty-cycle. It is the method thatwill be implemented in this paper. In this paper we propose a PWM module embedded in a 8051 microcontroller. ThePWM module can support PWM pulse signals by initializing the control register andduty-cycle register with three methods just mentioned above to adjust the duty cycle andseveral operation modes to add flexibility for user. The following section explains the architecture of the PWM module and the architecturesof basic functional blocks. Section3 describes two operation modes. Experimental andsimulation results verifying proper system operation are also shown in that section.Depending on mode of operation the PWM module creates one or more pulse-widthmodulated signals whose duty ratios can be independently adjusted. Implementation of PWM module in MCU Overview of the PWM module A block diagram of PWM module is shown in Fig.3. It is clearly from the diagram thatthe whole module is composed of two sections: PWM signal generator and dead-timegenerator with channel select logic. The PWM function can be started by the user throughimplementing some instructions for initializing the PWM module. In particular the followingpower and motion control applications are supported: DC Motor Uninterruptablel Power Supply UPSThe PWM module also has the following features: Two PWM signal outputs with complementary or independent operation Hardware dead-time generators for complementary mode Duty cycle updates are configurable to be immediated or synchronized to the PWM Fig.3 Architecture of PWM Module Details of the architecture PMW generator The architecture of the 2-output PWM generator shownin Fig.4 is based on a 16-bitresolution counter which creates a pulse-width modulated signal. The system is synthesizedby a system clock signal whose frequency can be divided by 4 times or 12 times throughsetting the value of T3M for PWM0 or T4M for PWM1 in the special register PWMCON asshown in Fig.4. To PWM0 generator the clock to 16-bit counter will be pre-divided by 4times by default when T3M is set to zero. And the clock will be divided by 12 times whenT3M is set to 1. This is also true for PWM1. The other bits in PWMCON are explained indetail in Table 1. Fig .4 Bit Mapping of PWMCON Table 1: The Bit Definition in PWMCONChannel-select logic The follow Fig. 5 shows the channel-select logic which is useful in ComplementaryMode. From this diagram it is clear to know that signal CP and CPWM control the source ofPWMH and PWML. And the details about the two control signals will be discussed in thesection 3 and the architecture of dead-time generator will also be discussed in section 5 forthe continuity of Complementary Mode. Fig. 5 Diagram of Channel-select LogicOperation Mode and Simulation Results The design has two operation modes: Independent Mode and Complimentary Mode. Bysetting the corresponding bit CPWM in register PWMCON shown in Fig.6 user can select oneof the two operation modes. When CPWM is set to zero PWM module will work inIndependent Mode whereas PWM module will work in Complimentary Mode. In thefollowing of this section the two operation mode will be explained respectively in detail andthe simulation results of the PWM module from the Synoposys VCS EDA platform whichverify the design will also be shown.Independent PWM Output Mode An Independent PWM Output mode is useful for driving loads such as the one shown inFigure 6. A particular PWM output is in the Independent Output mode when thecorresponding CP bit in the PWMCON register is set to zero.In this case two-channel PWMoutputs are independent of each other. The signal on pin PWM0/PWMH is from PWM0generator and the signal on pin PWM1/PWML is from PWM0 generator. The separate case isachieved by the channel-select logic shown in Fig. 6. The PWM I/O pins are set toindependent mode by default upon advice reset. The dead-time generator is disabled in theIndependent mode. The simulation result is shown in Figure 6 as the following Fig.6 Tr4 andtr3 are run bits to PWM0 and PWM1 respectively. Actually from this diagram Pin P15/P14 of MCU is used for PWMH/ PWML or normal I/O alternatively. Fig6 the Waveform of PWM Outputs in Independent ModeComplementary PWM Output Mode The Complementary Output mode is used to drive inverter loads similar to the oneshown in Figure 7. This inverter topology is typical for DC applications. In ComplementaryOutput Mode the pair of PWM outputs cannot be active simultaneously. The PWM channeland output pin pair are internally configured through channel-select logic as shown in Figure7.A dead-time may be optionally inserted during device switching where both outputs areinactive for a short period. Fig 7 : Typical Load for Complementary PWM Outputs The Complementary mode is selected for PWM I/O pin pair by setting the appropriateCPWM bit in PWMCON. In this case PSEL is in effect. PWMH and PWML will come fromPWM0 generator when PSEL is set to zero when the signals from PWM1 generator is uselesswhereas PWMH and PWML will come from PWM1 generator when PSEL is set to 1 whenthe signals from PWM0 generator is useless. In the process of producing the PWM outputs inComplementary Mode the dead-time will be inserted to be discussed in the following section.Dead-time Control Dead-time generation is automatically enabled when PWM I/O pin pair is operating inthe Complementary Output mode. Because the power output devices cannotswitchinstantaneously some amount of time must be provided between the turn-off event of onePWM output in a complementary pair and the turn-on event of the other transistor. The2-output PWM module has one programmable dead-time with 8-bitregister.Thecomplementary output pair for the PWM module has an 8-bit down counter that is used toproduce the dead-time insertion. As shown in Figure 8 the dead time unit has a rising andfalling edge detector connected to PWM signal from one of PWM generator. The dead timesis loaded into the timer on the detected PWM edge event. Depending on whether the edge isrising or falling one of the transitions on the complementary outputs is delayed until the timercounts down to zero. A timing diagram indicating the dead time insertion for the pair of PWMoutputs is shown in Figure 8a. Fig 8a Dead-time Unit Block Diagram Fig. 8b the Waveforms of PWM Outputs in Complementary ModeConclusions In this paper we have designed PWM module based on an 8-bit MCU compatible with8051 family. The design can generate 2-channel programmable periodic PWM signals withtwo operation mode Independent Mode and Complementary Mode in which dead-time willbe inserted. The simulation results on the EDA platform have proven its correctness andusefulness. 附录B 汉语翻译基于C51 兼容微处理器单片机的PWM 控制器设计Yue-Li Hu Wei Wa 单片机研究与开发中心Campus P.O.B.221 149Yanchang Rd Shanghai 200072 China 导言PWM 技术，是一种电压调节方法，通过控制具有固定电压的直流电源的开关频率来调整两端负荷电压。
单片机的外文文献及中文翻译
单片机的外文文献及中文翻译一、外文文献Title: The Application and Development of SingleChip Microcontrollers in Modern ElectronicsSinglechip microcontrollers have become an indispensable part of modern electronic systems They are small, yet powerful integrated circuits that combine a microprocessor core, memory, and input/output peripherals on a single chip These devices offer significant advantages in terms of cost, size, and power consumption, making them ideal for a wide range of applicationsThe history of singlechip microcontrollers can be traced back to the 1970s when the first microcontrollers were developed Since then, they have undergone significant advancements in technology and performance Today, singlechip microcontrollers are available in a wide variety of architectures and capabilities, ranging from simple 8-bit devices to complex 32-bit and 64-bit systemsOne of the key features of singlechip microcontrollers is their programmability They can be programmed using various languages such as C, Assembly, and Python This flexibility allows developers to customize the functionality of the microcontroller to meet the specific requirements of their applications For example, in embedded systems for automotive, industrial control, and consumer electronics, singlechip microcontrollers can be programmed to control sensors, actuators, and communication interfacesAnother important aspect of singlechip microcontrollers is their low power consumption This is crucial in batterypowered devices and portable electronics where energy efficiency is of paramount importance Modern singlechip microcontrollers incorporate advanced power management techniques to minimize power consumption while maintaining optimal performanceIn addition to their use in traditional electronics, singlechip microcontrollers are also playing a significant role in the emerging fields of the Internet of Things （IoT) and wearable technology In IoT applications, they can be used to collect and process data from various sensors and communicate it wirelessly to a central server Wearable devices such as smartwatches and fitness trackers rely on singlechip microcontrollers to monitor vital signs and perform other functionsHowever, the design and development of systems using singlechip microcontrollers also present certain challenges Issues such as realtime performance, memory management, and software reliability need to be carefully addressed to ensure the successful implementation of the applications Moreover, the rapid evolution of technology requires developers to constantly update their knowledge and skills to keep up with the latest advancements in singlechip microcontroller technologyIn conclusion, singlechip microcontrollers have revolutionized the field of electronics and continue to play a vital role in driving technological innovation Their versatility, low cost, and small form factor make them an attractive choice for a wide range of applications, and their importance is expected to grow further in the years to come二、中文翻译标题：单片机在现代电子领域的应用与发展单片机已成为现代电子系统中不可或缺的一部分。
at89c52单片机中英文资料对照外文翻译文献综述
D.htmlat89c52单片机中英文资料对照外文翻译文献综述at89c52单片机简介中英文资料对照外文翻译文献综述AT89C52 Single-chip microprocessor introductionSelection of Single-chip microprocessor1. Development of Single-chip microprocessorThe main component part of Single-chip microprocessor as a result of by such centralize to be living to obtain on the chip，In immediate future middle processor CPU。
Storage RAM immediately﹑memoy readROM﹑Interrupt system、Timer /'s counter along with I/O's rim electric circuit awaits the main microcomputer section，The lumping is living on the chip。
Although the Single-chip microprocessor r is only a chip，Yet through makes up and the meritorous service be able to on sees，It had haveed the calculating machine system property，calling it for this reason act as Single-chip microprocessor r minisize calculating machine SCMS and abbreviate the Single-chip microprocessor。
单片机科技文献翻译
科技文献摘译二〇一一年六月四日The monolithic integrated circuit application, first is its control function, namely lies in the realization computer control.But online control aspect, because the computation fuselage is in the system, therefore has the volume to the computer small, the power loss small, the cost low, the price inexpensive as well as the control function strong and so on the requests, to these requests really it may be said must belong to the monolithic integrated circuit.At present the monolithic integrated circuit seeps each domain which lives to us, which domain is nearly very difficult to find not to have the monolithic integrated circuit trail.The missile navigation equipment, on the airplane each kind of measuring appliance control, the computer network communication and the data transmission, the industrial automation process real-time control and the data processing, the widespread use each kind of intelligent IC card, the civil luxury car safety system, the videocorder, the camera, the completely automatic washer control, as well as program control toy, electronic pet and so on, these cannot leave the monolithic integrated circuit.Say nothing of automatic control domain robot, intelligent measuring appliance, medical instrument In humanity's each production activity and scientific experiment, in order to understand with the grasping entire process progress and the final output, needs frequently carries on the inspection and the survey to each kind of basic parameter or the physical quantity, thus obtains the essential information, and by it achievement analysis judgment and policy-making basis.The examination technology and the sensor are people in order to was measured the object contains the information carries on a series of technical measure which the qualitative understanding and quota grasping adopts.The modern of science and technology fast development causes the human society to enter the information age, mainly will depend upon in the information age people's social activity to the information resource development and the gain, the transmission and processing, but the sensor will be in head of the automatic detection and the control system, will be the sensation, the gain and the examination information window; The sensor belongs to the object of study and the observation and control system connection installment, all scientific research and the production process must gain the information, all must transform through it for easy to transmitand the processing electrical signal.Therefore the sensor status and the function is extremely important.Sensor function quite Yu Ren five senses.The system automatic routine, the intellectualized degree are higher, the system the level of dependency is bigger to the sensor, the sensor plays the decisive role to the system function.Therefore, domestic and foreign all lists as the sensor technology the most advanced technique.The sensor application sensor application domain involves the machine manufacture, the commercial run control, the automobile electronic products, the correspondence electronic products, the expense electronic products and the special purpose equipment and so on.(1) special purpose equipmentThe special purpose equipment mainly includes domain application and so on the medical service, environmental protection, meteorology specialized electronic installations.At present the medical domain is the sensor sales volume huge, the profit considerable emerging market, this domain request sensing component to the miniaturization, the low cost and the redundant reliable direction develops.(2) industrial automationIndustry domain application sensor, like craft control, industry machinery as well as tradition; Each kind of survey craft variable (for example temperature, fluid position, pressure, current capacity and so on); Survey electron characteristic (electric current, voltage and so on) and physical quantity (movement, speed, load as well as intensity), as well as the traditional close/localization sensor development is rapid.(3) correspondence electronic productsHandset output large growth and the handset new function unceasing increase brought the opportunity and the challenge for the sensor market, the colored tablet handset and the photograph handset market share rises unceasingly increased the sensor in this domain application proportion.In addition, will apply in the group telephone and the non-rope telephone ultrasonic sensor, uses in the magnistorized medium the magnetic field sensor and so on all appearing the strong trend growth.(4) automobile industryThe modern high-quality passenger vehicle computerization control system level key lies in uses the pressure transmitter quantity and the level, at present on an ordinary home use passenger vehicle probably installs several dozens arrives the near hundred sensors, but on luxury car sensor quantity may reach 200 much, the type usually reaches 30 kinds, many pieces reach hundred kindsCurrent eliminates enhances the performance unceasingly and the reliability, the sensor technology total trend of development is: The sensor integration will be refers on the identical chip or is multitudinous the identical type the single sensor integration for unidimensional, the two-dimensional sensor, or electric circuit integration integrations and so on sensor and adjustment, compensation.The sensor multi-purpose is enables the sensor simultaneously to have many kinds of examination function, the multi-purpose integrated sensor develops an important direction, namely integrates the many kinds of function sensitive unit or identical function many sensitive units on the chip, like the compound resistance sensor, a chip may simultaneously examine the pressure and the temperature.The sensor intellectualization is one kind of belt microcomputer has at the same time the examination, the judgment, the information processing, man-machine interaction, function and so on protection sensors.The sensor intellectualization is one kind of belt microcomputer has at the same time the examination, the judgment, the information processing, man-machine interaction, function and so on protection sensors.The development biological modelling sensor, the nature is the biosensor outstanding designer.It through long years, not only has accomplished many functions unusually, the performance excellent biosensor.If dog's sense of smell ability is higher than the humanity, bird's visual ability is far human's 8~15 times and so on.These animal's induction performance is the sensor technology can not hold a candle now.Therefore, will study their mechanism, the development biological modelling sensor causes the people to pay attention enormously, also will be one of sensor application development important directions.From above may see, the monolithic integrated circuit applicationsignificance is not restricted in the economic efficiency which its function as well as brings, a bigger significance lies in the monolithic integrated circuit the application fundamentally to change the traditional control system design concept and the design method, the trend of development also day by day changes, main performance for following several aspects: Manufacture craft CMOS (overall CMOS); Realizes as far as possible monolithic; General character and individuality coexistence.单片机的应用，首先是它的控制功能，即在于实现计算机控制。
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广东工业大学
本科毕业设计（论文）
外文参考文献译文及原文
系部
专业自动化
年级 2006级
班级名称
学号
学生姓名
指导教师
2009年6月
目录
外文文献译文 (1)
1.单片机定义 (1)
2.单片机介绍 (2)
3.单片机历史 (3)
4.单片机的应用领域 (4)
5.at89c52单片机介绍 (6)
外文文献原文 (8)
1. The definition of a single-chip (8)
2. single-chip introduced (9)
3. single-chip history (11)
4. single-chip applications (12)
5.at89c52 chip explains (14)
外文文献译文
1.单片机定义
单片机是指一个集成在一块芯片上的完整计算机系统。
尽管他的大部分功能集成在一块小芯片上，但是它具有一个完整计算机所需要的大部分部件：CPU、内存、内部和外部总线系统，目前大部分还会具有外存。
同时集成诸如通讯接口、定时器，实时时钟等外围设备。
而现在最强大的单片机系统甚至可以将声音、图像、网络、复杂的输入输出系统集成在一块芯片上。
单片机也被称为微控制器（Microcontroller），是因为它最早被用在工业控制领域。
单片机由芯片内仅有CPU的专用处理器发展而来。
最早的设计理念是通过将大量外围设备和CPU集成在一个芯片中，使计算机系统更小，更容易集成进复杂的而对体积要求严格的控制设备当中。
INTEL的Z80是最早按照这种思想设计出的处理器，从此以后，单片机和专用处理器的发展便分道扬镳。
早期的单片机都是8位或4位的。
其中最成功的是INTEL的8031，因为简单可靠而性能不错获得了很大的好评。
此后在8031上发展出了MCS51系列单片机系统。
基于这一系统的单片机系统直到现在还在广泛使用。
随着工业控制领域要求的提高，开始出现了16位单片机，但因为性价比不理想并未得到很广泛的应用。
90年代后随着消费电子产品大发展，单片机技术得到了巨大的提高。
随着INTEL i960系列特别是后来的ARM系列的广泛应用，32位单片机迅速取代16位单片机的高端地位，并且进入主流市场。
而传统的8位单片机的性能也得到了飞速提高，处理能力比起80年代提高了数百倍。
目前，高端的32位单片机主频已经超过300MHz，性能直追90年代中期的专用处理器，而普通的型号出厂价格跌落至1美元，最高端的型号也只有10美元。
当代单片机系统已经不再只在裸机环境下开发和使用，大量专用的嵌入式操作系统被广泛应用在全系列的单片机上。
而在作为掌上电脑和手机核心处理的高端单片机甚至可以直接使用专用的Windows和Linux操作系统。
单片机比专用处理器更适合应用于嵌入式系统，因此它得到了最多的应用。