JESD22-A105C-Power and Temperature Cycling

JESD22-A103C_2004_High_Temperature_Storage_Life

1 Scope The test is applicable for evaluation, screening, monitoring, and/or qualification of all solid state devices. High Temperature storage test is typically used to determine the effect of time and temperature, under storage conditions, for thermally activated failure mechanisms of solid state electronic devices, including nonvolatile memory devices (data retention failure mechanisms). During the test elevated temperatures (accelerated test conditions) are used without electrical stress applied. This test may be destructive, depending on Time, Temperature and Packaging (if any).
2 Apparatus 2.1 High temperature storage chambers The apparatus required for this test shall consist of a controlled temperature chamber capable of maintaining the specified temperature over the entire sample population under test. 2.2 Electrical test equipment Electrical equipment capable of performing the appropriate measurements for the devices being tested, including write and verify the required data retention pattern(s) for nonvolatile memories.

JESD22A115C Nov 2010 Electrostatic Discharge (ESD)..Machine Model

STANDARDElectrostatic Discharge (ESD) Sensitivity Testing, Machine Model (MM)JESD22-A115C(Revision of JESD22-A115B, March 2010)NOVEMBER 2010JEDEC SOLID STATE TECHNOLOGY ASSOCIATIONNOTICEJEDEC standards and publications contain material that has been prepared, reviewed, and approved through the JEDEC Board of Directors level and subsequently reviewed and approvedby the JEDEC legal counsel.JEDEC standards and publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability and improvement of products, and assisting the purchaser in selecting and obtaining with minimum delay the proper product for use by those other than JEDEC members, whether the standard is tobe used either domestically or internationally.JEDEC standards and publications are adopted without regard to whether or not their adoption may involve patents or articles, materials, or processes. By such action JEDEC does not assume any liability to any patent owner, nor does it assume any obligation whatever to parties adoptingthe JEDEC standards or publications.The information included in JEDEC standards and publications represents a sound approach to product specification and application, principally from the solid state device manufacturer viewpoint. Within the JEDEC organization there are procedures whereby a JEDEC standard or publication may be further processed and ultimately become an ANSI standard.No claims to be in conformance with this standard may be made unless all requirements stated inthe standard are met.Inquiries, comments, and suggestions relative to the content of this JEDEC standard or publication should be addressed to JEDEC at the address below, or call (703) 907-7559 orPublished by©JEDEC Solid State Technology Association 20103103 North 10th StreetSuite 240 SouthArlington, VA 22201-2107This document may be downloaded free of charge; however JEDEC retains thecopyright on this material. By downloading this file the individual agrees not tocharge for or resell the resulting material.PRICE: Refer to Printed in the U.S.A.All rights reservedPLEASE!DON’T VIOLATETHELAW!This document is copyrighted by JEDEC and may not bereproduced without permission.Organizations may obtain permission to reproduce a limited number of copies through entering into a license agreement. For information, contact:JEDEC Solid State Technology Association3103 North 10th StreetSuite 240 SouthArlington, VA 22201-2107or call (703) 907-7559SPECIAL NOTE⏹JESD22-A115 is a reference document; it is not a requirement per JESD47 (Stress Test DrivenQualification of Integrated Circuits).⏹Machine Model as described in JESD22-A115 should not be used as a requirement forintegrated circuit ESD qualification.⏹Only HBM and CDM are the necessary ESD qualification test methods as specified in JESD47.JEDEC Standard No. 22-A115CPage 1Test Method A115C(Revision of Test Method A115B)TEST METHOD A115CELECTROSTATIC DISCHARGE (ESD) SENSITIVITY TESTING,MACHINE MODEL (MM)(From JEDEC Board Ballot JCB-97-10, and JCB-10-13, and JCB-10-60, formulated under the cognizance of JC-14.1 Committee on Reliability Test Methods for Packaged Devices.)1 ScopeThis method establishes a standard procedure for testing microcircuits using an electrostatic discharge (ESD) model known commonly in the industry as the Machine Model (MM). The objective is to provide reliable, repeatable MM ESD test results. There is limited data supporting the ability of this model to simulate discharges of machinery or to establish manufacturing handling practices. However, the model is useful for producing human-body model (HBM)-like ESD effects at lower voltages and for failure mode determination. The method produces results with are closely related to HBM and produces similar failure modes.2 ApparatusThis test method requires the following equipment. 2.1 SimulatorAn ESD Pulse Simulator and a Device Under Test (DUT) socket equivalent to the circuit of Figure 1. The simulator must be capable of supplying pulses with the characteristics required by Figure 2 and Figure 3.2.2 OscilloscopeThe oscilloscope and amplifier combination shall have a 350 MHz minimum single-shot bandwidth and a visual writing speed of 4 cm/ns minimum.2.3 Current probeThe current probe shall have a minimum pulse-current bandwidth of 350 MHz. A current probe(transformer and cable with a nominal length of 1 meter) with a 1 GHz bandwidth and a current rating of 12 amperes maximum pulse-current is recommended.2.4 Evaluation LoadsAn 18 AWG tinned copper wire is recommended for the short waveform verification test. The lead length should be as short as practicable to span the distance between the two farthest pins in the socket while passing through the current probe. The ends of the 18 AWG wire may be ground to a point where clearance is needed to make contact on fine pitch socket pins.JEDEC Standard No. 22-A115C Page 2Test Method A115B(Revision of Test Method A115B)2 Apparatus (cont’d) 2.4 Evaluation Loads (cont’d)A 500 ohm +/-1%, 1000 volt, low inductance resistor shall be used for initial system checkout and periodic system recalibration.Figure 1 — Typical equivalent MM ESD circuitNOTE 1 The performance of any simulator is influenced by its parasitic capacitance and inductance.NOTE 2 Precautions must be taken in tester design to avoid recharge transients and multiple pulses.NOTE 3 R2, used for initial equipment qualification and requalification as specified in 3.1, shall be a low inductance, 1000 volt, 500 ohm resistor with +/-1% tolerance.NOTE 4 Stacking of DUT socket adaptors (piggybacking) is allowed only if the waveforms can be verified to meet the specifications in Table 1.NOTE 5 Reversal of terminal A and B to achieve dual polarity is not permitted.NOTE 6 S2 should be closed 10 to 100 milliseconds after the pulse delivery period to ensure the DUT socket is not left in a charged state.NOTE 7 C1, 200 pF +/- 10%.JEDEC Standard No. 22-A115CPage 3Test Method A115C(Revision of Test Method A115B)2 Apparatus (cont’d)Figure 2 — Current Waveform through a shorting wire, 400 volt dischargeFigure 3 — Current waveform through a 500 ohm resistor, 400 volt dischargeJEDEC Standard No. 22-A115C Page 4Test Method A115B(Revision of Test Method A115B)3 Qualification, calibration, and waveform verification3.1 Equipment qualificationEquipment calibration must be performed during initial acceptance testing. Recalibration is required whenever equipment repairs are made that may affect the waveform and a minimum of every 12 months. The tester must meet the requirements of Table 1 and Figure 2 at all voltage levels using the shorting wire and at the 400 volt level with the 500 ohm resistor (see Figure 3). The waveform measurements during calibration shall be made using the worst-case pin on the highest pin count board with a positivemechanical clamp socket. (Machine repeatability should be verified during initial equipment acceptance by performing a minimum of 5 consecutive positive and a minimum of 5 consecutive negative waveforms at a voltage level in Table 1.) The high-voltage relays and associated high-voltage circuitry shall be tested by the user of computer-controlled systems per the equipment manufacturer's instructions (system diagnostics). This test will check for any open or short relays.Table 1 — Waveform specificationVoltage Level (V) Positive Ipeak for Short, Ips1(A) Positive Ipeak for 500 Ohm* Ipr (A) Current at 100 ns for 500 Ohm* I100 (A)Maximum Ringing Current, I R(A) Resonance Frequency for Short, FR (1/t fr )(Mhz)100 1.5 - 2.0 N/A N/A Ips1 x 30% 11 - 16 200 2.8 - 3.8 N/A N/A Ips1 x 30% 11 - 16 4005.8 - 8.0I100 x 4.5 maximum0.29+/-20%Ips1 x 30%11 - 16* The 500 ohm load is used only during Equipment Qualification as specified in 3.1.3.1.1 Safety TrainingDuring initial equipment set-up, the safety engineer or applicable safety representative, shall inspect the equipment in its operating location to ensure that the equipment is not operated in a combustible (hazardous) environment.Additionally, all personnel shall receive system operational training and electrical safety training prior to using the equipment.JEDEC Standard No. 22-A115CPage 5Test Method A115C(Revision of Test Method A115B)3 Qualification, calibration, and waveform verification (cont’d)3.2 Worst-case pinThe worst-case pin combination for each socket and DUT board shall be identified and documented. It is recommended that the manufacturers supply the worst-case pin data with each DUT board. The pin combination with the waveform closest to the limits (see Table 1) shall be designated for waveform verification.The worst-case pin combination shall be identified by the following procedure.3.2.1 For each test socket, identify the socket pin with the shortest wiring path from the pulsegenerating circuit to the test socket. Connect this pin to Terminal B (where it will remain the referenced pin throughout the worst case pin search) and connect one of the remaining pins to Terminal A. Attach a shorting wire between these pins with the current probe around the shorting wire, as close to Terminal B as practicable.3.2.2 Apply a positive 400 volt pulse and a negative 400 volt pulse and verify that the waveform meets the requirements defined in Table 1 for both positive and negative pulses.3.2.3 Repeat steps 3.2.1 and 3.2.2 until all socket pins have been evaluated.3.2.4 Determine the worst-case pin pair (within the limits and closest to the minimum or maximum parameter values as specified in Table 1) to be used for future waveform verification.3.2.5 For initial board check-out, connect a 500 ohm resistor between the worst-case pins previously identified with the shorting wire in step 3.2.4. Apply a positive and negative 400 volt pulse and verify that the waveform meets the requirements defined in Table 1.NOTE In case the test socket/test board has already been characterized for worst-case pin on HBM, then that pin combination is acceptable for use with MM waveform verification.As an alternative to the worst-case pin search, the reference pin pair may be identified for each test socket of each test fixture. The reference pin combination shall be identified by determining the socket pin with the shortest wiring path from the pulse generating circuit to the test socket. Connect this pin to Terminal B and then connect the socket pin with the longest wiring path from the pulse generating circuit to the test socket to Terminal A (normally provided by the manufacturer). Attach a shorting wire between these pins with the current probe around the shorting wire. Follow the procedure in step 3.2.2. For the initial board check-out connect a 500 ohm resistor between the reference pins. Apply a positive and negative 400 volt pulse and verify that the waveform meets the parameters in Table 1.JEDEC Standard No. 22-A115C Page 6Test Method A115B(Revision of Test Method A115B)3 Qualification, calibration, and waveform verification (cont’d)3.3 Waveform verificationThe waveform verification shall be performed at the beginning of each shift a tester is operated and when a socket/DUT board is changed. If at any time the waveforms do not meet the requirements defined in Figure 1 and Table 1 at the 400 volt level, the testing shall be halted until the waveform is in compliance. Additionally, the system diagnostics test as defined in 3.1 for automated systems shall be performed prior to the beginning of each shift testing is done. The period between waveform checks may be extended providing test data supports the increased interval. In case the waveform no longer meets the limits in Table 1, all ESD testing performed after the previous satisfactory waveform check will be considered invalid.3.3.1 With the required DUT socket installed and with no part in the socket, attach a shorting wire in the DUT socket such that the worst-case pins are connected between Terminal A and Terminal B as shown in Figure 2. Place the current probe around the shorting wire.3.3.2 Initiate a positive pulse at the 400 volt level per Table 1 and Figure 2. Verify that all parameters meet the limits specified in Table 1 and Figure 1.3.3.3 Initiate a negative pulse at the 400 volt level per Table 1. Verify that all parameters meet the limits specified in Table 1 and Figure 1.4 CharacterizationThe devices used for characterization testing must have completed all normal manufacturing operations.4.1 Prior to ESD testing, dc parametric and functional testing at room temperature and, if applicable, high temperature shall be performed on all devices submitted for ESD testing. The test devices shall meet device data sheet requirements for these parameters.4.2 A sample of 3 devices for each voltage level shall be characterized for the device ESD failurethreshold using the voltage steps shown in Table 1. Finer voltage steps may optionally be used to obtain a more accurate measure of the failure threshold. ESD Testing should begin at the lowest step in Table 1. The ESD test shall be performed at room temperature.4.3 Each sample of 3 devices shall be stressed at one voltage level using 1 positive and 1 negative pulses with a minimum of 0.5 second between pulses per pin for all pin combinations specified in Table 2. It is permitted to use a separate sample of 3 devices for each pin combination specified in Table 2. It is permitted to use the same sample (3) at the next higher voltage stress level if all parts pass the failure criteria specified in clause 5 after ESD exposure to a specified voltage level.JEDEC Standard No. 22-A115CPage 7Test Method A115C(Revision of Test Method A115B)4 Characterization (cont’d)4.4 Pin combinations, t he pin combinations to be used are given in Table 2. The actual number of pin combinations depends on the number of power pin groups. Like named power pins (VCC1, VCC2, VSS1, VSS2, GND, etc.) that are directly connected by metal (inside the package) may be tied together and treated as one pin for Terminal B connection. Otherwise, each power pin must be treated as a separate power pin. Programming pins that do not draw current should be considered as I/O pins(example: Vpp pins on memory devices). Active discrete devices (FETs, transistors, etc.) shall be tested using all possible pin-pair combinations (one pin connected to Terminal A, another pin connected to Terminal B) regardless of pin name or function. All pins configured as "no connect" pins shall beverified as “no-connect” and left open (floating) at all times. Pins labeled “no-connect”, that in fact are connected, shall be tested as non-supply pins.Table 2 — Pin Combinations for Integrated Circuits PinCombinationConnect Individually to Terminal A Connect to Terminal B (Ground) Floating Pins (unconnected) 1All pins one at a time, except the pin(s) connectedto Terminal B First power pin(s)All pins except 1/PUT* and first power pin(s) 2 All pins one at a time, except the pin(s) connectedto Terminal B Second power pin(s)All pins except PUT and second power pin(s) 3 All pins one at a time, except the pin(s) connectedto Terminal B Nth power pin(s)All pins except PUT and Nth power pin(s) 4Each Non-supply pin, oneat a timeAll other Non-supply pins collectively except PUTAll power pins* 1/PUT - Pin under test.4.5 If a different sample group is ESD tested at each stress level, it is permitted to perform the dc parametric and functional ATE testing after all sample groups have been ESD tested.5 Failure criteriaA part will be defined as a failure if, after exposure to ESD pulses, it no longer meets the device datasheet requirements using parametric and functional testing. If testing is required at multiple temperatures, testing shall be performed at the lowest temperature first.JEDEC Standard No. 22-A115CPage 8Annex A (informative) Differences between JESD22-A115C and JESD22A-115BThis table briefly describes most of the changes made to entries that appear in this standard,JESD22-A115C, compared to its predecessor, JESD22-A115B (March 2010). If the change to a concept involves any words added or deleted (excluding deletion of accidentally repeated words), it is included. Some punctuation changes are not included.Clause Description of ChangeCover Added a “Special Note” to the forth page of the documentA.1 Differences between JESD22-A115B and JESD22A-115-AClause Description of Change1 Modified Scope to give users a better understanding of the relative merits and status ofmachine Model 9MM) testing.4 Changed title from Classification testing to Characterization4 First paragraph, replaced classification with characterization6 This clause was removed in this revision.Test Method A115B(Revision of Test Method A115B)Rev. 7/08Standard Improvement Form JEDEC JESD22-A115CThe purpose of this form is to provide the Technical Committees of JEDEC with input from the industry regarding usage of the subject standard. Individuals or companies are invited to submit comments to JEDEC. All comments will be collected and dispersed to the appropriate committee(s).If you can provide input, please complete this form and return to:JEDECAttn: Publications Department 3103 North 10th Street Suite 240 SouthArlington, VA 22201-2107Fax: 703.907.75831. I recommend changes to the following: Requirement, clause numberTest method number Clause numberThe referenced clause number has proven to be:Unclear Too Rigid In ErrorOther2. Recommendations for correction:3. Other suggestions for document improvement:Submitted by Name: Phone: Company: E-mail:Address:City/State/Zip:Date:。

jedec标准列表

JESD22-A100E:2020 Cycled Temperature-Humidity-Bias with Surface Condensation Life Test (循环温度-湿度-偏差与表面凝结寿命测试)JESD22-A101D.01:2021 Steady-State Temperature-Humidity Bias Life Test(稳态温度-湿度偏差寿命测试)JESD22-A102E:2015(R2021) Accelerated Moisture Resistance - Unbiased Autoclave (加速的耐湿性-无偏高压灭菌器)JESD22-A103E.01:2021 High Temperature Storage Life(高温储存寿命)JESD22-A104F :2020 Temperature Cycling(温度循环)JESD22-A105D:2020 Power and Temperature Cycling(功率和温度循环)JESD22-A106B.01:2016 Thermal Shock(热冲击)JESD22-A107C:2013 Salt Atmosphere(盐雾)JESD22-A108F:2017 Temperature, Bias, And Operating Life(温度,偏置和使用寿命) JESD22-A109B:2011 HERMETICITY(气密性)JESD22-A110E.01:2020 Highly Accelerated Temperature and Humidity Stress Test (HAST) -高加速温度和湿度应力测试(HAST)JESD22-A111B :2018 Evaluation Procedure for Determining Capability to Bottom Side Board Attach by Full Body Solder Immersion of Small Surface Mount Solid State Devices(通过小型表面安装固态器件的全身焊锡浸入确定底部侧板连接能力的评估程序)。

封装的JEDEC标准

2 x) S6 B) M* p; J" C6 kHTFB：high temperature forward bias高温正偏试验
. g8 s- X. d3 Y. @- VHTRB：high temperature reverse bias高温反偏试验
HTGB：high temperature gate bias高温栅偏试验
( o+ l! [+ g2 F: @
（TST）
JESD22A106-B
据查是晶圆级的考核
23
盐雾试验
JESD22-A107-B
24
耐焊接热试验标准
JESD22-B106-B
25
温湿度敏感器件的符号与标识
JEP113-B
26
表贴半导体器件的共面性试验
JESD22-B108
HTOL：high temperature operating life高温工作寿命试验
168hrs
5
温度循环试验
（TCT）
JESD22-A104D
500cycles
6
温度循环寿命测试
JESD22-A100C
7
上电温度循环
22A105-B
8
高温储存试验
（HTST）
JESD22-A103C
1000hrs
9
高温环境条件下的工作寿命试验
JESD22-A108C
10
恒温恒湿试验
（THT）
JESD22-A101C
JESD22-B102E
16
晶须试验
JESD22A121
17
跌落试验
IMAPS-drop-impact-dynamic-response-2008

JEDEC工业标准

JEDEC工业标准环境应力试验[JDa1]JESD22-A100-B Cycled Temperature-Humidity-Bias Life Test 上电温湿度循环寿命试验, (Revision of JESD22-A100-A) April 2000 [Text-jd001][JDa2]JESD22-A101-B Steady State Temperature Humidity Bias Life Test 上电温湿度稳态寿命试验, (Revision of JESD22-A101-A) April 1997 [Text-jd002][JDa3]JESD22-A102-C Accelerated Moisture Resistance -Unbiased Autoclave高加速蒸煮试验, (Revision of JESD22-A102-B) December 2000 [Text-jd003][JDa4]JESD22-A103-A Test Method A103-A High Temperature Storage Life高温储存寿命试验, (Revision of Test Method A103 Previously Published in JESD22-B) July 1989 [Text-jd004] [JDa5]JESD22-A103-B High Temperature Storage Life高温储存寿命试验, (Revision of JESD22-A103-A) August 2001 [Text-jd005][JDa6]JESD22-A104-B Temperature Cycling温度循环, (Revision of JESD22-A104-A) July 2000 (参见更新版本A104C) [Text-jd006][JDa7]EIA/JESD22-A105-B Test Method A105-B Power and Temperature Cycling上电和温度循环, (Revision of Test Method A105-A) February 1996 [Text-jd007][JDa8]JESD22-A106-A Test Method A106-A Thermal Shock热冲击, (Revision of Test Method A106-Previously Published in JESD22-B) April 1995 [Text-jd008][JDa9]JESD22-A107-A Salt Atmosphere盐雾试验, (Revision of Test Method A107-Previously Published in JESD22-B) December 1989 [Text-jd009][JDa10]JESD22-A108-B Temperature, Bias, and Operating Life高温环境条件下的工作寿命试验, (Revision of JESD22-A108-A) December 2000[JDa11]JESD22-A110-B Test Method A110-B Highly-Accelerated Temperature and Humidity Stress Test (HAST)高加速寿命试验, (Revision of Test Method A110-A) February 1999 [Text-jd010] [JDa12]JESD22-A113-B Preconditioning of Nonhermetic Surface Mount Devices Prior to Reliability Testing非密封表贴器件在可靠性试验以前的预处理, (Revision of Test Method A113-A)March 1999 [Text-jd011][JDa13]JESD22-A118 Accelerated Moisture Resistance - Unbiased HAST不上电的高加速湿气渗透试验, December 2000 [Text-jd012][JDa14]JESD22-B106-B Test Method B106-B Resistance to Soldering Temperature for Through-Hole Mounted Devices插接器件的抗焊接温度试验, (Revision of Test Method B106-A) February1999 [Text-jd013][JDa15]EIA/JESD47 Stress-Test-Driven Qualification of Integrated Circuits集成电路施加应力的产品验收试验, July 1995 [Text-jd031][JDa1]JESD22-A104C Temperature Cycling, (Revision of JESD22-A104-B) May 2005 [Text-jd040]电应力和电测试试验[JDb1]JESD22-A114-B Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM)人体模型条件下的静电放电敏感度试验, (Revision of JESD22-A114-A) June 2000 [Text-jd014] [JDb2]EIA/JESD22-A115-A Electrostatic Discharge (ESD) Sensitivity Testing Machine Model (MM)机器模型条件下的静电放电敏感度试验, (Revision of EIA/JESD22-A115) October 1997 [Text-jd015][JDb3]JESD22-A117 Electrically Erasable Programmable ROM (EEPROM) Program/Erase Endurance and Data Retention Test EEPROM的擦涂和数据保存试验, January 2000 [Text-jd016][JDb4]EIA/JESD78 IC Latch-Up Test集成电路器件闩锁试验, March 1997 [Text-jd017][JDb5]JESD22-C101-A Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components微电子器件在电荷感应模型条件下的抗静电放电试验, (Revision of JESD22-C101) June 2000 [Text-jd018]机械应力试验[JDc1]JESD-22-B103-A Test Method B103-A Vibration, Variable Frequency振动和扫频试验 (Revision of Test Method B103 Previously Published in JESD22-B) July 1989 [Text-jd019] [JDc2]JESD22-B104-A Test Method B104-A Mechanical Shock机械冲击 (Revision of Test Method B104, Previously Published in JEDEC Standard No.22-B) September 1990 [Text-jd020][JDc3]EIA/JESD22-B116 Wire Bond Shear Test Method焊线邦定的剪切试验方法, July 1998 [Text-jd021][JDc4]JESD22-B117 BGA Ball Shear BGA焊球的剪切试验, July 2000 [Text-jd022][JDc5]JESD22B113 Board Level Cyclic Bend Test Method for Interconnect Reliability Characterization of Components for Handheld Electronic Products, March 2006 [Text-jd038] [JDc6]JESD22-B111 Board Level Drop Test Method of Components for Handheld Electronic Products, July 2003 [Text-jd039]综合试验与测试[JDd1]JEDEC Standard No.22-A109 Test Method A109 Hermeticity密封性试验, July 1988 [Text-jd023][JDd2]JESD22-A120 Test Method for the Measurement of Moisture Diffusivity and Water Solubility in Organic Materials Used in Integrated Circuits集成电路器件中使用的有机材料水分扩散和水溶性测定试验方法, June 2001 [Text-jd024][JDd3]JESD22-B100-A Physical Dimensions物理尺寸的测量, (Revision of Test Method B100-Previously Published in JESD22-B) April 1990 [Text-jd025][JDd4]JESD22-B101 Test Method B101 External Visual外观检查, (Previously published in JESD22-B) September 1987 [Text-jd026][JDd5]EIA/JESD22-B102-C Solderability Test Method可焊性试验方法, September 1998 [Text-jd027] [JDd6]EIA/JESD22-B105-B Test Method B105-B Lead Integrity器件管脚的完整性试验, (Revision of Test Method B105-A) January 1999 [Text-jd028][JDd7]EIA/JESD22-B107-A Test Method B107-A Marking Permanency图标的耐久性试验, (Revision of Test Method B107-Previously Published in JESD22-B) September 1995 [Text-jd029] [JDd8]JESD22-B108 Coplanarity Test for Surface-Mount Semiconductor Devices表贴半导体器件的共面性试验, November 1991 [Text-jd030]其它[JDe1]JEP113-B Symbol and Labels for Moisture-Sensitive Devices湿度敏感器件的符号和标识, (Revision of JEP113-A) May 1999 [Text-jd032][JDe2]EIA/JEP122 Failure Mechanisms and Models for Silicon Semiconductors Devices硅半导体器件的失效机理和模型, February 1996 [Text-jd033][JDe3]IPC/JEDEC J-STD-020A Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices针对非密封表贴半导体器件的湿度/回流焊敏感度分类和级别,April 1999 [Text-jd034][JDe4]IPC/JEDEC J-STD-033 Standard for Handling, Packing, Shipping and Use of Moisture/Reflow Sensitive Surface Mount Devices湿度/回流焊敏感标贴器件的处理、包装、运输和使用的标准, May 1999 [Text-jd035][JDe5]EIA/JEP103-A Suggested Product-Documentation Classifications and Disclaimers, (Revision of JEP103) July 1996 [Text-jd036][JDe6]IPC/JEDEC J-STD-020D.1 Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices针对非密封表贴半导体器件的湿度/回流焊敏感度分类和级别,Supersedes IPC/JEDEC J-STD-020D August 2007, March 2008 [Text-jd037]。

JEDEC工业标准

JEDEC工业标准环境应力试验[JDa1]JESD22-A100-B Cycled Temperature-Humidity-Bias Life Test 上电温湿度循环寿命试验, (Revision of JESD22-A100-A) April 2000 [Text-jd001][JDa2]JESD22-A101-B Steady State Temperature Humidity Bias Life Test 上电温湿度稳态寿命试验, (Revision of JESD22-A101-A) April 1997 [Text-jd002][JDa3]JESD22-A102-C Accelerated Moisture Resistance -Unbiased Autoclave高加速蒸煮试验, (Revision of JESD22-A102-B) December 2000 [Text-jd003][JDa4]JESD22-A103-A Test Method A103-A High Temperature Storage Life高温储存寿命试验, (Revision of Test Method A103 Previously Published in JESD22-B) July 1989[Text-jd004][JDa5]JESD22-A103-B High Temperature Storage Life高温储存寿命试验, (Revision of JESD22-A103-A) August 2001 [Text-jd005][JDa6]JESD22-A104-B Temperature Cycling温度循环, (Revision of JESD22-A104-A) July 2000 (参见更新版本A104C) [Text-jd006][JDa7]EIA/JESD22-A105-B Test Method A105-B Power and Temperature Cycling上电和温度循环, (Revision of Test Method A105-A) February 1996 [Text-jd007][JDa8]JESD22-A106-A Test Method A106-A Thermal Shock热冲击, (Revision of Test Method A106-Previously Published in JESD22-B) April 1995 [Text-jd008][JDa9]JESD22-A107-A Salt Atmosphere盐雾试验, (Revision of Test Method A107-Previously Published in JESD22-B) December 1989 [Text-jd009][JDa10]JESD22-A108-B Temperature, Bias, and Operating Life高温环境条件下的工作寿命试验, (Revision of JESD22-A108-A) December 2000[JDa11]JESD22-A110-B Test Method A110-B Highly-Accelerated Temperature and Humidity Stress Test (HAST)高加速寿命试验, (Revision of Test MethodA110-A) February 1999 [Text-jd010][JDa12]JESD22-A113-B Preconditioning of Nonhermetic Surface Mount Devices Prior to Reliability Testing非密封表贴器件在可靠性试验以前的预处理, (Revision of TestMethod A113-A) March 1999 [Text-jd011][JDa13]JESD22-A118 Accelerated Moisture Resistance - Unbiased HAST不上电的高加速湿气渗透试验, December 2000 [Text-jd012][JDa14]JESD22-B106-B Test Method B106-B Resistance to Soldering Temperature for Through-Hole Mounted Devices插接器件的抗焊接温度试验, (Revision of Test Method B106-A) February 1999 [Text-jd013][JDa15]EIA/JESD47 Stress-Test-Driven Qualification of Integrated Circuits集成电路施加应力的产品验收试验, July 1995 [Text-jd031][JDa1]JESD22-A104C Temperature Cycling, (Revision of JESD22-A104-B) May 2005 [Text-jd040]电应力和电测试试验[JDb1]JESD22-A114-B Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM)人体模型条件下的静电放电敏感度试验, (Revision of JESD22-A114-A)June 2000 [Text-jd014][JDb2]EIA/JESD22-A115-A Electrostatic Discharge (ESD) Sensitivity Testing Machine Model (MM)机器模型条件下的静电放电敏感度试验, (Revision of EIA/JESD22-A115)October 1997 [Text-jd015][JDb3]JESD22-A117 Electrically Erasable Programmable ROM (EEPROM) Program/Erase Endurance and Data Retention Test EEPROM的擦涂和数据保存试验, January 2000 [Text-jd016][JDb4]EIA/JESD78 IC Latch-Up Test集成电路器件闩锁试验, March 1997 [Text-jd017] [JDb5]JESD22-C101-A Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components微电子器件在电荷感应模型条件下的抗静电放电试验, (Revision of JESD22-C101) June2000 [Text-jd018]机械应力试验[JDc1]JESD-22-B103-A Test Method B103-A Vibration, Variable Frequency振动和扫频试验(Revision of Test Method B103 Previously Published in JESD22-B) July1989 [Text-jd019][JDc2]JESD22-B104-A Test Method B104-A Mechanical Shock机械冲击(Revision of Test Method B104, Previously Published in JEDEC Standard No.22-B) September 1990[Text-jd020][JDc3]EIA/JESD22-B116 Wire Bond Shear Test Method焊线邦定的剪切试验方法, July 1998 [Text-jd021][JDc4]JESD22-B117 BGA Ball Shear BGA焊球的剪切试验, July 2000 [Text-jd022][JDc5]JESD22B113 Board Level Cyclic Bend Test Method for Interconnect Reliability Characterization of Components for Handheld Electronic Products, March 2006[Text-jd038][JDc6]JESD22-B111 Board Level Drop Test Method of Components for Handheld Electronic Products, July 2003 [Text-jd039]综合试验与测试[JDd1]JEDEC Standard No.22-A109 Test Method A109 Hermeticity密封性试验, July 1988 [Text-jd023][JDd2]JESD22-A120 Test Method for the Measurement of Moisture Diffusivity and Water Solubility in Organic Materials Used in Integrated Circuits集成电路器件中使用的有机材料水分扩散和水溶性测定试验方法, June 2001 [Text-jd024][JDd3]JESD22-B100-A Physical Dimensions物理尺寸的测量, (Revision of Test Method B100-Previously Published in JESD22-B) April 1990 [Text-jd025][JDd4]JESD22-B101 Test Method B101 External Visual外观检查, (Previously published in JESD22-B) September 1987 [Text-jd026][JDd5]EIA/JESD22-B102-C Solderability Test Method可焊性试验方法, September 1998 [Text-jd027][JDd6]EIA/JESD22-B105-B Test Method B105-B Lead Integrity器件管脚的完整性试验, (Revision of Test Method B105-A) January 1999 [Text-jd028][JDd7]EIA/JESD22-B107-A Test Method B107-A Marking Permanency图标的耐久性试验, (Revision of Test Method B107-Previously Published in JESD22-B) September 1995 [Text-jd029][JDd8]JESD22-B108 Coplanarity Test for Surface-Mount Semiconductor Devices表贴半导体器件的共面性试验, November 1991 [Text-jd030]其它[JDe1]JEP113-B Symbol and Labels for Moisture-Sensitive Devices湿度敏感器件的符号和标识, (Revision of JEP113-A) May 1999 [Text-jd032][JDe2]EIA/JEP122 Failure Mechanisms and Models for Silicon Semiconductors Devices硅半导体器件的失效机理和模型, February 1996 [Text-jd033][JDe3]IPC/JEDEC J-STD-020A Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices针对非密封表贴半导体器件的湿度/回流焊敏感度分类和级别, April 1999 [Text-jd034][JDe4]IPC/JEDEC J-STD-033 Standard for Handling, Packing, Shipping and Use of Moisture/Reflow Sensitive Surface Mount Devices湿度/回流焊敏感标贴器件的处理、包装、运输和使用的标准, May 1999 [Text-jd035][JDe5]EIA/JEP103-A Suggested Product-Documentation Classifications and Disclaimers, (Revision of JEP103) July 1996 [Text-jd036][JDe6]IPC/JEDEC J-STD-020D.1 Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices针对非密封表贴半导体器件的湿度/回流焊敏感度分类和级别, Supersedes IPC/JEDEC J-STD-020D August 2007, March2008 [Text-jd037]。

关于JESD的标准族统一编号

JEDEC工业标准环境应力试验[JDa1]JESD22-A100-B Cycled Temperature-Humidity-Bias Life Test 上电温湿度循环寿命试验, (Revision of JESD22-A100-A) April 2000 [Text-jd001][JDa2]JESD22-A101-B Steady State Temperature Humidity Bias Life Test 上电温湿度稳态寿命试验, (Revision of JESD22-A101-A) April 1997 [Text-jd002][JDa3]JESD22-A102-C Accelerated Moisture Resistance -Unbiased Autoclave高加速蒸煮试验, (Revision of JESD22-A102-B) December 2000 [Text-jd003][JDa4]JESD22-A103-A Test Method A103-A High Temperature Storage Life高温储存寿命试验, (Revision of Test Method A103 Previously Published in JESD22-B) July 1989 [Text-jd004] [JDa5]JESD22-A103-B High Temperature Storage Life高温储存寿命试验, (Revision of JESD22-A103-A) August 2001 [Text-jd005][JDa6]JESD22-A104-B Temperature Cycling温度循环, (Revision of JESD22-A104-A) July 2000 (参见更新版本A104C) [Text-jd006][JDa7]EIA/JESD22-A105-B Test Method A105-B Power and Temperature Cycling上电和温度循环, (Revision of Test Method A105-A) February 1996 [Text-jd007][JDa8]JESD22-A106-A Test Method A106-A Thermal Shock热冲击, (Revision of Test Method A106-Previously Published in JESD22-B) April 1995 [Text-jd008][JDa9]JESD22-A107-A Salt Atmosphere盐雾试验, (Revision of Test Method A107-Previously Published in JESD22-B) December 1989 [Text-jd009][JDa10]JESD22-A108-B Temperature, Bias, and Operating Life高温环境条件下的工作寿命试验, (Revision of JESD22-A108-A) December 2000[JDa11]JESD22-A110-B Test Method A110-B Highly-Accelerated Temperature and Humidity Stress Test (HAST)高加速寿命试验, (Revision of Test Method A110-A) February 1999[Text-jd010][JDa12]JESD22-A113-B Preconditioning of Nonhermetic Surface Mount Devices Prior to Reliability Testing非密封表贴器件在可靠性试验以前的预处理, (Revision of Test Method A113-A)March 1999 [Text-jd011][JDa13]JESD22-A118 Accelerated Moisture Resistance - Unbiased HAST不上电的高加速湿气渗透试验, December 2000 [Text-jd012][JDa14]JESD22-B106-B Test Method B106-B Resistance to Soldering Temperature for Through-Hole Mounted Devices插接器件的抗焊接温度试验, (Revision of Test MethodB106-A) February 1999 [Text-jd013][JDa15]EIA/JESD47 Stress-Test-Driven Qualification of Integrated Circuits集成电路施加应力的产品验收试验, July 1995 [Text-jd031][JDa16]JESD22-A104C Temperature Cycling, (Revision of JESD22-A104-B) May 2005 [Text-jd040]电应力和电测试试验[JDb1]JESD22-A114-B Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM)人体模型条件下的静电放电敏感度试验, (Revision of JESD22-A114-A) June 2000 [Text-jd014][JDb2]EIA/JESD22-A115-A Electrostatic Discharge (ESD) Sensitivity Testing Machine Model (MM)机器模型条件下的静电放电敏感度试验, (Revision of EIA/JESD22-A115) October1997 [Text-jd015][JDb3]JESD22-A117 Electrically Erasable Programmable ROM (EEPROM) Program/Erase Endurance and Data Retention Test EEPROM的擦涂和数据保存试验, January 2000[Text-jd016][JDb4]EIA/JESD78 IC Latch-Up Test集成电路器件闩锁试验, March 1997 [Text-jd017][JDb5]JESD22-C101-A Field-Induced Charged-Device Model Test Method forElectrostatic-Discharge-Withstand Thresholds of Microelectronic Components微电子器件在电荷感应模型条件下的抗静电放电试验, (Revision of JESD22-C101) June2000 [Text-jd018]机械应力试验[JDc1]JESD-22-B103-A Test Method B103-A Vibration, Variable Frequency振动和扫频试验(Revision of Test Method B103 Previously Published in JESD22-B) July 1989 [Text-jd019] [JDc2]JESD22-B104-A Test Method B104-A Mechanical Shock机械冲击(Revision of Test Method B104, Previously Published in JEDEC Standard No.22-B) September 1990[Text-jd020][JDc3]EIA/JESD22-B116 Wire Bond Shear Test Method焊线邦定的剪切试验方法, July 1998 [Text-jd021][JDc4]JESD22-B117 BGA Ball Shear BGA焊球的剪切试验, July 2000 [Text-jd022][JDc5]JESD22B113 Board Level Cyclic Bend Test Method for Interconnect Reliability Characterization of Components for Handheld Electronic Products, March 2006 [Text-jd038] [JDc6]JESD22-B111 Board Level Drop Test Method of Components for Handheld Electronic Products, July 2003 [Text-jd039]综合试验与测试[JDd1]JEDEC Standard No.22-A109 Test Method A109 Hermeticity密封性试验, July 1988 [Text-jd023][JDd2]JESD22-A120 Test Method for the Measurement of Moisture Diffusivity and Water Solubility in Organic Materials Used in Integrated Circuits集成电路器件中使用的有机材料水分扩散和水溶性测定试验方法, June 2001 [Text-jd024][JDd3]JESD22-B100-A Physical Dimensions物理尺寸的测量, (Revision of Test Method B100-Previously Published in JESD22-B) April 1990 [Text-jd025][JDd4]JESD22-B101 Test Method B101 External Visual外观检查, (Previously published in JESD22-B) September 1987 [Text-jd026][JDd5]EIA/JESD22-B102-C Solderability Test Method可焊性试验方法, September 1998 [Text-jd027][JDd6]EIA/JESD22-B105-B Test Method B105-B Lead Integrity器件管脚的完整性试验, (Revision of Test Method B105-A) January 1999 [Text-jd028][JDd7]EIA/JESD22-B107-A Test Method B107-A Marking Permanency图标的耐久性试验, (Revision of Test Method B107-Previously Published in JESD22-B) September 1995[Text-jd029][JDd8]JESD22-B108 Coplanarity Test for Surface-Mount Semiconductor Devices表贴半导体器件的共面性试验, November 1991 [Text-jd030]其它[JDe1]JEP113-B Symbol and Labels for Moisture-Sensitive Devices湿度敏感器件的符号和标识, (Revision of JEP113-A) May 1999 [Text-jd032][JDe2]EIA/JEP122 Failure Mechanisms and Models for Silicon Semiconductors Devices硅半导体器件的失效机理和模型, February 1996 [Text-jd033][JDe3]IPC/JEDEC J-STD-020A Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices针对非密封表贴半导体器件的湿度/回流焊敏感度分类和级别, April 1999 [Text-jd034][JDe4]IPC/JEDEC J-STD-033 Standard for Handling, Packing, Shipping and Use of Moisture/Reflow Sensitive Surface Mount Devices湿度/回流焊敏感标贴器件的处理、包装、运输和使用的标准, May 1999 [Text-jd035][JDe5]EIA/JEP103-A Suggested Product-Documentation Classifications and Disclaimers, (Revision of JEP103) July 1996 [Text-jd036][JDe6]IPC/JEDEC J-STD-020D.1 Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices针对非密封表贴半导体器件的湿度/回流焊敏感度分类和级别, Supersedes IPC/JEDEC J-STD-020D August 2007, March 2008 [Text-jd037]。

JEDEC标准族

JEDEC工业标准环境应力试验[JDa1]JESD22-A100-B Cycled Temperature-Humidity-Bias Life Test 上电温湿度循环寿命试验, (Revision of JESD22-A100-A) April 2000 [Text-jd001][JDa2]JESD22-A101-B Steady State Temperature Humidity Bias Life Test 上电温湿度稳态寿命试验, (Revision of JESD22-A101-A) April 1997 [Text-jd002][JDa3]JESD22-A102-C Accelerated Moisture Resistance -Unbiased Autoclave高加速蒸煮试验, (Revision of JESD22-A102-B) December 2000 [Text-jd003][JDa4]JESD22-A103-A Test Method A103-A High Temperature Storage Life高温储存寿命试验, (Revision of Test Method A103 Previously Published in JESD22-B) July 1989 [Text-jd004] [JDa5]JESD22-A103-B High Temperature Storage Life高温储存寿命试验, (Revision of JESD22-A103-A) August 2001 [Text-jd005][JDa6]JESD22-A104-B Temperature Cycling温度循环, (Revision of JESD22-A104-A) July 2000 (参见更新版本A104C) [Text-jd006][JDa7]EIA/JESD22-A105-B Test Method A105-B Power and Temperature Cycling上电和温度循环, (Revision of Test Method A105-A) February 1996 [Text-jd007][JDa8]JESD22-A106-A Test Method A106-A Thermal Shock热冲击, (Revision of Test Method A106-Previously Published in JESD22-B) April 1995 [Text-jd008][JDa9]JESD22-A107-A Salt Atmosphere盐雾试验, (Revision of Test Method A107-Previously Published in JESD22-B) December 1989 [Text-jd009][JDa10]JESD22-A108-B Temperature, Bias, and Operating Life高温环境条件下的工作寿命试验, (Revision of JESD22-A108-A) December 2000[JDa11]JESD22-A110-B Test Method A110-B Highly-Accelerated Temperature and Humidity Stress Test (HAST)高加速寿命试验, (Revision of Test Method A110-A) February 1999[Text-jd010][JDa12]JESD22-A113-B Preconditioning of Nonhermetic Surface Mount Devices Prior to Reliability Testing非密封表贴器件在可靠性试验以前的预处理, (Revision of Test Method A113-A)March 1999 [Text-jd011][JDa13]JESD22-A118 Accelerated Moisture Resistance - Unbiased HAST不上电的高加速湿气渗透试验, December 2000 [Text-jd012][JDa14]JESD22-B106-B Test Method B106-B Resistance to Soldering Temperature for Through-Hole Mounted Devices插接器件的抗焊接温度试验, (Revision of Test MethodB106-A) February 1999 [Text-jd013][JDa15]EIA/JESD47 Stress-Test-Driven Qualification of Integrated Circuits集成电路施加应力的产品验收试验, July 1995 [Text-jd031][JDa16]JESD22-A104C Temperature Cycling, (Revision of JESD22-A104-B) May 2005 [Text-jd040]电应力和电测试试验[JDb1]JESD22-A114-B Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM)人体模型条件下的静电放电敏感度试验, (Revision of JESD22-A114-A) June 2000 [Text-jd014][JDb2]EIA/JESD22-A115-A Electrostatic Discharge (ESD) Sensitivity Testing Machine Model (MM)机器模型条件下的静电放电敏感度试验, (Revision of EIA/JESD22-A115) October1997 [Text-jd015][JDb3]JESD22-A117 Electrically Erasable Programmable ROM (EEPROM) Program/Erase Endurance and Data Retention Test EEPROM的擦涂和数据保存试验, January 2000[Text-jd016][JDb4]EIA/JESD78 IC Latch-Up Test集成电路器件闩锁试验, March 1997 [Text-jd017][JDb5]JESD22-C101-A Field-Induced Charged-Device Model Test Method forElectrostatic-Discharge-Withstand Thresholds of Microelectronic Components微电子器件在电荷感应模型条件下的抗静电放电试验, (Revision of JESD22-C101) June2000 [Text-jd018]机械应力试验[JDc1]JESD-22-B103-A Test Method B103-A Vibration, Variable Frequency振动和扫频试验(Revision of Test Method B103 Previously Published in JESD22-B) July 1989 [Text-jd019] [JDc2]JESD22-B104-A Test Method B104-A Mechanical Shock机械冲击(Revision of Test Method B104, Previously Published in JEDEC Standard No.22-B) September 1990[Text-jd020][JDc3]EIA/JESD22-B116 Wire Bond Shear Test Method焊线邦定的剪切试验方法, July 1998 [Text-jd021][JDc4]JESD22-B117 BGA Ball Shear BGA焊球的剪切试验, July 2000 [Text-jd022][JDc5]JESD22B113 Board Level Cyclic Bend Test Method for Interconnect Reliability Characterization of Components for Handheld Electronic Products, March 2006 [Text-jd038] [JDc6]JESD22-B111 Board Level Drop Test Method of Components for Handheld Electronic Products, July 2003 [Text-jd039]综合试验与测试[JDd1]JEDEC Standard No.22-A109 Test Method A109 Hermeticity密封性试验, July 1988 [Text-jd023][JDd2]JESD22-A120 Test Method for the Measurement of Moisture Diffusivity and Water Solubility in Organic Materials Used in Integrated Circuits集成电路器件中使用的有机材料水分扩散和水溶性测定试验方法, June 2001 [Text-jd024][JDd3]JESD22-B100-A Physical Dimensions物理尺寸的测量, (Revision of Test Method B100-Previously Published in JESD22-B) April 1990 [Text-jd025][JDd4]JESD22-B101 Test Method B101 External Visual外观检查, (Previously published in JESD22-B) September 1987 [Text-jd026][JDd5]EIA/JESD22-B102-C Solderability Test Method可焊性试验方法, September 1998 [Text-jd027][JDd6]EIA/JESD22-B105-B Test Method B105-B Lead Integrity器件管脚的完整性试验, (Revision of Test Method B105-A) January 1999 [Text-jd028][JDd7]EIA/JESD22-B107-A Test Method B107-A Marking Permanency图标的耐久性试验, (Revision of Test Method B107-Previously Published in JESD22-B) September 1995[Text-jd029][JDd8]JESD22-B108 Coplanarity Test for Surface-Mount Semiconductor Devices表贴半导体器件的共面性试验, November 1991 [Text-jd030]其它[JDe1]JEP113-B Symbol and Labels for Moisture-Sensitive Devices湿度敏感器件的符号和标识, (Revision of JEP113-A) May 1999 [Text-jd032][JDe2]EIA/JEP122 Failure Mechanisms and Models for Silicon Semiconductors Devices硅半导体器件的失效机理和模型, February 1996 [Text-jd033][JDe3]IPC/JEDEC J-STD-020A Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices针对非密封表贴半导体器件的湿度/回流焊敏感度分类和级别, April 1999 [Text-jd034][JDe4]IPC/JEDEC J-STD-033 Standard for Handling, Packing, Shipping and Use of Moisture/Reflow Sensitive Surface Mount Devices湿度/回流焊敏感标贴器件的处理、包装、运输和使用的标准, May 1999 [Text-jd035][JDe5]EIA/JEP103-A Suggested Product-Documentation Classifications and Disclaimers, (Revision of JEP103) July 1996 [Text-jd036][JDe6]IPC/JEDEC J-STD-020D.1 Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices针对非密封表贴半导体器件的湿度/回流焊敏感度分类和级别, Supersedes IPC/JEDEC J-STD-020D August 2007, March 2008 [Text-jd037]。

JESD22简介+目录列表

JESD22标准定义及意义详细如下JESD22-A101orJESD22-A110.3. A101稳态温湿度偏置寿命JESD22-A101-BPublished:Apr-1997STEADY-STATETEMPERATUREHUMIDITYBIASLIFETEST: Thisstandardestablishesadefinedmethodandconditionsf orperformingatemperaturehumiditylifetestwithbiasapplied.Thetestisusedtoevaluatethereliabilityofnonhermeticpackagedsolidstatedevicesinhumidenvironments.Itemployshightem peratureandhumidityconditionstoacceleratethepenetrati onofmoisturethroughexternalprotectivematerialoralongi nterfacesbetweentheexternalprotectivecoatingandcondu ctorsorotherfeatureswhichpassthroughit.Thisrevisionen hancestheabilitytoperformthistestonadevicewhichcanno tbebiasedtoachieveverylowpowerdissipation.JESD22-A101-B发布：1997 年8 月稳态温湿度偏置寿命试验本标准建立了一个定义的方法，用于进行一个施加偏置电压的温湿度寿命试验。

本试验用于评估非气密封装固态器件在潮湿环境下的可靠性。

试验采用高温和高湿条件以加速水汽对外部保护材料或沿着外部保护材料和外部保护涂层，贯通其的导体或其他部件的穿透作用。

JEDEC-22A103C 高温存储

JEDECSTANDARDHigh Temperature Storage Life JESD22-A103C(Revision of JESD22-A103-B)NOVEMBER 2004JEDEC SOLID STATE TECHNOLOGY ASSOCIATIONJEDEC Standard 22-A103CPage 1TEST METHOD A103CHIGH TEMPERATURE STORAGE LIFE(From JEDEC Board Ballot JCB-04-96, formulated under the cognizance of JC-14.1 Subcommittee on Reliability Test Methods for Packaged Devices.)1 ScopeThe test is applicable for evaluation, screening, monitoring, and/or qualification of all solid state devices.High Temperature storage test is typically used to determine the effect of time and temperature, under storage conditions, for thermally activated failure mechanisms of solid state electronic devices, including nonvolatile memory devices (data retention failure mechanisms). During the test elevated temperatures (accelerated test conditions) are used without electrical stress applied. This test may be destructive, depending on Time, Temperature and Packaging (if any).2 Apparatus2.1 High temperature storage chambersThe apparatus required f or this test shall consist of a controlled temperature chamber capable of maintaining the specified temperature over the entire sample population under test.2.2 Electrical test equipmentElectrical equipment capable of performing the appropriate measurements for the devices being tested, including write and verify the required data retention pattern(s) for nonvolatile memories.Test Method A103C(Revision of A103-B)JEDEC Standard 22-A103CPage 2Test Method A103C(Revision of A103-B)3 Procedure3.1 High temperature storage conditionsThe Devices under test shall be subjected to continuous storage at one of the Temperature Conditions of Table 1.Table 1 — High Temperature storage conditionsCondition A: +125 (-0/+10) °CCondition B: +150 (-0/+10) °CCondition C: +175 (-0/+10) °CCondition D: +200 (-0/+10) °CCondition E: +250 (-0/+10) °CCondition F: +300 (-0/+10) °CCondition G: +85 (-0/+10) °CNOTE CAUTION should be exercised when selecting an accelerated test condition since theaccelerated temperature used may exceed the capabilities of the device and materials, thereby inducing failures (overstress) failures that would not occur under normal use conditions.As a minimum the following items should be taken into consideration:1) Melting point of metals present, especially solder. Degradation of metals includes metallurgical interfaces.2) Package degradation. For example Glass Transition Temperature and thermal stability (in air) of any polymeric materials.3) Moisture rating of package (per J-STD-020).4) Temperature limitations of silicon devices. For example: Charge loss in Nonvolatile memories.The Qualification and Reliability monitoring test conditions have typically duration of 1000 hours per condition B of Table 1 (JESD 47). Other conditions and durations may be used as appropriate.The devices may be returned to room ambient conditions for interim electrical measurements.JEDEC Standard 22-A103CPage 33 Procedure (cont’d)3.2 MeasurementsUnless otherwise specified, interim and final electrical test measurements shall be completed within 96 hours after removal of the devices from the specified test conditions. Intermediate measurements are optional unless otherwise specified.The electrical test measurements shall consist of parametric and functional tests specified in the applicable procurement document. For nonvolatile memories, the data specified data retention pattern must be written initially, and then subsequently verified without re-writing.3.3 Failure criteriaA device will be considered a High Temperature Storage failure if parametric limits are exceeded, or if functionality cannot be demonstrated under nominal and worst-case conditions, as specified in the applicable procurement document. For nonvolatile memories, the specified data retention pattern shall be verified before and after storage. A margin test may be used to detect data retention degradation.Mechanical damage, such as cracking, chipping, or breaking of the package, (as defined in test method B101 “External visual”) will be considered a failure, provided that such damage was not induced by fixtures or handling and it is critical to the package performance in the specific application.Cosmetic package defects and degradation of lead finish, or solderability are not considered valid failure criteria for this stress.4 SummaryThe following details shall be specified in the applicable procurement document.a) Electrical test measurements.b) Sample size and number of failures (specify zero if none observed).c) Time and conditions, if other than 1000 hours per condition B.d) Intermediate electrical test measurements, if required.e) Nonvolatile memory data retention pattern (f or appropriate devices)Test Method A103C(Revision of A103-B)JEDEC Standard 22-A103CPage 4Annex A (informative) Difference between JESD22-A103C and JESD22-A103-BThis table briefly describes most of the changes made to entries that appear in this standard, JESD22-A103C, compared to its predecessor, JESD22-A103-B (August 2001). If the change to a concept involves any words added or deleted (excluding deletion of accidentally repeated words), it is included. Some punctuation changes are not included.Page Description of change2 Add Test Condition G + 85°C to Table 1- High Temperature storageconditionsTest Method A103C(Revision of A103-B)。

JESD22-A104D temperatuer cycling

2.4 maximum sample temperature: (Ts(max)): The maximum temperature experienced by the sample(s) as measured by thermocouples, per 3.3.
2.5 minimum sample temperature: (Ts(min)): The minimum temperature experienced by the sample(s) as measured by thermocouples, per 3.3.
This test is conducted to determine the ability of components and solder interconnects to withstand mechanical stresses induced by alternating high- and low-temperature extremes. Permanent changes in electrical and/or physical characteristics can result from these mechanical stresses.
Organizations may obtain permission to reproduce a limited number of copies through entering into a license agreement. For information, contact:
JEDEC Solid State Technology Association 3103 North 10th Street Suite 240 South

22a105 - Power and Temperature Cycling

EIA/JESD22-A105-BPage 1TEST METHOD A105-BPOWER AND TEMPERATURE CYCLING(From Council Ballot JCB-95-85, formulated under the cognizance of JC-14.1 Committee on Reliability Test Methods for Packaged Devices)1 PurposeThe power and temperature cycling test is performed to determine the ability of a device to withstand alternate exposures at high and low temperature extremes with operating biases periodically applied and removed. It is intended to simulate worst case conditions encountered in typical applications.The power and temperature cycling test is considered destructive. It is intended for device qualification.2 ApparatusThe apparatus required for this test shall consist of a controlled temperature chamber capable of producing the specified temperatures within the specified transition times. Sockets or other mounting means shall be provided within the chamber so that reliable electrical contact can be made to the device terminals in the specified circuit configuration. Power supplies and biasing networks shall be capable of maintaining the specified operating conditions throughout the testing period despite normal variations in line voltages or ambient temperatures. The test circuitry should also be designed so that existence of abnormal or failed devices does not alter the specified conditions for other units on test. Care should be taken to avoid possible damage from transient voltage spikes or other conditions that might result in electrical, thermal, or mechanical overstress.3 ProcedureWhen special mounting or heat sinking is required, the details shall be specified in the applicable procurement document.The power should then be applied and suitable checks made to assure that all devices are properly biased. During the test, the power applied to the devices shall be alternately cycled 5 minutes on 5 minutes off unless otherwise specified in the applicable procurement document.The devices shall concurrently be cycled between temperature extremes for the specified number of cycles. The time at the high and low temperature extremes shall be sufficient to allow the total mass of each device under test to reach the specified temperature extremes with no power applied. The low temperature to high temperature transition or reverse sequence is acceptable.Test Method A105-B(Revision of Test Method A105)EIA/JESD22-A105-BPage 2The power and temperature cycling test shall be continuous except when parts are removed from the chamber for interim electrical measurements. If the test is interrupted as a result of power or equipment failure, the test may restart from the point of stoppage.3.1 Test conditionsThe electrical bias circuit shall be specified in the applicable procurement document. The device shall be subjected to the test conditions derived from table 1 as illustrated in figure 1.3.2 PrecautionsSince case and junction temperatures of some devices can be significantly greater than ambient temperature, the circuit should be structured so that the maximum rated case or junction temperature shall not be exceeded. Precautions should be taken to avoid electrical damage and thermal runaway. If LN2 is used, care must be taken to avoid direct exposure of the parts and boards to the LN2.The test setup should be monitored initially and at the conclusion of a test interval to establish that all devices are being stressed to the specified requirements. Deviations must be corrected prior to further cycling to assure the validity of the qualification data.Table 1 —Test conditionsTransition Dwell TimeTime Between at EachTemperature Temperature TemperatureTest Extremes Extreme,Extreme,Condition Degrees C.Max.Min.A-40(+0, -10)20 minutes10 minutesto+85(+10,-0)B-40(+0, -10)30 minutes10 minutesto+ 125(+10, -10)NOTE — Recommended temperature cycles for qualification= 1000.Test Method A105-B(Revision of Test Method A105)EIA/JESD22-A105-BPage 45 SummaryThe following details shall be specified in the applicable procurement document:(a) Special mounting, inapplicable.(b) Test conditions from table 1.(c) Biasing conditions.(d) Power duty cycle if other than specified in 3.(e) Test intervals.(f) Electrical measurements.(g) Sample size and quality level.(h) The number of temperature cycles, if other than 1000.Test Method A105-B(Revision of Test Method A105)。

JESD22-A103D高温存储试验

JESD22-A103D高温存储试验1. 范围该测试适用于评价、筛选、监测或鉴定试验所有固态器件。

高温存储测试经常用来判定在存储条件下时间和温度的影响，针对固体电子器件的热激活失效机理和失效时间分布。

测试器件，使用加速温度应力，不使用电气条件。

该测试也许具有破坏性，根据时间、温度和封装。

2. 参考文档JESD22-B101, External VisualJESD47，Stress-Test-Driven Qualification of Integrated CircuitsJ-STD-020，Joint IPC/JEDEC Standard ,Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface-Mount Devices.3. 设备3.1 高温存储箱在测试期间，能将所有测试样品保持在特定温度的可控温度箱。

3.2 电子测试设备能对器件进行适当测量的电子设备。

4. 流程4.1 高温存储条件被测器件应该在表1的其中一个温度条件下连续存储。

注意当选择一个加速条件时应谨慎行事，因为使用的加速温度可能超过器件和材料的承受能力，从而出现正常使用条件下不会发生的失效。

作为最低限度，应考虑下列项目：1）金属熔点，特别是焊锡。

金属老化包括冶金接口。

2）封装老化。

例如：任何高分子材料的玻璃转化温度Tg和空气中的热稳定性。

3）封装的含水量。

4）硅器件的温度限制。

5）测试条件（温度、时间）应选择覆盖相应失效机理的加速和器件的预期寿命。

鉴定试验和可靠性检测测试条件一般要求时间为表1中条件B 1000小时。

其他条件和时间适当使用。

器件要恢复室温状态或其他定义温度时进行临时测试。

4.2 测量除非另行规定，临时和最终测试测量应该在器件从特定测试条件移除后168小时内完成。

除非另行规定，临时测量为可选。

如果提供了特定技术的验证数据，可以不需要满足时间窗口。

JEDEC工业标准

JEDEC工业标准环境应力试验[JDa1]JESD22-A100-B Cycled Temperature-Humidity-Bias Life Test 上电温湿度循环寿命试验, (Revision of JESD22-A100-A) April 2000 [Text-jd001][JDa2]JESD22-A101-B Steady State Temperature Humidity Bias Life Test 上电温湿度稳态寿命试验, (Revision of JESD22-A101-A) April 1997 [Text-jd002][JDa3]JESD22-A102-C Accelerated Moisture Resistance -Unbiased Autoclave高加速蒸煮试验, (Revision of JESD22-A102-B) December 2000 [Text-jd003][JDa4]JESD22-A103-A Test Method A103-A High Temperature Storage Life高温储存寿命试验, (Revision of Test Method A103 Previously Published in JESD22-B) July 1989 [Text-jd004] [JDa5]JESD22-A103-B High Temperature Storage Life高温储存寿命试验, (Revision of JESD22-A103-A) August 2001 [Text-jd005][JDa6]JESD22-A104-B Temperature Cycling温度循环, (Revision of JESD22-A104-A) July 2000 (参见更新版本A104C) [Text-jd006][JDa7]EIA/JESD22-A105-B Test Method A105-B Power and Temperature Cycling上电和温度循环, (Revision of Test Method A105-A) February 1996 [Text-jd007][JDa8]JESD22-A106-A Test Method A106-A Thermal Shock热冲击, (Revision of Test Method A106-Previously Published in JESD22-B) April 1995 [Text-jd008][JDa9]JESD22-A107-A Salt Atmosphere盐雾试验, (Revision of Test Method A107-Previously Published in JESD22-B) December 1989 [Text-jd009][JDa10]JESD22-A108-B Temperature, Bias, and Operating Life高温环境条件下的工作寿命试验, (Revision of JESD22-A108-A) December 2000[JDa11]JESD22-A110-B Test Method A110-B Highly-Accelerated Temperature and Humidity Stress Test (HAST)高加速寿命试验, (Revision of Test Method A110-A) February 1999 [Text-jd010] [JDa12]JESD22-A113-B Preconditioning of Nonhermetic Surface Mount Devices Prior to Reliability Testing非密封表贴器件在可靠性试验以前的预处理, (Revision of Test Method A113-A)March 1999 [Text-jd011][JDa13]JESD22-A118 Accelerated Moisture Resistance - Unbiased HAST不上电的高加速湿气渗透试验, December 2000 [Text-jd012][JDa14]JESD22-B106-B Test Method B106-B Resistance to Soldering Temperature for Through-Hole Mounted Devices插接器件的抗焊接温度试验, (Revision of Test Method B106-A) February1999 [Text-jd013][JDa15]EIA/JESD47 Stress-Test-Driven Qualification of Integrated Circuits集成电路施加应力的产品验收试验, July 1995 [Text-jd031][JDa1]JESD22-A104C Temperature Cycling, (Revision of JESD22-A104-B) May 2005 [Text-jd040]电应力和电测试试验[JDb1]JESD22-A114-B Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM)人体模型条件下的静电放电敏感度试验, (Revision of JESD22-A114-A) June 2000 [Text-jd014] [JDb2]EIA/JESD22-A115-A Electrostatic Discharge (ESD) Sensitivity Testing Machine Model (MM)机器模型条件下的静电放电敏感度试验, (Revision of EIA/JESD22-A115) October 1997 [Text-jd015][JDb3]JESD22-A117 Electrically Erasable Programmable ROM (EEPROM) Program/Erase Endurance and Data Retention Test EEPROM的擦涂和数据保存试验, January 2000 [Text-jd016][JDb4]EIA/JESD78 IC Latch-Up Test集成电路器件闩锁试验, March 1997 [Text-jd017][JDb5]JESD22-C101-A Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components微电子器件在电荷感应模型条件下的抗静电放电试验, (Revision of JESD22-C101) June 2000 [Text-jd018]机械应力试验[JDc1]JESD-22-B103-A Test Method B103-A Vibration, Variable Frequency振动和扫频试验 (Revision of Test Method B103 Previously Published in JESD22-B) July 1989 [Text-jd019] [JDc2]JESD22-B104-A Test Method B104-A Mechanical Shock机械冲击 (Revision of Test Method B104, Previously Published in JEDEC Standard No.22-B) September 1990 [Text-jd020][JDc3]EIA/JESD22-B116 Wire Bond Shear Test Method焊线邦定的剪切试验方法, July 1998 [Text-jd021][JDc4]JESD22-B117 BGA Ball Shear BGA焊球的剪切试验, July 2000 [Text-jd022][JDc5]JESD22B113 Board Level Cyclic Bend Test Method for Interconnect Reliability Characterization of Components for Handheld Electronic Products, March 2006 [Text-jd038] [JDc6]JESD22-B111 Board Level Drop Test Method of Components for Handheld Electronic Products, July 2003 [Text-jd039]综合试验与测试[JDd1]JEDEC Standard No.22-A109 Test Method A109 Hermeticity密封性试验, July 1988 [Text-jd023][JDd2]JESD22-A120 Test Method for the Measurement of Moisture Diffusivity and Water Solubility in Organic Materials Used in Integrated Circuits集成电路器件中使用的有机材料水分扩散和水溶性测定试验方法, June 2001 [Text-jd024][JDd3]JESD22-B100-A Physical Dimensions物理尺寸的测量, (Revision of Test Method B100-Previously Published in JESD22-B) April 1990 [Text-jd025][JDd4]JESD22-B101 Test Method B101 External Visual外观检查, (Previously published in JESD22-B) September 1987 [Text-jd026][JDd5]EIA/JESD22-B102-C Solderability Test Method可焊性试验方法, September 1998 [Text-jd027] [JDd6]EIA/JESD22-B105-B Test Method B105-B Lead Integrity器件管脚的完整性试验, (Revision of Test Method B105-A) January 1999 [Text-jd028][JDd7]EIA/JESD22-B107-A Test Method B107-A Marking Permanency图标的耐久性试验, (Revision of Test Method B107-Previously Published in JESD22-B) September 1995 [Text-jd029] [JDd8]JESD22-B108 Coplanarity Test for Surface-Mount Semiconductor Devices表贴半导体器件的共面性试验, November 1991 [Text-jd030]其它[JDe1]JEP113-B Symbol and Labels for Moisture-Sensitive Devices湿度敏感器件的符号和标识, (Revision of JEP113-A) May 1999 [Text-jd032][JDe2]EIA/JEP122 Failure Mechanisms and Models for Silicon Semiconductors Devices硅半导体器件的失效机理和模型, February 1996 [Text-jd033][JDe3]IPC/JEDEC J-STD-020A Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices针对非密封表贴半导体器件的湿度/回流焊敏感度分类和级别,April 1999 [Text-jd034][JDe4]IPC/JEDEC J-STD-033 Standard for Handling, Packing, Shipping and Use of Moisture/Reflow Sensitive Surface Mount Devices湿度/回流焊敏感标贴器件的处理、包装、运输和使用的标准, May 1999 [Text-jd035][JDe5]EIA/JEP103-A Suggested Product-Documentation Classifications and Disclaimers, (Revision of JEP103) July 1996 [Text-jd036][JDe6]IPC/JEDEC J-STD-020D.1 Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices针对非密封表贴半导体器件的湿度/回流焊敏感度分类和级别,Supersedes IPC/JEDEC J-STD-020D August 2007, March 2008 [Text-jd037]。

封装的JEDEC标准

封装的JEDEC标准封装级JEDEC标准是一种用于测试和评估半导体器件的标准。

其中包括吸湿敏感度试验、预处理标准、超声扫描判定标准、高压蒸煮试验、温度循环试验、高温储存试验、高温环境条件下的工作寿命试验、恒温恒湿试验、高温加速应力试验、不上电的高加速湿气渗透试验、低温储存试验、管脚疲劳度试验和易焊性试验。

吸湿敏感度试验（MSL）是一种测试半导体器件吸湿敏感性的标准。

JEDEC版本号为J-STD-020D，中文版为非密封型固态芯片。

采用标准为IPC J-STD 020D.1.吸湿敏感度试验的等级从MSL1到MSL6不等。

预处理标准22A113F是一种用于测试半导体器件预处理的标准。

FT+ MSL3+FT3是采用标准。

超声扫描判定标准（J-STD-035D）是一种用于测试半导体器件焊接质量的标准。

采用标准为jstd035声学扫描.pdf。

高压蒸煮试验（PCT）是一种测试半导体器件耐湿性的标准。

JEDEC版本号为JESD22-A102C，采用标准为22A102C-PCT.PDF，测试时间为168小时。

温度循环试验（TCT）是一种测试半导体器件耐温性的标准。

JEDEC版本号为JESD22-A104D，测试时间为500个循环。

温度循环寿命测试（JESD22-A100C）是一种测试半导体器件寿命的标准，采用标准为Cycled XXX-H。

上电温度循环（22A105-B）是一种测试半导体器件温度循环性能的标准，采用标准为22A105-B-_Power_and_Temperature_Cycli。

高温储存试验（HTST）是一种测试半导体器件耐高温性的标准。

JEDEC版本号为JESD22-A103C，测试时间为1000小时。

高温环境条件下的工作寿命试验（JESD22-A108C）是一种测试半导体器件在高温环境下的寿命的标准，测试条件为温度、偏置电压和电流。

恒温恒湿试验（THT）是一种测试半导体器件耐湿性的标准。

JEDEC版本号为JESD22-A101C，测试时间为1000小时。

JESD22标准

C:\Users\ ATC6100\ Desktop\ JEDEC标准\ JESD22-A100D.pdfC:\Users\ATC6100\ Desktop\JESD22-A101D.pdfC:\Users\ATC6100\Desktop\JEDEC标准\JESD22-A102E.pdf C:\Users\ ATC6100\ Desktop\JESD22-1D标准解读.docxC:\Users\ATC6100\Desktop\JESD22-A103E.pdfC:\Users\ATC6100\Desktop\JESD22-A104E.pdfC:\Users\ATC6100\Desktop\JESD22\JEDEC标准\JESD22-A105C_0.pdfC:\Users\ATC6100\Desktop\JESD22\JEDEC标准\JESD22-A106B-01.pdfC:\Users\ATC6100\Desktop\JEDEC标准\JESD22-A107C.pdfC:\Users\ATC6100\Desktop\JEDEC标准\JESD22-A108D.pdfC:\Users\ATC6100\Desktop\JESD22\JEDEC标准\JESD22-A109B.pdf C:\Users\ATC6100\Desktop\JESD22\JEDEC标准\JESD22-A110E.pdf C:\Users\ATC6100\Desktop\JEDEC标准\JESD22-A111B.pdf C:\Users\ATC6100\Desktop\JESD22\JEDEC标准\J-STD-020E.pdf C:\Users\ATC6100\Desktop\JESD22\JEDEC标准\JESD22-A113H.pdf C:\Users\ATC6100\Desktop\C:\Users\ATC6100\Desktop\JEDEC标准\JESD22-A117D.pdf C:\Users\ATC6100\Desktop\JEDEC标准\JESD22-A118B.pdf C:\Users\ATC6100\Desktop\JEDEC标准\JESD22-A119A.pdf C:\Users\ATC6100\Desktop\JESD22-A120B.pdfC:\Users\ATC6100\Desktop\JEDEC标准\JESD22-A121A_R.pdf C:\Users\ATC6100\Desktop\JESD22\JEDEC标准\JESD22-A122A.pdf C:\Users\ATC6100\Desktop\JESD22\JEDEC标准\JESD22-B100B.pdf C:\Users\ATC6100\Desktop\JESD22\JEDEC标准\JESD22-B101C.pdf C:\Users\ATC6100\Desktop\JESD22\JEDEC标准\JESD22-A120B.pdf C:\Users\ATC6100\Desktop\JESD22\JEDEC标准\JESD22-B103B-01.pdf C:\Users\ATC6100\Desktop\JESD22-B110B.pdf C:\Users\ATC6100\Desktop\JESD22-B105E.pdf C:\Users\ATC6100\Desktop\JESD22\JEDEC标准\JESD22-B106E.pdf C:\Users\ATC6100\Desktop\JESD22\JEDEC标准\JESD22-B107D_R.pdf C:\Users\ATC6100\Desktop\JEDEC标准\JESD22-B108B.pdfC:\Users\ ATC6100\ Desktop\ JEDEC标准\JESD22-B109B.pdf C:\Users\ ATC6100\ Desktop\JESD22-B110B.pdfC:\Users\ ATC6100\ Desktop\ JEDEC标准\ JESD22-B111A.pdf C:\Users\ ATC6100\ Desktop\ JEDEC标准\JESD22-B112B.pdfC:\Users\ATC6100\Desktop\ JEDEC标准\JESD22-B113A.pdfC:\Users\ATC6100\Desktop\JEDEC标准\JESD22-B114A.pdfC:\Users\ATC6100\Desktop\C:\Users\ATC6100\Desktop\JESD22-B117B.pdfC:\Users\ ATC6100\ Desktop\C:\Users\ ATC6100\ Desktop\C:\Users\ ATC6100\ Desktop\。

JESD22标准清单

32010现行静电放电敏感性试验esd机器模型mm17a117coct2011现行电可擦除可编程只读存储器eeprom编程擦除耐久性以及数据保持试验18a118amar2011现行加速水汽抵抗性无偏压hast无偏置电压未饱和高压蒸汽19a119nov2004现行低温贮存寿命20a120ajan2008现行用于集成电路的有机材料的水汽扩散率以及水溶解度试验方法21a121ajul2008现行锡及锡合金表面镀层晶须生长的测试方法22a122aug2007现行功率循环23b100bjun2003现行物理尺寸24b101baug2009现行
Nov 2004
现行
低温贮存寿命
20.
A120
A Jan 2008
现行
用于集成电路的有机材料的水汽扩散率以及水溶解度试验方法
21.
A121
A Jul 2008
现行
锡及锡合金表面镀层晶须生长的测试方法
22.
A122
Aug 2007
现行
功率循环
23.
B100
B Jun 2003
现行
物理尺寸
24.
B101
Mar 2011
现行
半导体晶圆以及芯片背面外目检
42.
C100
/
已废止
高温连续性
43.
C101
F Oct 2013
现行
静电放电敏感性试验（ESD）场诱导带电器件模型
JESD22-B
Published:Sep-2000Superseded
SUPERSEDEDBYTHETESTMETHODSINDICATEDBY'JESD22-'
JESD22-A100C
发布：2007年10月

JESD22-A105C-Power and Temperature Cycling

NOTICE
JEDEC standards and publications contain material that has been prepared, reviewed, and approved through the JEDEC Board of Directors level and subsequently reviewed and approved
1 Scope
This test method applies to semiconductor devices that are subjected to temperature excursions and required to power on and off during all temperatures. The power and temperature cycling test is performed to determine the ability of a device to withstand alternate exposures at high and low temperature extremes with operating biases periodically applied and removed. It is intended to simulate worst case conditions encountered in typical applications.
3 Apparatus
The apparatus required for this test shall consist of a controlled temperature chamber capable of producing the specified temperatures within the specified transition times. Sockets or other mounting means shall be provided within the chamber so that reliable electrical contact can be made to the device terminals in the specified circuit configuration. Power supplies and biasing networks shall be capable of maintaining the specified operating conditions throughout the testing period despite normal variations in line voltages or ambient temperatures. The test circuitry should also be designed so that existence of abnormal or failed devices does not alter the specified conditions for other units on test. Care should be taken to avoid possible damage from transient voltage spikes or other conditions that might result in electrical, thermal, or mechanical overstress.