数字电路与系统分析第九章习题答案

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电路分析课后习题第9章答案

L2
b
题9-6图
(ωM ) 2 M2 = jωL1 + = jω ( L1 − ) jωL2 L2 M2 0.0144 则L = L1 − = 0.1 − = 0.064 H L2 0.4
9-7
图所示的变压器电路，原边接电源电压，题9-7图所示的变压器电路，原边接电源电压，副边接负载电阻。求原边电流和通过互感耦合传送到副边回路的功率。载电阻。求原边电流和通过互感耦合传送到副边回路的功率。 • 已知 U S = 10∠0°V R1 = 30Ω ωL1 = 40Ω ωL2 = 120Ω ɺ ɺ R2 = 10Ω ωM = 30Ω R1 I 1 I2
•
•
图所示电路， 9-3 题9-3图所示电路，求电路中的电流
•
I 1 和 I 2 。已知
ω = 100rad / s,U s = 10∠0°V , R1 = 10Ω, L1 = 40mH ,
R2 = 6Ω, L2 = 50mH , M = 4 H .
R1 ɺ I1 ɺ I2 L2
+ _
ɺ US
L1
n 5 = 400 × 5 = 2000Ω
2
得等效初级电路如图所示
U 1 ≈ 20∠0°V
•
ɺ = 20U • ɺ 由U 1 2 U 2 = 1∠0°V
9-12 在题9-12图所示电路中，负载阻抗ZL=(6-j8) 在题9 12图所示电路中，负载阻抗图所示电路中为了与内阻为1k 的信号源匹配，试求变压器的变比的信号源匹配，为了与内阻为 • 为多少？时负载获得的功率。为多少？并求 U S = 2时负载获得的功率。 V
M
R2
题9-3图
列两个网孔方程如下所示：

电路理论基础(陈希有)习题答案第九章

2f C 2 C1
所以
C
答案 9.8 解：(1)根据题意，电路发生谐振时，存在下列关系：
1 / LC 10 4 rad/s I U / R 1A U LI 10V L
解得
R 0.1 L 1 mH C 10 F
品质因数 U 10 Q L 100 U 0.1 （2） I (j C ) 10 10 90 V 10 90 V U C 即有 uC 10 2 cos( t 90)V
不随频率变化得 R1 R2 R ，式（1）简化为
1
LC ( jL 1 jC ) 2 R L C R ( jL 1 jC ) R Z ( j ) 2 R LC R L C R( jL 1 jC ) R ( jL 1 jC ) R 由 Z ( j ) 为实数得： LC LC L 2 R , R2 R R C 故当 R1 R2 L C 时端口电流与端口电压的波形相似，此时 Z ( j ) L C 。答案 9.4 解： RC 并联的等效阻抗 R / jC R Z RC R 1/ jC 1 jRC Z RC /U H ( j ) U 2 1 jL Z RC R 1 2 R jL(1 jRC ) 1 LC jL / R 幅频特性 1 H ( j ) (1 2 LC ) 2 (L / R) 2
| Z ( j ) |
1 0.7
( )
O 1 2 3 4
/ c
45
1 2 3 (b) 4

O
/ c
90
(c)
答案 9.3 解：等效输入阻抗 R j L R jC Z ( j ) 1 2 R1 j L R2 j C

数字电路与逻辑设计李晓辉第9章习题答案

四、习题解答9-1 题9-1图所示为ＴＴＬ与非门构成的微分型单稳态电路，试画出在输入信号I v 作用下，a 、b 、d 、e 、0v 各点波形，求输出0v 的脉冲宽度。

Iv 0v abde0.01Fμ100Ω5.1k Ω题 9-1图解在输入信号I v 作用下，a 、b 、d 、e 、0v 各点波形如图9-8所示。

3.6V3.6V3.6V3.6V3.6V 0.3V 0.3V0.3V 0.3V 0.3V0.3V-1.5V1.4V 1.4V1.4V-1.5Vd ab etwv Iv脉宽3300.7()(100100)0.0110210w t R R C s s --=+=+⨯⨯=⨯9-2 题9-2图所示为ＣＭＯＳ反相器构成的多谐振荡器，试分析其工作原理，画出a 、b 点及O v 的工作波形，写出振荡周期的公式。

Ov C2R 1R ba题9-2图图9-8 题9-1 波形图解题9-2图中电路是教材中CMOS 型多谐振荡器的改进电路，阈值电压V T 不同，振荡频率会改变。

C 两端电压峰值变为2V DD ，从而大大减小了由于阈值电压V T 的离散性导致振荡频率的变化。

1R 接入后保护了CMOS 门输入二极管。

a 、b 点及0v 的工作波形如图9-9所示。

振荡周期计算令1210R R =，有12lnDD T w T V V t R C V +=，222ln DD Tw DD TV V t R C V V -=-，12w w T t t =+ 若1,2T DD V V =则ln 9 2.2T RC RC =≈。

9-3 利用图9-13所示的集成单稳态触发器，要得到输出脉冲宽度等于3ms 的脉冲，外接电容C 应为多少？（假定内部电阻int R Ω（2k ）为微分电阻。

） extC ext R extR intR ext C C CV CC V Ov O v '74121ext/C CCV 2A 1A BIv extC extR int R ext C C CV CCV Ov O v '74121ext/C 2A 1A BIv (b )(a)解因为int 0.7w t R C =，所以33int 310 2.140.70.7210w t C uF uF R -⨯===⨯⨯ 9-4 题9-4图是用两个集成单稳态触发器74121组成的脉冲变换电路，外接电阻和外接电容的参数如图所示。

《数字电路-分析与设计》1--10章习题及解答(部分)_北京理工大学出版社

第五章习题5-1 图题5-1所示为由或非门组成的基本R-S 锁存器。

试分析该电路，即写出它的状态转换表、状态转换方程、状态图、驱动转换表和驱动方程，并画出它的逻辑符号，说明S 、R 是高有效还是低有效。

解：状态转换表：状态转换驱动表5-2 试写出主从式R-S 触发器的状态转换表、状态转换方程、状态图、驱动转换表和驱动方程，注意约束条件。

解：与R-S 锁存器类似，但翻转时刻不同。

5-3 试画出图5.3.1所示D 型锁存器的时序图。

解：G=0时保持，G=1时Q=D 。

图题5-1 或非门组成的基本R-S 锁存器S R状态转换方程：Q n+1Q n+1=S+RQ n状态转换图： S =Q n+1R=Q n+1 状态转换驱动方程：逻辑符号：输入高有效 G D Q图题5-3 D 型锁存器的时序图5-4试用各种描述方法描述D锁存器：状态转换表、状态转换方程、时序图、状态转换驱动表、驱动方程和状态转换图。

5-5锁存器与触发器有何异同？5-6试描述主从式RS触发器，即画出其功能转换表，写出状态方程，画出状态表，画出逻辑符号。

5-7试描述JK、D、T和T'触发器的功能，即画出它们的逻辑符号、状态转换表、状态转换图，时序图，状态转换驱动表，写出它们的状态方程。

5-8试分析图5.7.1(a) 所示电路中虚线内电路Q’与输入之间的关系。

5-9试分析图5.7.1(b)所示电路的功能，并画出其功能表。

5-10试用状态方程法完成下列触发器功能转换：JK→D, D→T, T→D, JK→T, JK→T’, D→T’。

解：JK→D：Q n+1=JQ+KQ，D：Q n+1=D=DQ+DQ。

令两个状态方程相等：D=DQ+DQ =JQ+KQ。

对比Q、Q的系数有：J=D，K=D逻辑图略。

5-11试用驱动表法完成下列触发器功能转换：JK→D, D→T, T→D, JK→T, JK→T’, D→T’。

解：略。

5-12用一个T触发器和一个2-1多路选择器构成一个JK触发器。

数字电路与系统设计课后习题答案

.1.1将下列各式写成按权展开式：（352.6）10=3×102+5×101+2×100+6×10-1（101.101）2=1×22+1×20+1×2-1+1×2-3（54.6）8=5×81+54×80+6×8-1（13A.4F）16=1×162+3×161+10×160+4×16-1+15×16-21.2按十进制0~17的次序，列表填写出相应的二进制、八进制、十六进制数。

解：略1.3二进制数00000000~11111111和0000000000~1111111111分别可以代表多少个数？解：分别代表28=256和210=1024个数。

1.4将下列个数分别转换成十进制数：（1111101000）2，（1750）8，（3E8）16解：（1111101000）2=（1000）10（1750）8=（1000）10（3E8）16=（1000）101.5将下列各数分别转换为二进制数：（210）8，（136）10，（88）16解：结果都为：（10001000）21.6将下列个数分别转换成八进制数：（111111）2，（63）10，（3F）16解：结果都为（77）81.7将下列个数分别转换成十六进制数：（11111111）2，（377）8，（255）10解：结果都为（FF）161.8转换下列各数，要求转换后保持原精度：解：（1.125）10=（1.0010000000）10——小数点后至少取10位（0010 1011 0010）2421BCD=（11111100）2（0110.1010）余3循环BCD码=（1.1110）21.9用下列代码表示（123）10，（1011.01）2：解：（1）8421BCD码：（123）10=（0001 0010 0011）8421BCD（1011.01）2=（11.25）10=（0001 0001.0010 0101）8421BCD（2）余3 BCD码（123）10=（0100 0101 0110）余3BCD（1011.01）2=（11.25）10=（0100 0100.0101 1000）余3BCD1.10已知A=（1011010）2，B=（101111）2，C=（1010100）2，D=（110）2（1）按二进制运算规律求A+B，A-B，C×D，C÷D，（2）将A、B、C、D转换成十进制数后，求A+B，A-B，C×D，C÷D，并将结果与（1）进行比较。

数字逻辑电路王秀敏第9章检测+习题答案081016

检测题 (第9章)一、选择题答案：1. （D ）2. （D ）3. （D ）4. （C ）5. （B ）二、填空题答案：1.单稳态2.截止，高电平3.定时元件R 、C4.微分电路5.输出波形的幅度三、分析计算解：（1）T+CC 22128,33V V V ==⨯=T-CC 11124,33V V V ==⨯=T+T-844V V V V ∆=-=-= （2）根据I V 上升过程中，I CC 23V V >时，O 0V =，I V 下降过程中，I CC 13V V <时，O 1V =画出波形图如图R9.1（3）T+A T-A 114,4222V V V V V V ====⨯=，T+T-422V V V V ∆=-=-=04812v i (V)v O (V)V OH V OLtt图R9.1四、解：以最简单的三个与非门组成的环形振荡器为例，V A V B V C VD2tpd tpd3tpd图R9.2图T9.2，它是由三个反相器组成的环形振荡器，环形振荡器是由奇数个与非门依次首尾相接组成的环形电路，这个电路没有稳定状态，它必然会产生自激振荡。

其振荡频率完全取决于与非门的平均延迟时间。

设初始瞬态为1A =，经过第1个门的延迟在经第2门延迟，最后第3门延迟而反馈到A 点，使0A =，从1A =到0A =总过需要经历D1D2D31t t t T ++=的时间。

同理，使0A =变为1A =也要经历相同的时间过程。

因此振荡周期为126pd T T t ==（在美级门的平均延迟时间相等的情况下），故每级门的平均传输延迟时间为D /6t T =，从示波器荧光屏上读出波形周期T ，算出D t 的值。

各门输出波形如图图T9.2所示。

基于上述原理，将任何3≥的奇数个反相器首尾连接成环形电路都能产生自激振荡，振荡周期2pd T nt =。

五、答：（1）图P9.3（a ）构成对称式多谐振荡器，图T9.3(b)构成石英晶体多谐振荡器（2）T9.3（a ）的振荡周期频率为OH IK OH TH 12,nV V T Rfcl f V V T-≈=-，T （或f ）与R 、C及OH V 、OL V 、T V 有关，图T9.3(b)的振荡频率f 非常稳定，仅由晶体的谐振荡频率决定。

《数字电路-分析与设计》第九章习题及解答(部分) 北京理工大学出版社

第九章习题9-1 答：所有D i均为1时电流最大，为I VREFMAX=V REF(1/23+1/22+1/21+1/20) /R = (1+2+4+8)V REF/23R=15V REF/8R=1.875V REF/R=1.875mA；P VREFMAX= V REFI VREFMAX=5*1.875=9.375mW。

9-2解：ΔV=V REF/16=0.3125V; V omax=15ΔV=4.6875V；当D3 D2 D1 D0=1001时，V o=9ΔV=2.8125V。

9-3答案：V O=V REF/28∑D i2i，i=0~7。

9-4解：T型：I VREF= V REF/3R∑D i；P VREF= V REF2/3R∑D i；P VREFMAX=n*V REF2/3R；P VREFMIN=0；P VREF与位数、输入数据有关。

倒T型：I VREF=V REF/R，P VREF=V REF2/R，与输入数据D无关。

9-5解：由2n>= V omax/ΔV=5V/1mV=5000，得n=13；由V omax=(2n-1)V REF/2n，得V REF=213V omax/(213 -1) ≈V omax=5V；如果取n=13，V REF=5V，则：ΔV=V REF/213=5/8192= 0.0006<1mV，V omax=(213-1)V REF/213=8191*5/8192=4.99938V，满足设计要求。

9-6解：该图中电阻网络作为反馈电阻，故增益表达式为：A=-2n/Σ(2i×D i)V①当D9-D0=1000000000时，A V=-210/29=-2；②当增益为5时，令A V=-2n/Σ(2i×D i)=-213/X，得X=-213/-5=1638.4，取X=(1638)10=(0011001100110)2实际增益为A V=-213/1638=5.0019-7解：1. 74LS194构成m序列发生器，其输出状态Q3Q2Q1Q0的顺序为0001，0010，0100，1001，0011，0110，1101，1010，0101，1011，0111，1111，1110，1100，1000；2.AD7520构成4位DAC，其输出为VO=-V REF/24∑D i*2i=-5/16∑D i*2i=-0.3125∑D i*2i；3. 由于Q0接在D9上，所以DAC输入数据D9D8D7D6的顺序为Q0Q1Q2Q3的顺序：1000，0100，0010，1001，1100，0110，1011， 0101，1010，1101，1110，1111，0111，0011，0001；4．所以波形图为：9-8解：此题与9-5类似：n=13，V REF=5V；实际分辨率为0.61mV。

数字电路及系统设计课后习题答案

1.1 将下列各式写成按权展开式：2 1 0 -1(352.6 ) io=3X 102+5X 101+2X 10°+6X 10(101.101 ) 2=1 X 22+1x 2O+1X 2-1+1x 2-3( 54.6 )8=5X 81+54X 80+6X 8-12 1 0 -1 -2(13A.4F)16=1X162+3X161+10X 160+4X16-1+15X16-21.2 按十进制0~17 的次序，列表填写出相应的二进制、八进制、十六进制数。

解：略1.3 二进制数00000000~11111111 和0000000000~1111111111 分别可以代表多少个数？解：分别代表28=256和210=1024个数。

1.4 将下列个数分别转换成十进制数：1111101000)2，(1750) 8，( 3E8)16解：( 1111101000)2=( 1000)10( 1750)8= ( 1000)10(3E8)16=(1000)101.5 将下列各数分别转换为二进制数： ( 210)8，( 136)10，( 88)16解：结果都为：（10001000）21.6 将下列个数分别转换成八进制数：（111111）2，（63）10，（3F）16解：结果都为（77）81.7 将下列个数分别转换成十六进制数：（11111111）2，（377）8 ，（255）10 解：结果都为（FF）161.8 转换下列各数，要求转换后保持原精度：解：（1.125 ）10=（1.0010000000 ）10 ——小数点后至少取10 位（0010 1011 0010 ）2421BCD= （11111100）2（0110.1010 ）余 3 循环BC[M= （ 1.1110 ） 21.9 用下列代码表示（1 23）10，（1011.01 ）2：解：（1） 8421BCD码：（123 ）10= （0001 0010 0011 ）8421BCD（1011.01 ）2=（11.25）10=（0001 0001.0010 0101 ）8421BCD(2) 余3 BCD码(123) io= (0100 0101 0110 )余3BCD(1011.01 ) 2=( 11.25 ) 10=(0100 0100.0101 1000 )余3BcD1.10 已知A=(1011010) 2，B=( 101111) 2，c=(1010100) 2，D=( 110) 2(1)按二进制运算规律求A+B, A-B, C X D, C一D,(2)将A B、C D转换成十进制数后，求A+B, A-B, C X D,C- D,并将结果与(1)进行比较。

数字集成电路设计与系统分析答案

懂得1、Please illustrate the meaning of its voltage transfer characteristic to a logic gate, and describe the static behaviors showed in the voltage transfer characteristic curves.The electrical function of a gate is best expressed by its voltage transfer characteristic (VTC),which plots the output voltage as a function of the input voltage Vout=f(Vin).The high and low nominal voltage Voh and Vol;The gate or switching threshold voltage Vm,that is define as Vm=f(Vm)(The gate threshold voltage presents the midpoint of the switching characteristics,which is obtained when the output of a gate is short circuited to the input);The high and low input voltage Vih and Vil are defined by the point where the gain (=dVout/dVin)of the VTC equals -12、Please draw the voltage transfer characteristic curve of the inverter and label the static operation points in the VTC.3、Please describe the definition of noise margin and its physical significance(物理意义), then draw the figure of definition of noise margins.The noise margins represent the levels of noise that can be sustained(所允许的) when gates are cascaded. A measure of the sensitivity of a gate to noise is given by the noise margins NML(noise margin low) and NMH(noise margin high), which quantize the size of the legal “0” and “1”, respectively, and set a fixed maximum threshold on the noise value4、Please describe the meaning of the regenerative property and the conditions of a gate with regenerative property.A gate with regenerative property ensures that a disturbed signal converges back to a nominal voltage level after passing through a number of logical stages. The VTC should have a transient region (or undefined region) with a gain greater than 1 in absolute value, bordered by the two legal zones, where the gain should be less than 1 in absolute value5、What are the definitions of the fan-out and fan-in properties?The number that can be driven is termed the fan-out of circuit, that denotes the number of load gates N that are connected to the output of the driving gate. The fan-in of a gate is defined as the number of independent input nodes to the gate.6、How to describe the performance of a digital IC? Please illustrate the parameters used to characterize the transient performance of a logic family, and draw the associated figure of the definition of these parP ropagation delay time and rise/fall time can be used to characterize the transient performance of a logic family .Propagation delay time of a gate expresses the delay experienced by a signal when passing through a gate,which represent how quickly the gate responds to the changes at its inputs.Rise/fall time express how fast a signal transits between the different levels. Propagation delay time is defined as the period between the 50%transition points of the input and output signals.Rise/fall time is defined as the period between the 10% and 90% points of the total voltage transition at the output waveforms.1、Illustrate the basic structure and simple operation principle of MOS transistor.Four terminals:source, drain, gate, body; Vertical Structure: gate electrode, insulator, semiconductor substrate; Horizontal Structure: source region, channel region, drain region2、Illustrate the basic function of each terminal of MOS device, and describe the general terminal connections of NMOS and PMOS transistor, respectively.The source and the drain are the electrodes conducting the current. The gate electrode is thecontrolling terminal. The function of the body is secondaryIn NMOS devices, the source is defined as the n+ region which has a lower potential(电势) than the other n+ region, the drain. The source is the terminal with the higher potential in PMOS devices, The body is generally connected to a DC supply that is identical for all devices of the same type (GND for NMOS, VDD for PMOS).3、What does the transition (or input) characteristic of MOS transistor mean? And what conclusions we can find from the characteristic curve?It describes the relationship between the gate-source voltage and the drain-source current with the certain drain-source voltage .When the gate-source voltage is less than the threshold voltage, the conducting current is zero, that is, the NMOS transistor is in cutoff operation. When is larger than, the NMOS transistor is on.4、What does the current-voltage (or output) characteristic of MOS transistor mean? And what conclusions we can find from the I-V characteristic curve?.It describes the relationship between the drain-source voltage and the drain-source current with a certain gate-source voltageVgs > Vt , 0<VDS <VGS -VT : Linear modeThe inversion layer forms a continuous current path between the source and the drain.A drain current proportional to Vds will flow from the drain to the source through the conducting channel. The channel region acts as a voltage-controlled linear resister.5、Describe the operation modes of NMOS and PMOS transistors respectively, and define the corresponding ideal current equations.1、Explain the channel-length modulation, sub-threshold conduction, short-channel effect and narrow-channel effect. And illustrate their corresponding chief impacts on the device.This simple current equation prescribes a linear drain-bias dependence for the current in MOS transistors, determined by the empirical model parameter λ, called the channel-length modulation coefficientOne typical condition, which is due to the two-dimensional nature of channel current flow, is the sub-threshold conduction in small-geometry MOS transistors.As a working definition, a MOS transistor is called a short-channel device if its channel length is on the same order of magnitude as the depletion region thicknesses of the source and drain junctions.The short-channel effects that arise in this case are attributed to two physical phenomena: the limitations imposed on electron drift characteristics in the channel; the modification of the threshold voltage due to the shortening channel lengthMOS transistor that have channel widths on the same order of magnitude as the maxium depletion region thickness are defined as narrow channel devices.For MOSFET with small channel widths,the actual threshold voltage increases as a result of this extra depletion charge of the fringe depletion region.This fact is called narrow channel effect.2、Describe the three main components of the load capacitanceCL, when a logic gate is driving other fan-out gates. And sketch the capacitance model of NMOS transistor.Gate capacitances (of other inputs connected to out)Diffusion(or junction) capacitances (of drain/source regions)Routing capacitances (output to other inputs)1,Describe the basic structure and operation of a static CMOS inverter. Then draw theassociated transistor schematicThis structure consists of an enhancement-type NMOS transistor and an enhancement-type PMOS transistor, operating in complementary mode. So this configuration is called Complementary MOS (CMOS). The gate terminals of the PMOS and NMOS transistors are connected to form the inverter input. The drain terminals of the PMOS and NMOS transistors are connected to form the inverter output. The source and the substrate of the NMOS transistor are connected to the ground, while the source and body of PMOS transistor are connected to VDD The circuit topology is complementary push-pull in the sense that: For high input the NMOS transistor drives (pulls down) the output node while the PMOS transistor acts as the load, and for low input the PMOS transistor drives (pulls up) the output node while the NMOS transistor acts as the load.When the input is at VDD: The NMOS is on (conducting) while the PMOS is off (cut-off). A direct path exists between Vout and the ground node, resulting in a steady-state value of 0V at the output. When the input is at ground:The NMOS is off while the PMOS is on. A direct path exists between VDD and Vout, yielding a high output voltage (equal to VDD).Static CMOS logic:structure:The static CMOS style is really an extension of the static CMOS inverter to multiple inputs. A logic function in static CMOS must be implemented in both NMOS and PMOS transistors. It is the combination of the pull-up network(PUN) and the pull-down network(PDN). Each input always connects to PUN and PDN simultaneously. The function of the PUN is to provide a connection between the output and VDD anytime the output of the logic gate is meant to be 1 (based on the inputs). The function of the PDN is to connect the output to VSS when the output of the logic gate is meant to be 0.Opreation: The pull-down net should be “on” when the pull-up net is “off” and vice versa. For any given input combination, the output is connected either to VDD or to ground via a low-resistance path. A DC current path between the VDD and ground is not established for any of the input combinations. With the complementary nature of NMOS and PMOS, the pull-up or the pull-down is “on” alternately to implement the logic operation.Discuss the main problems for high fan-in static CMOS gates and the associated techniques for fast complex gates.tpHL = 0.69 Reqn(C1+2C2+3C3+4CL); Propagation delay deteriorates(恶化) rapidly as a function of fan-in quadratically in the worst case, Gates with a fan-in greater than 4 become excessively slow and must be avoided.tPLH increases linearly due to the linearly increasing value of the diffusion capacitance;tPHL increase quadratically due to the simultaneous increase the resistance and internal capacitance in serial part.Transistor sizing: as long as fan-out capacitance dominatesProgressive transistor sizing: This approach reduces the dominant resistance, while keeping the increase in capacitance within boundsTransfer gate:Configuration:The source and drain nodes serve as inputs and outputs, while the gate node serves as the control input, the body node is connected to the power/ground Operation: For NMOS transfer gate,it turns on while the gate control terminal goes high, and the input signal will be delivered to the output node; it turns off while the gate control terminal goes low, and the output node will be impedance.CMOS transmission gate:Configuration: The CMOS transmission gate consists of one NMOS and one PMOS transistor, with the source and drain connected in parallel; The gate voltages appliedto these two transistors are also set to be complementary signals. The substrate terminal of the NMOS transistor is connected to ground and the substrate terminal of the PMOS transistor is connected to Vdd.Operation: If the control signal C is logic-high (equal to Vdd), then both transistors are turned on and provide a low-resistance current path between the input and output nodes. If the control signal C is logic-low, then both transistors will be off, and the path between the input and output nodes will be in the high-impedance state. The weakness of one device is overcome by the strength of the other device, whether the output is transmitting a high or low value. This is a clear advantage of the CMOS transfer gate over the single transistor counterpart.DCVLS:Operation: Assume now that, for a given set of inputs, PDN1 conducts while PDN2 does not, and that Out and out are initially high and low, respectively. Turning on PDN1: Causes Out to be pulled down (below VDD−|VTP |); Out is in a high impedance state, as M2 and PDN2 are both turned off. At the point M2 turns on and starts charging out非to VDD — eventually turning off M1; This in turn enables Out to discharge all the way to GND.XOR/XNOR: When the signals A and B have the same values, there is one conducting path either AB or A非B非; Then the output F is pulled down;At the same time, the other pull-down paths connected to the F非are both turned off. When F is pulled down below VDD−|VTP |, M2 t urns on and starts charging F非to VDD —eventually turning off M1 and pulling down F to Gnd. When the signals A and B have the different values, there is one conducting path either AB非or A非B; Then the output F非is pulled down; At the same time, the other pull-down paths connected to the F are both turned off. When F非is pulled down below VDD−|VTP |, M1 turns on and starts charging F to VDD —eventually turning off M2 and pulling down F非to Gnd.Precharge-Evaluate dynamic CMOS:Operation: Precharge (when the clock signal Φ= 0)：The PMOS precharge transistor MP is conducting while the complementary NMOS transistor MN is off. The output load capacitance is precharged to VDD by MP, then VOH=VDD；The input voltages have no influence yet upon the output level since the complementary NMOS transistor MN is off. Evaluate (when the clock signal Φ=1)：The precharge transistor MP turns off while the NMOS evaluate transistor MN turns on. The output node voltage may now remain at the logic-high level or drop to a logic low, depending on the input voltage levels: If the input signals create a conducting path between the output node and the ground, PDN is on, and the output capacitance will discharge toward VOL=0;Otherwise, when PDN is off, the output voltage remains at VOH= VDD.Domino dynamic CMOS logic:When Φ=0, during precharge: The output of the n-type dynamic gate is charged up to VDD, and the output of the inverter is set to 0. When Φ=1, during evaluation: The dynamic gate conditionally discharges, and there are two possibilities: The output node of the dynamic CMOS stage is either discharged to a low level through the NMOS circuitry (1 to 0 transition), or it remains high. Consequently, the inverter output voltage can also make at most one transition during the evaluation phase, from 0 to 1.TSPC dynamic CMOS logic:Configuration:If one constrains a NORA stage to have only n-precharge gates, and not static gates, then a p-channel transistor can be eliminated from the clocked latch; The dynamic circuit technique to be presented in that it uses only one-phase clock signal, so no clock skew problem exists. The NORA design style can be simplified so that a single clock is sufficient. For the doubled n-C2MOS latch, when φ= 1, the latch is in the transparent evaluate mode and corresponds to 2 cascaded inverters (non-inverting); For the doubled n-C2MOS latch, when φ= 0, both inverters are disabled (hold mode) -- only the pull-up network is still active.Pipelined NORA dynamic CMOS system:Configuration: Consists of an np-CMOS logic sequence and a clocked CMOS output buffer; A pipelined system can be constructed by simply cascading alternating φ-section and φ -section, meaning that evaluation occurs during active φ and φ respectively;Operation:φ=0, during hold mode :N block performs the precharge operation and pulls node Out1 up to VDD through the p-type device Mp1, while p block performs the discharge operation and pulls the node Out2 down to zero through the n-type device Mn2; The clocked CMOS latch will not be in operation and the previous output voltage will be stored on the output load capacitor CL. φ=1, during evaluate mode:All cascaded NMOS and PMOS blocks evaluate output levels one after the other, and then the signal Out2 will be inversed to the output node by the clocked CMOS latch in operation;Operation Mode: Evaluate―Hold: All logic stages perform the precharge-discharge operation when the clock is high, and all stages evaluate output levels when the clock is low. Therefore, wewill call this circuit a section, meaning that evaluation occurs during active .Clocked CMOS dynamic circuit:Basic Structure:A pair of PMOS and NMOS transistors controlled by the complementary clock signals are cascaded in the pullup and pulldown paths of the static CMOS gate, respectively, then a CMOS logic gate can be synchronized with a clock. Operation: φ=1, during evaluation mode：The transistors Mp1 and Mp2 are both turned on, then this gate can evaluate normally as a CMOS inverter to generate the logic output In非; φ=0 , during hold mode: Both transistors Mp1 and Mp2 are off, decoupling the output from the input. The CMOS circuit cannot conduct and evaluate, then the output Q retains its previous value stored on the output capacitor CL.Sequential logic:Virtually all useful systems require storage of state information, leading to another class of circuits called sequential logic circuits. In these circuits, the output not only depends upon the current values of the inputs, but also upon preceding output values. In other words, a sequential circuit remembers some of the past history of the system; A sequential circuit consists of a combinational circuit and a memory block in the feedback loop.Combination logic:In all logic circuits described so far, the output is directly related to the input. Typically, there are no feedback loops between the output and the input in these circuits (also classified as non-regenerative circuits), so the outputs are always a logical combination of the inputs. As a class, these circuits are known as combinational logic circuits. Combinational logic circuits, described earlier, have the property that the output of a logic block is only a function of the current input values, assuming that enough time has elapsed for the logic gates to settle. Static storage:preserve state as long as the power is on;are built using positive feedback or regeneration with an intentional connection between the output and the input;useful when updates are infrequent (clock gating)Dynamic storage:store state on parasitic capacitors;only hold state for short periods of time (milliseconds);require periodic refresh to annihilate charge leakage;usually simpler, so higher speed and lower power;useful in datapath circuits that require high performance levels and are periodically clockedLatch: level sensitive circuit that passes inputs to Q when the clock is high (or low);input sampledon the falling edge of the clock is held stable when clock is low (or high)Register or Flip-flops (edge-triggered): edge sensitive circuits that only sample the inputs on a clock transitionpositive edge-triggered: 0- 1negative edge-triggered: 1 -0built using latches (e.g., master-slave flip-flops)。

14-15成都信息工程大学电路分析第9章+作业参考答案(1)

第9章电路频率响应P9-14 电路如图P9-14所示，利用叠加定理求电压)(0t u 。

补充问题：求6Ω电阻的吸收的有功功率图P9-14 图1 解：1）直流源10V 单独作用，如图1所示，Vu 1001=， 6Ω电阻吸收的功率：W P 7.1661021==2）V t )3cos(12单独作用，如图2所示，Ω6j ∙Ω4j图2 图3V j j j j j j j j U︒-∠=︒∠⨯-+-⨯+-+-⨯=∙57.26268.100212)4(6)4(66)4(6)4(602,所以：V t t u )57.263cos(68.10)(02︒-=6Ω电阻的端电压，如图2所示：VUU ︒∠=︒-∠-︒∠=-︒∠=∙∙87.62237.557.26268.1002120212026Ω电阻吸收的功率：W P 4.26237.522=⎪⎪⎭⎫ ⎝⎛=3）V t )2sin(4单独作用，如图3所示，()V j j j j U︒-∠=-⨯︒-∠⨯+-+-=∙43.63247.21690244161616103，所以：V t t u )43.632cos(47.21)(03︒-=6Ω电阻吸收的功率：W P 4.386247.2123=⎪⎪⎭⎫⎝⎛=4）时域叠加：V t t t u t u u t u )43.632cos(47.21)57.263cos(68.1010)()()(0302010︒-+︒-+=++= 5）6Ω电阻吸收的有功功率：W P P P P 5.574.384.27.16321=++=++=P9-6 设计一个RLC 串联电路，使得其在谐振频率rad/s 500=ω时阻抗为10Ω，品质因数为80，求其带宽。

解：设RLC 串联电路如图1所示：.图1由题意可知，Ω=10R ，又品质因数H RL RL Q 16501080808000=⨯==⇒==ωω同理品质因数uF RC RCQ 25105080180118000=⨯⨯==⇒==ωω带宽：srad QBW /625.080500===ωP9-20 求图P9-20所示电路的谐振频率0ω，品质因数Q 以及带宽B 。

《数字电路与系统设计》课后答案

abcff121??1101?1000101000??13bca000111100?1111111fab1bca000111100?111111fa?b214411试将24译码器扩展成416译码器a3a1?en?y3a24?y02a2译码器?y1?y0?en?en?en?enaa1241a1242a1243a12441a0a0a0a0a0?y0?y1?y2?y3?y0?y1?y2?y3?y0?y1?y2?y3?y0?y1?y2?y3?y?y?y?y?y?y?y?y?y?y?y?y01234567?y?y1011?y?y141589121315412试用74138设计一个多输出组合网络它的输入是4位二进制码abcd输出为
= A·BD·BC
(3) 画逻辑电路，如下图所示：
D
B
F
C
A
题4.4图
4.10电话室对3种电话编码控制，按紧急次序排列优先权高低是：火警电话、急救电话、普通电话，分别编码为11，10，01。试设计该编码电路。
解：设火警为A，急救为B，普通为C，列真值表为：
A
B
C
F
1
F2
1
1பைடு நூலகம்
1
0
1
1
0
0
0
1
0
1
0
0
0
= Y0Y4Y8Y12
F2(A,B,C,D)
m(0,1,2)
= m0m1m2
= Y0Y1Y2
F3(A,B,C,D)
m(8,9,10,11)
= m8m9m10m11
= Y8Y9Y10Y11
F4(A,B,C,D)m0
=Y0
数字电路与系统设计课后答案
4.1分析图P4.1电路的逻辑功能

数字逻辑电路与系统设计习题答案

第1章习题及解答1.1 将下列二进制数转换为等值的十进制数。

（1）（11011）2 （2）（10010111）2（3）（1101101）2 （4）（11111111）2（5）（0.1001）2（6）（0.0111）2（7）（11.001）2（8）（101011.11001）2题1.1 解：（1）（11011）2 =（27）10 （2）（10010111）2 =（151）10（3）（1101101）2 =（109）10 （4）（11111111）2 =（255）10（5）（0.1001）2 =（0.5625）10（6）（0.0111）2 =（0.4375）10（7）（11.001）2=（3.125）10（8）（101011.11001）2 =（43.78125）10 1.3 将下列二进制数转换为等值的十六进制数和八进制数。

（1）（1010111）2 （2）（110111011）2（3）（10110.011010）2 （4）（101100.110011）2题1.3 解：（1）（1010111）2 =（57）16 =（127）8（2）（110011010）2 =（19A）16 =（632）8（3）（10110.111010）2 =（16.E8）16 =（26.72）8（4）（101100.01100001）2 =（2C.61）16 =（54.302）81.5 将下列十进制数表示为8421BCD码。

（1）（43）10 （2）（95.12）10（3）（67.58）10 （4）（932.1）10题1.5 解：（1）（43）10 =（01000011）8421BCD（2）（95.12）10 =（10010101.00010010）8421BCD（3）（67.58）10 =（01100111.01011000）8421BCD（4）（932.1）10 =（100100110010.0001）8421BCD1.7 将下列有符号的十进制数表示成补码形式的有符号二进制数。

《电路与模拟电子技术》第二版第九章习题解答

第九章信号的运算与处理电路9.1 求题9.1图所示电路中的01u 、02u 和o u 。

解：A 1构成反相比例电路I I L u u u u 10101010001-=-=-=A 2构成同相比例电路I I u u u 11)101001(02=+=u 0=u 01-u 02=-21u I9.2 试证明题9.2图所示电路的输出电压))(1(1221I I o u u R R u -+=。

解：A 1构成同相比例电路11201)1(I u R R u +=由虚短可得 u 2-=u I2，由虚断可得122201R u u R u u -=--将前二式代入上式可得))(1(12210I I u u R R u -+=9.3 求题9.3图所示运算电路的输入输出关系。

题9.1图题9.2图解A 1构成反相比例电路，A 2则构成反相加法电路 11011010100I I u u u -=-=212010210)5101010(I I I u u u u u -=+-=9.4 求题9.4图所示运算电路的输出电压。

设Ω==k R R 1021，Ω==k R R F 203。

解：由虚断可得321132323223323322I I I I I I u u R R u R u R R R R u R u u +=++=++=+32011011u u R R u R u R u I FI F +=++=-由虚短u +=u - 得u 0=-2u I1+2u I2+u I39.5 用二个运放设计一个实现321853I I I o u u u u +-=的运算电路，画出电路图，标出各电阻值，电阻的阻值限在（1~500）Ωk 之间。

解：运算可通过二级反相加法电路实现，如图所示)(331101R u R u R u I I F +-=，题9.3图u u u 题9.4图R R R R01212212021232414234()I F F F F F F I I I u u R R R R R u R u u u R R R R R R R =-+=-+与要求比较得522=R R F ，取R F2=100k Ω，R 2=20k Ω又取R 4=R F2=100k Ω，则311=R R F ，831=R R F取R F1=240 k Ω，则R 1=80 k Ω，R 3=30 k Ω。

《通信电路与系统》第九章部分习题参考答案概况

电工电子教学实验中心《通信电路与系统》部分习题参考答案第九章数字基带传输系统9-3.解:已知二进制符号序列及波形为:0 1 1 0 1 0 0 0 0 1 0 0 0 1 1 0 0 0 0 0 1 0对应的 AMI 码序列及波形为:0 +1 -1 0 +1 0 0 0 0 -1 0 0 0 +1 -1 0 0 0 0 0 +1 0对应的 HDB 3码序列及波形为:0 +1 -1 0 +1 0 0 0 +V -1 0 0 0 +1 -1 0 0 0 -V 0 +1 0【注】 :AMI 码和 HDB 3码都有三个电平,为三元码。

上述画出的 AMI码波形只给了一种可能,其反极性的波形也是正确的。

HDB 3码中的符号 ±V 和 ±B 只代表作用的不同, 其电平和波形与 ±1码的一样。

9-5.解:(1对于任意基本码形 g (t的单极性二进制序列,其功率谱为( ( 1( ( 1( (22s m s s s mf f mf G p f f G p p f f P −−+−=∑∞−∞=δ 其中, 21( (2/2/sin 2 (2s s s s T t A t g fT fT AT f G −=↔⎟⎟⎠⎞⎜⎜⎝⎛=ππ, s s T f /1=, p =1/2,当, 2s T t <, 则有(2/2/sin 162/2/sin 16 (4242s m s s s mf f m m A fT fT T A f P −+=∑∞−∞=δππππ (2双边功率谱中有 f s 离散谱(m = -1和 +1 ,接收端提取位同步信号,其功率分量为π42A 。

【注】 :对于基本波形为矩形的 NRZ 基带码序列,当传 1和传 0等概率(1/2时,无论是单极性还是双极性码, 功率谱中都没有位同步 f s 离散谱及其谐波分量, 仅仅是单极性码有直流分量。

本题中的基本波形为三角形,基本属于 RZ 码,应该含有位同步f s 离散谱分量及 f s 的奇次谐波分量。

数字电路与系统设计课后习题答案

将下列各式写成按权展开式：（）10=3×102+5×101+2×100+6×10-1（）2=1×22+1×20+1×2-1+1×2-3（）8=5×81+54×80+6×8-1（）16=1×162+3×161+10×160+4×16-1+15×16-2按十进制0~17的次序，列表填写出相应的二进制、八进制、十六进制数。

解：略二进制数00000000~和0000000000~11分别可以代表多少个数解：分别代表28=256和210=1024个数。

将下列个数分别转换成十进制数：（00）2，（1750）8，（3E8）16解：（00）2=（1000）10（1750）8=（1000）10（3E8）16=（1000）10将下列各数分别转换为二进制数：（210）8，（136）10，（88）16解：结果都为：（）2将下列个数分别转换成八进制数：（111111）2，（63）10，（3F）16解：结果都为（77）8将下列个数分别转换成十六进制数：（）2，（377）8，（255）10解：结果都为（FF）16转换下列各数，要求转换后保持原精度：解：（）10=（）10——小数点后至少取10位（0010 1011 0010）2421BCD=（）2（）余3循环BCD码=（）2用下列代码表示（123）10，（）2：解：（1）8421BCD码：（123）10=（0001 0010 0011）8421BCD（）2=（）10=（0001 0101）8421BCD（2）余3 BCD码（123）10=（0100 0101 0110）余3BCD（）2=（）10=（0100 1000）余3BCD已知A=（1011010）2，B=（101111）2，C=（1010100）2，D=（110）2（1）按二进制运算规律求A+B，A-B，C×D，C÷D，（2）将A、B、C、D转换成十进制数后，求A+B，A-B，C×D，C÷D，并将结果与（1）进行比较。

数字电路与系统设计课后习题答案之欧阳语创编

1.1将下列各式写成按权展开式：（352.6）10=3×102+5×101+2×100+6×10-1 （101.101）2=1×22+1×20+1×2-1+1×2-3（54.6）8=5×81+54×80+6×8-1（13A.4F）16=1×162+3×161+10×160+4×16-1+15×16-21.2按十进制0~17的次序，列表填写出相应的二进制、八进制、十六进制数。

解：略1.3二进制数00000000~11111111和0000000000~1111111111分别可以代表多少个数？解：分别代表28=256和210=1024个数。

1.4 将下列个数分别转换成十进制数：（1111101000）2，（1750）8，（3E8）16解：（1111101000）2=（1000）10（1750）8=（1000）10（3E8）16=（1000）101.5将下列各数分别转换为二进制数：（210）8，（136）10，（88）16解：结果都为：（10001000）21.6 将下列个数分别转换成八进制数：（111111）2，（63）10，（3F）16解：结果都为（77）81.7 将下列个数分别转换成十六进制数：（11111111）2，（377）8，（255）10解：结果都为（FF）161.8 转换下列各数，要求转换后保持原精度：解：（1.125）10=（1.0010000000）10——小数点后至少取10位（0010 1011 0010）2421BCD=（11111100）2（0110.1010）余3循环BCD码=（1.1110）21.9 用下列代码表示（123）10，（1011.01）2：解：（1）8421BCD码：（123）10=（0001 0010 0011）8421BCD（1011.01）2=（11.25）10=（0001 0001.0010 0101）8421BCD（2）余3 BCD码（123）10=（0100 0101 0110）余3BCD（1011.01）2=（11.25）10=（0100 0100.0101 1000）余3BCD1.10 已知A=（1011010）2，B=（101111）2，C=（1010100）2，D=（110）2（1）按二进制运算规律求A+B，A-B，C×D，C÷D，（2）将A、B、C、D转换成十进制数后，求A+B，A-B，C×D，C÷D，并将结果与（1）进行比较。

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