eda设计4位数码管显示
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module seg_714(
input clk,
input rst,
output reg clkout_5ms,
output reg clkout_1s,
output reg [7:0] cadp,
output reg [3:0] AN
);
reg [31:0] cnt_5ms;
reg [31:0] cnt_1s;
reg [1:0] x;
always @ (posedge clk or posedge rst)
if(rst==1) cnt_5ms<=0;
else if(cnt_5ms==499999) cnt_5ms<=0;
else cnt_5ms<=cnt_5ms+1;
always @ (posedge clk or posedge rst)
if(rst==1) clkout_5ms<=0;
else if(cnt_5ms<=249999) clkout_5ms<=0;
else clkout_5ms<=1;
always @ (posedge clkout_5ms or posedge rst)
if(rst==1) x<=0;
else x<=x+1;
always @ (x or rst)
if(rst==1) AN=4'b1111;
else if(clkout_1s==0) AN=4'b1111;
else
case(x)
0 : begin AN=4'b0111; cadp = 8'b00000011; end
1 : begin AN=4'b1011; cadp = 8'b11000001; end
2 : begin AN=4'b1101; cadp = 8'b00100101; end
3 : begin AN=4'b1110; cadp = 8'b10011010; end default cadp=0;
endcase
always @ (posedge clk or posedge rst)
if(rst==1) cnt_1s<=0;
else if(cnt_1s==99999999) cnt_1s<=0;
else cnt_1s<=cnt_1s+1;
always @ (posedge clk or posedge rst)
if(rst==1) clkout_1s<=0;
else if(cnt_1s<=49999999) clkout_1s<=0;
else clkout_1s<=1;
endmodule