2011年数字集成电路设计期末考试试卷_中国科技大学

Digital Integrated Circuits

Final Exam, Fall 2011

School of Software Engineering

University of Science and Technology of China

(19:00pm–21:00 pm November24th, 2011)

Name:Student ID:Score:

1. Which of the following two circuits is better in terms of speed? Why?(5 points)

2. Describe at least two methods to reduce power dissipation of digital integrated circuits. (5 points)

3. What are the advantage and disadvantage of using the transistor M r in the figure below? (4 points)

4.Reconstruct the following circuit logically to avoid glitches.Describe at least one other method to avoid glitches. (5 points)

5.Sketch a transistor-level circuit for a 6-Transistor SRAM. Describe how to size transistors to ensure writing reliability and reading stability.What is the purpose of having PMOS transistors? (10 points)

6.Consider a 24-bit, 6 stage carry-bypass adder with the following delays: t setup=4, t carry=1, t sum=4, t bypass

=2.

b) Consider the setup delay and carry propagation of the2nd, 3rd, and 4th stages.It is not on the critical path and can be made slower without affecting performance. If each stage is allowed to handle a different number of bits,how many bits would you assign to each of the first four stages to minimize the delay from inputs to the carry output

for the first16 bits of the adder?(6 points)

c)Given the condition that the number of bits in the last two stages is 8, how many bits would you assign to each of the last two stages to minimize the delay of the adder?

(4 points)

7. Assume the registers in the following figure are edge triggered with t clk-q, max= 4ns, t clk-q, min = 2ns, t setup = 1ns, and t hold= 1ns:

CLK

(a) What is the maximum operating frequency of this system if there is no skew and jitter? (8 points)

(b) What is the maximum random clock skew that this system can tolerate? (6 points)

8.Throughout this problem assume that the drain capacitance in the following figure,

C D = 0.

a) Assuming P(A=0）= P(B=0) = P(C=0) = P(D=0)=0.5, what are the activity factors (i.e.,α0→1) at each of the nodes n0– n3?(6 points)

b) Assuming the circuit operates with a supply voltage V DD and a clock frequency f, what is the total dynamic power consumed by this circuit as a function of Cin, C1, C2, and C L (as labeled above)? Note that you should include the power dissipated by driving the A, B, C, and D inputs.(7 points)

c)Using the method of logical effort, calculate the delay from A to n2 ((in units of t inv) as a function of Cin, C1, C2, and CL.(5 points)

9. Sketch a transistor-level circuit for a master-slave positive edge-triggered register which consists of transmission gates. Express t setup and t hold in terms of t pd_inv(the delay of an inverter) and t pd_tx (the delay of a transmission gate). (7 points）

10.What is the logic function performed by this circuit? What is the purpose of having the transistor M1? (4 points)

11. Assume that the threshold voltage of NMOS transistors V TN = 0.4V. Calculate the voltage of nodes A and B respectively? (4 points)

12.Consider the figure below. During the precharge phase, the output node is precharged to V DD. Assume that all inputs are set to zeros during precharge, and that the capacitance C a is discharged。Assume further that input B remains at 0 during evaluation, while input A makes a0—>1transition，turning M a on.Calculate the