单片机外文翻译--STC89C52处理芯片

外文资料翻译

STC89C52 processi ng chip

Prime features:

With MCS - 51 SCM product compatibility, 8K bytes in the system programmable Flash memory, 1000 times CaXie cycle, the static operation: 0Hz ~ 33Hz, triple encryption program memory, 32 programmed I/O port, three 16 timer/counter, the eight uninterrupted dual-career UART serial passage, low power consumption, leisure and fall after fall electric power mode can be awakened and continuous watchdog timer and double-number poin ter, power ide ntifier. Efficacy: characteristics

STC89C52 is one kind of low power consumption, high CMOS8 bit micro-co ntroller, 8K in system programmable Flash memory. Use high-de nsity nonv olatile storage tech no logy, and in dustrial 80C51 product in structi on and pin fully compatible. The Flash memory chips allows programs in the system, also suitable for programmable conventional programming. In a single chip, have clever 8 bits CPU and on li ne system programmable Flash, in crease STC89C52 for many embedded control system to provide high vigorous application and useful solutions. STC89C52 has following standard efficacy: 8k byte Flash RAM, 256 bytes, 32 I/O port, the watchdog timer, two, three pointer numerical 16 timer/counter, a 6 vector level 2 continuous structure, the serial port, working within crystals and horological circuit. In addition, 0Hz AT89S52 can drop to the static logic operation, support two software can choose power saving mode. Idle mode, the CPU to stop working, and allows the RAM, timer/c oun ters, serial, continu ous to work. Protectio n asa na patter n, RAM content is survival, vibrators frozen, SCM, until all the work under a continuous or hardware reset. 8-bit microcontrollers 8K bytes in the system programmable Flash AT89S52 devices.

Mouth: P0 P0 mouth is a two-way ope n drain I/O. As export, each can drive eight TTL logic level. For P0 port to write "1", foot as the high impeda nee in

put.

When access to exter nal programs and nu merical memory, also known as

low P0 mouth eight address/nu merical reuse. In this mode, with the in tern al P0 resistor.

In the flash when programming, also used for P0 mouth; absorb in struct ion bytes In the process, the output comma nd byte calibrati on. When the program requires external, calibration on pull-up resistors.

Mouth: P1 mouth P1 is an internal resistance of the eight two-way I/O buffers can drive, P1 output four TTL logic level. To write "1" P1 port, the internal resista nce to port, can push as in put mouth. Whe n used as in put, exter nal and in ternal foot because of low resista nce, will output curre nt (IIL).

In addition, P1.0 and P1.2 respectively timer/counter 2 external counting in put (P1.0 / T2) and whe n the trigger editor/co un ter P1.1 in put (2), specific

T2EX/are shown below. In programming and calibration, flash P1 mouth absorb eight address low byte.

Efficacy: the foot.

P1.0 T2 (timer/co un ter T2 external coun ti ng in put), clock output

P1.1 T2EX (timer/co un ter T2 capture/overloaded triggered sig nals and directi on con trol),

P1.5 MOSI (with) on li ne system program ming,

P1.6 MISO (with) on li ne system program ming,

P1.7 SCK (with) on li ne system program ming,

Mouth: P2 P2 mouth is an internal resista nce of the eight two-way I/O buffers and P2 output can drive four TTL logic level. To write "1" P2 port, the internal resista nce to port, can push as in put mouth. When used as in put, exter nal and in ternal foot because of low resista nce, will output curre nt (IIL).

In the exter nal program memory access or use 16bit exter nal nu merical memory address read (for example MOVX execution DPTR @), P2 mouth send out high 8 address. In this application, P2 mouth on the internal use strong pull send 1. In using 8-bit address (such as MOVX @ Rl) access to external numerical memory, P2 mouth output P2 latches content. In programming and calibration, flash P2 mouth also absorb high eight address byte and some con trol sig nal.