单片机_英文参考文献

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单片机设计体参考文献

单片机设计体参考文献

单片机设计体参考文献介绍单片机(Microcontroller)是一种集成了微处理器核心、存储器、输入/输出端口以及其他功能模块的集成电路芯片。

它具有低功耗、体积小、易于控制和使用的特点,广泛应用于各种电子设备中。

在单片机的设计过程中,参考文献的重要性不言而喻。

好的参考文献可以为设计者提供丰富的知识和经验,指导设计过程并解决问题。

本文将就单片机设计方面的参考文献进行全面、详细、完整和深入的探讨,为读者提供有关单片机设计的一些建议和指导。

选择合适的参考文献选择合适的参考文献是进行单片机设计的第一步。

以下是一些有关单片机设计的经典参考书目,供读者参考。

1. 《The 8051 Microcontroller and Embedded Systems Using Assembly and C》•作者:Muhammad Ali Mazidi, Janice Gillispie Mazidi, Rolin D.McKinlay•出版年份:2007年•内容简介:本书全面介绍了8051单片机的架构、编程和应用。

书中涵盖了从基本知识到高级应用的内容,适合初学者和有一定经验的读者。

2. 《ARM Cortex-M3和Cortex-M4单片机高级编程》•作者:Yifeng Zhu•出版年份:2013年•内容简介:本书详细介绍了ARM Cortex-M3和Cortex-M4单片机的架构、指令集和编程技巧。

作者通过丰富的实例和案例,深入浅出地讲解了单片机的高级编程技术。

3. 《单片机与嵌入式系统应用》•作者:Ryan Heffernan, Muhammad Ali Mazidi, Danny Causey•出版年份:2012年•内容简介:本书介绍了单片机和嵌入式系统的基本概念和原理,包括硬件和软件的设计和开发。

书中还提供了大量的实例和项目,帮助读者将理论知识应用到实际项目中。

单片机设计流程在进行单片机设计时,遵循一定的设计流程是非常重要的。

单片机英文文献资料及翻译

单片机英文文献资料及翻译

单片机英文文献资料及翻译单片机(英文:Microcontroller)Microcontroller is a small computer on a single integrated circuit that contains a processor core, memory, and programmable input/output peripherals. Microcontrollers are designed for embedded applications, in contrast to the microprocessors used in personal computers or other general purpose applications.A microcontroller's processor core is typically a small, low-power computer dedicated to controlling the operation of the device in which it is embedded. It is often designed to provide efficient and reliable control of simple and repetitive tasks, such as switching on and off lights, or monitoring temperature or pressure sensors.MEMORYMicrocontrollers typically have a limited amount of memory, divided into program memory and data memory. The program memory is where the software that controls the device is stored, and is often a type of Read-Only Memory (ROM). The data memory, on the other hand, is used to store data that is used by the program, and is often volatile, meaning that it loses its contents when power is removed.INPUT/OUTPUTMicrocontrollers typically have a number of programmable input/output (I/O) pins that can be used to interface with external sensors, switches, actuators, and other devices. These pins can be programmed to perform specific functions,such as reading a sensor value, controlling a motor, or generating a signal. Many microcontrollers also support communication protocols like serial, parallel, and USB, allowing them to interface with other devices, including other microcontrollers, computers, and smartphones.APPLICATIONSMicrocontrollers are widely used in a variety of applications, including:- Home automation systems- Automotive electronics- Medical devices- Industrial control systems- Consumer electronics- RoboticsCONCLUSIONIn conclusion, microcontrollers are powerful and versatile devices that have become an essential component in many embedded systems. With their small size, low power consumption, and high level of integration, microcontrollers offer an effective and cost-efficient solution for controlling a wide range of devices and applications.。

单片机英文文献及翻译)

单片机英文文献及翻译)

Validation and Testing of Design Hardening for Single Event Effects Using the 8051 MicrocontrollerAbstractWith the dearth of dedicated radiation hardened foundries, new and novel techniques are being developed for hardening designs using non-dedicated foundry services. In this paper, we will discuss the implications of validating these methods for the single event effects (SEE) in the space environment. Topics include the types of tests that are required and the design coverage (i.e., design libraries: do they need validating for each application?). Finally, an 8051 microcontroller core from NASA Institute of Advanced Microelectronics (IAμE) CMOS Ultra Low Power Radiation Tolerant (CULPRiT) design is evaluated for SEE mitigative techniques against two commercial 8051 devices.Index TermsSingle Event Effects, Hardened-By-Design, microcontroller, radiation effects.I. INTRODUCTIONNASA constantly strives to provide the best capture of science while operating in a space radiation environment using a minimum of resources [1,2]. With a relatively limited selection of radiation-hardened microelectronic devices that are often two or more generations of performance behind commercialstate-ofthe-art technologies, NASA’s performance of this task is quite challenging. One method of alleviating this is by the use of commercial foundry alternatives with no or minimally invasive design techniques for hardening. This is often called hardened-by-design (HBD).Building custom-type HBD devices using design libraries and automated design tools may provide NASA the solution it needs to meet stringent science performance specifications in a timely,cost-effective, and reliable manner.However, one question still exists: traditional radiation-hardened devices have lot and/or wafer radiation qualification tests performed; what types of tests are required for HBD validation?II. TESTING HBD DEVICES CONSIDERATIONSTest methodologies in the United States exist to qualify individual devices through standards and organizations such as ASTM, JEDEC, and MIL-STD- 883. Typically, TID (Co-60) and SEE (heavy ion and/or proton) are required for device validation. So what is unique to HBD devices?As opposed to a “regular” commercial-off-the-shelf (COTS) device or application specific integrated circuit (ASIC) where no hardening has been performed, one needs to determine how validated is the design library as opposed to determining the device hardness. That is, by using test chips, can we “qualify” a future device using the same library?Consider if Vendor A has designed a new HBD library portable to foundries B and C. A test chip is designed, tested, and deemed acceptable. Nine months later a NASA flight project enters the mix by designing a new device using Vendor A’s library. Does this device require complete radiation qualification testing? To answer this, other questions must be asked.How complete was the test chip? Was there sufficient statistical coverage of all library elements to validate each cell? If the new NASA design uses a partially or insufficiently characterized portion of the design library, full testing might be required. Of course, if part of the HBD was relying on inherent radiation hardness of a process, some of the tests (like SEL in the earlier example) may be waived.Other considerations include speed of operation and operating voltage. For example, if the test chip was tested statically for SEE at a power supply voltage of 3.3V, is the data applicable to a 100 MHz operating frequency at 2.5V? Dynamic considerations (i.e., nonstatic operation) include the propagated effects of Single Event Transients (SETs). These can be a greater concern at higher frequencies.The point of the considerations is that the design library must be known, the coverage used during testing is known, the test application must be thoroughly understood and the characteristics of the foundry must be known. If all these are applicable or have been validated by the test chip, then no testing may be necessary. A task within NASA’s Electronic Parts and Packaging (NEPP) Program was performed to explore these types of considerations.III. HBD TECHNOLOGY EVALUATION USING THE 8051 MICROCONTROLLERWith their increasing capabilities and lower power consumption, microcontrollers are increasingly being used in NASA and DOD system designs. There are existing NASA and DoD programs that are doing technology development to provide HBD. Microcontrollers are one such vehicle that is being investigated to quantify the radiation hardness improvement. Examples of these programs are the 8051 microcontroller being developed by Mission Research Corporation (MRC) and the IAμE (the focus of this study). As these HBD technologies become available, validation of the technology, in the natural space radiation environment, for NASA’s use in spaceflight systems is required.The 8051 microcontroller is an industry standard architecture that has broad acceptance, wide-ranging applications and development tools available. There are numerous commercial vendors that supply this controller or have it integrated into some type of system-on-a-chip structure. Both MRC and IAμE chose this device to demonstrate two distinctly different technologies for hardening. The MRC example of this is to use temporal latches that require specific timing to ensure that single event effects are minimized. The IAμE technology uses ultra low power, and layout and architecture HBD design rules to achieve their results. These are fundamentally different than the approach by Aeroflex-United Technologies Microelectronics Center (UTMC), the commercial vendor of a radiation–hardened 8051, that built their 8051 microcontroller using radiationhardened processes. This broad range of technology within one device structure makes the 8051an ideal vehicle for performing this technology evaluation.The objective of this work is the technology evaluation of the CULPRiT process [3] from IAμE. The process has been baselined against two other processes, the standard 8051 commercial device from Intel and a version using state-of-the-art processing from Dallas Semiconductor. By performing this side-by-side comparison, the cost benefit, performance, and reliability trade study can be done.In the performance of the technology evaluation, this task developed hardware and software for testing microcontrollers. A thorough process was done to optimize the test process to obtain as complete an evaluation as possible. This included taking advantage of the available hardware and writing software that exercised the microcontroller such that all substructures of the processor were evaluated. This process is also leading to a more complete understanding of how to test complex structures, such as microcontrollers, and how to more efficiently test these structures in the future.IV. TEST DEVICESThree devices were used in this test evaluation. The first is the NASA CULPRiT device, which is the primary device to be evaluated. The other two devices are two versions of a commercial 8051, manufactured by Intel and Dallas Semiconductor, respectively.The Intel devices are the ROMless, CMOS version of the classic 8052 MCS-51 microcontroller. They are rated for operation at +5V, over a temperature range of 0 to 70 °C and at a clock speeds of 3.5 MHz to 24 MHz. They are manufactured in Intel’s P629.0 CHMOS III-E process.The Dallas Semiconductor devices are similar in that they are ROMless 8052 microcontrollers, but they are enhanced in various ways. They are rated for operation from 4.25 to 5.5 Volts over 0 to 70 °C at clock speeds up to 25 MHz. They have a second full serial port built in, seven additional interrupts, a watchdog timer, a power fail reset, dual data pointers and variable speed peripheral access. In addition, the core is redesigned so that the machine cycle is shortened for most instructions, resulting in an effective processing ability that is roughly 2.5 times greater (faster) than the standard 8052 device. None of these features, other than those inherent in the device operation, were utilized in order to maximize the similarity between the Dallas and Intel test codes.The CULPRiT technology device is a version of the MSC-51 family compatible C8051 HDL core licensed from the Ultra Low Power (ULP) process foundry. The CULPRiT technology C8051 device is designed to operate at a supply voltage of 500 mV and includes an on-chip input/output signal level-shifting interface with conventional higher voltage parts. The CULPRiT C8051 device requires two separate supply voltages; the 500 mV and the desired interface voltage. The CULPRiT C8051 is ROMless and is intended to be instruction set compatible with the MSC-51 family.V. TEST HARDWAREThe 8051 Device Under Test (DUT) was tested as a component of a functional computer. Aside from DUT itself, the other componentsof the DUT computer were removed from the immediate area of the irradiation beam.A small card (one per DUT package type) with a unique hard-wired identifier byte contained the DUT, its crystal, and bypass capacitors (and voltage level shifters for the CULPRiT DUTs). This "DUT Board" was connected to the "Main Board" by a short 60-conductor ribbon cable. The Main Board had all other components required to complete the DUT Computer, including some which nominally are not necessary in some designs (such as external RAM, external ROM and address latch). The DUT Computer and the Test Control Computer were connected via a serial cable and communications were established between the two by the Controller (that runs custom designed serial interface software). This Controller software allowed for commanding of the DUT, downloading DUT Code to the DUT, and real-time error collection from the DUT during and post irradiation. A 1 Hz signal source provided an external watchdog timing signal to the DUT, whose watchdog output was monitored via an oscilloscope. The power supply was monitored to provide indication of latchup.VI. TEST SOFTWAREThe 8051 test software concept is straightforward. It was designed to be a modular series of small test programs each exercising a specific part of the DUT. Since each test was stand alone, they were loaded independently of each other for execution on the DUT. This ensured that only the desired portion of the 8051 DUT was exercised during the test and helped pinpoint location of errors that occur during testing. All test programs resided on the controller PC until loaded via the serial interface to the DUT computer. In this way, individual tests could have been modified at any time without the necessity of burning PROMs. Additional tests could have also been developed and added without impacting the overall test design. The only permanent code, which was resident on the DUT, was the boot code and serial code loader routines that established communications between the controller PC and the DUT.All test programs implemented:• An external Universal Asynchronous Receive and Transmit device (UART) for transmission of error information and communication to controller computer.• An external real-time clock for data error tag.•A watchdog routine designed to provide visual verification of 8051 health and restart test code if necessary.• A "foul-up" routine to reset program counter if it wanders out of code space.• An external telemetry data storage memory to provide backup of data in the event of an interruption in data transmission.The brief description of each of the software tests used is given below. It should be noted that for each test, the returned telemetry (including time tag) was sent to both the test controller and the telemetry memory, giving the highest reliability that all data is captured.Interrupt –This test used 4 of 6 available interrupt vectors (Serial, External, Timer0 Overflow, and Timer1 Overflow) to trigger routines that sequentially modified a value in the accumulator which was periodically compared to a known value. Unexpected values were transmitted with register information.Logic –This test performed a series of logic and math computations and provided three types of error identifications: 1) addition/subtraction, 2) logic and 3) multiplication/division. All miscompares of computations and expected results were transmitted with other relevant register information.Memory – This test loaded internal data memory at locations D:0x20 through D:0xff (or D:0x20 through D:0x080 for the CULPRiT DUT), indirectly, with an 0x55 pattern. Compares were performed continuously and miscompares were corrected while error information and register values were transmitted.Program Counter -The program counter was used to continuously fetch constants at various offsets in the code. Constants were compared with known values and miscompares were transmitted along with relevant register information. Registers – This test loaded each of four (0,1,2,3) banks of general-purpose registers with either 0xAA (for banks 0 and 2) or 0x55 (for banks 1 and 3). The pattern was alternated in order to test the Program Status Word (PSW) special function register, which controls general-purpose register bank selection. General-purpose register banks were then compared with their expected values. All miscompares were corrected and error information was transmitted.Special Function Registers (SFR) – This test used learned static values of 12 out 21 available SFRs and then constantly compared the learned value with the current one. Miscompares were reloaded with learned value and error information was transmitted.Stack – This test performed arithmetic by pushing and popping operands on the stack. Unexpected results were attributed to errors on the stack or to the stack pointer itself and were transmitted with relevant register information.VII. TEST METHODOLOGYThe DUT Computer booted by executing the instruction code located at address 0x0000. Initially, the device at this location was an EPROM previously loaded with "Boot/Serial Loader" code. This code initialized the DUT Computer and interface through a serial connection to the controlling computer, the "Test Controller". The DUT Computer downloaded Test Code and put it into Program Code RAM (located on the Main Board of the DUT Computer). It then activated a circuit which simultaneously performed two functions: held the DUT reset line active for some time (~10 ms); and, remapped the Test Code residing in the Program Code RAM to locate it to address 0x0000 (the EPROM will no longer be accessible in the DUT Computer's memory space). Upon awaking from the reset, the DUT computer again booted by executing the instruction code at address 0x0000, except this time that code was not be the Boot/Serial Loader code but the Test Code.The Test Control Computer always retained the ability to force the reset/remap function, regardless of the DUT Computer's functionality. Thus, if the test ran without a Single Event Functional Interrupt (SEFI) either the DUT Computer itselfor the Test Controller could have terminated the test and allowed the post-test functions to be executed. If a SEFI occurred, the Test Controller forced a reboot into Boot/Serial Loader code and then executed the post-test functions. During any test of the DUT, the DUT exercised a portion of its functionality (e.g., Register operations or Internal RAM check, or Timer operations) at the highest utilization possible, while making a minimal periodic report to the Test Control Computer to convey that the DUT Computer was still functional. If this reportceased, the Test Controller knew that a SEFI had occurred. This periodic data was called "telemetry". If the DUT encountered an error that was not interrupting the functionality (e.g., a data register miscompare) it sent a more lengthy report through the serial port describing that error, and continued with the test.VIII.DISCUSSIONA. Single Event LatchupThe main argument for why latchup is not an issue for the CULPRiT devices is that the operating voltage of 0.5 volts should be below the holding voltage required for latchup to occur. In addition to this, the cell library used also incorporates the heavy dual guard-barring scheme [4]. This scheme has been demonstrated multiple times to be very effective in rendering CMOS circuits completely immune to SEL up to test limits of 120 MeV-cm2/mg. This is true in circuits operating at 5, 3.3, and 2.5 Volts, as well as the 0.5 Volt CULPRiT circuits. In one case, a 5 Volt circuit fabricated on noncircuits wafers even exhibited such SEL immunity.B. Single Event UpsetThe primary structure of the storage unit used in the CULPRiT devices is the Single Event Resistant Topology (SERT) [5]. Given the SERT cell topology and a single upset node assumption, it is expected that the SERT cell will be completely immune to SEUs occurring internal to the memory cell itself. Obviously there are other things going on. The CULPRiT 8051 results reported here are quite similar to some resultsobtained with a CULPRiT CCSDS lossless compression chip (USES) [6]. The CULPRiT USES was synthesized using exactly the same tools and library as the CULPRiT 8051.With the CULPRiT USES, the SEU cross section data [7] was taken as a function of frequency at two LET values, 37.6 and 58.5 MeV-cm2/mg. In both cases the data fit well to a linear model where cross section is proportional to clock. In the LET 37.6 case, the zero frequency intercept occurred essentially at the zero cross section point, indicating that virtually all of these SEUs are captured SETs from the combinational logic. The LET 58.5 data indicated that the SET (frequency dependent) component is sitting on top of a "dc-bias" component –presumably a second upset mechanism is occurring internal to the SERT cells only at a second, higher LET threshold.The SET mitigation scheme used in the CULPRiT devices is based on the SERT cell's fault tolerant input property when redundant input data is provided to separate storage nodes. The idea is that the redundant input data is provided through a total duplication of combinational logic (referred to as “dual rail design”) such that a simple SET on one rail cannot produce an upset. Therefore, some other upset mechanism must be happening. It is possible that a single particle strike is placing an SET on both halves of the logic streams, allowing an SET to produce an upset. Care was taken to separate the dual sensitive nodes in the SERT cell layouts but the automated place-and-route of the combinatorial logic paths may have placed dual sensitive nodes close enough.At this point, the theory for the CULPRiT SEU response is that at about an LET of 20, the energy deposition is sufficiently wide enough (and in the right locations) to produce an SET in both halves of the combinatorial logic streams. Increasing LET allows for more regions to be sensitive to this effect, yielding a larger cross section. Further, the second SEU mechanism that starts at an LET of about 40-60 has to do with when the charge collection disturbance cloud gets large enough to effectively upset multiples of the redundant storage nodes within the SERT cell itself. In this 0.35 μm library, the node separation is several microns. However, since it takes less charge to upset a node operating at 0.5 Volts, with transistors having effective thresholds around 70 mV, this is likely the effect being observed. Also the fact that the per-bit memory upset cross section for the CULPRiT devices and the commercial technologies are approximately equal, as shown in Figure 9, indicates that the cell itself has become sensitive to upset.IX. SUMMARYA detailed comparison of the SEE sensitivity of a HBD technology (CULPRiT) utilizing the 8051 microcontroller as a test vehicle has been completed. This paper discusses the test methodology used and presents a comparison of the commercial versus CULPRiT technologies based on the data taken. The CULPRiT devices consistently show significantly higher threshold LETs and an immunity to latchup. In all but the memory test at the highest LETs, the cross section curves for all upset events is one to two orders of magnitude lower than the commercial devices. Additionally, theory is presented, based on the CULPRiT technology, that explain these results.This paper also demonstrates the test methodology for quantifying the level of hardness designed into a HBD technology. By using the HBD technology in a real-world device structure (i.e., not just a test chip), and comparing results to equivalent commercial devices, one can have confidence in the level of hardness that would be available from that HBD technology in any circuit application.ACKNOWLEDGEMENTSThe authors of this paper would like to acknowledge the sponsors of this work. These are the NASA Electronic Parts and Packaging Program (NEPP), NASA Flight Programs, and the Defense Threat Reduction Agency (DTRA).。

单片机英文参考文献

单片机英文参考文献

单片机英文参考文献篇一:5-单片机+外文文献+英文文献+外文翻译中英对照AT89C51的介绍(原文出处:http:///resource/)描述AT89C51是一个低电压,高性能CMOS8位单片机带有4K字节的可反复擦写的程序存储器(PENROM)。

和128字节的存取数据存储器(RAM),这种器件采用ATMEL公司的高密度、不容易丢失存储技术生产,并且能够与MCS-51系列的单片机兼容。

片内含有8位中央处理器和闪烁存储单元,有较强的功能的AT89C51单片机能够被应用到控制领域中。

功能特性AT89C51提供以下的功能标准:4K字节闪烁存储器,128字节随机存取数据存储器,32个I/O口,2个16位定时/计数器,1个5向量两级中断结构,1个串行通信口,片内震荡器和时钟电路。

另外,AT89C51还可以进行0HZ的静态逻辑操作,并支持两种软件的节电模式。

闲散方式停止中央处理器的工作,能够允许随机存取数据存储器、定时/计数器、串行通信口及中断系统继续工作。

掉电方式保存随机存取数据存储器中的内容,但震荡器停止工作并禁止其它所有部件的工作直到下一个复位。

引脚描述VCC:电源电压 GND:地 P0口:P0口是一组8位漏极开路双向I/O口,即地址/数据总线复用口。

作为输出口时,每一个管脚都能够驱动8个TTL电路。

当“1”被写入P0口时,每个管脚都能够作为高阻抗输入端。

P0口还能够在访问外部数据存储器或程序存储器时,转换地址和数据总线复用,并在这时激活内部的上拉电阻。

P0口在闪烁编程时,P0口接收指令,在程序校验时,输出指令,需要接电阻。

沈阳航空工业学院电子工程系毕业设计(外文翻译)P1口:P1口一个带内部上拉电阻的8位双向I/O口,P1的输出缓冲级可驱动4个TTL电路。

对端口写“1”,通过内部的电阻把端口拉到高电平,此时可作为输入口。

因为内部有电阻,某个引脚被外部信号拉低时输出一个电流。

闪烁编程时和程序校验时,P1口接收低8位地址。

单片机的外文文献及中文翻译

单片机的外文文献及中文翻译

SCM is an integrated circuit chip,is the use of large scale integrated circuit technology to a data processing capability of CPU CPU random access memory RAM,read-only memory ROM,a variety of I / O port and interrupt system, timers / timer functions (which may also include display driver circuitry,pulse width modulation circuit,analog multiplexer,A / D converter circuit)integrated into a silicon constitute a small and complete computer systems.SCM is also known as micro—controller (Microcontroller), because it is the first to be used in industrial control。

Only a single chip by the CPU chip developed from a dedicated processor。

The first design is by a large number of peripherals and CPU on a chip in the computer system, smaller, more easily integrated into a complex and demanding on the volume control device which。

单片机英文文献

单片机英文文献

单片机英文文献Introduction of Programmable controllersFrom a simple heritage, these remarkable systems have evolved to not only replace electromechanical devices, but to solve an ever-increasing array of control problems in both process and nonprocess industries. By all indications, these microprocessor powered giants will continue to break new ground in the automated factory into the 1990s.HISTORYIn the 1960s, electromechanical devices were the order of the dayass far as control was concerned. These devices, commonly known as relays, were being used by the thousands to control many sequential-type manufacturing processes and stand-along machines. Many of these relays were in use in the transportation industry, more specifically, the automotive industry. These relays used hundreds of wires and their interconnections to effect a control solution. The performance of a relay was basically reliable - at least as a single device. But the common applications for relay panels called for 300 to 500 or more relays, and the reliability and maintenance issues associated with supporting these panels became a very great challenge. Cost became another issue, for in spite of the low cost of the relay itself, the installed cost of the panel could be quite high. The total costincluding purchased parts, wiring, and installation labor, could range from $30~$50 per relay. To make matters worse, the constantly changingneeds of a process called for recurring modifications of a control panel. With relays, this was a costly prospect, as it was accomplished by a major rewiring effort on the panel. In addition these changes were sometimes poorly documented, causing a second-shift maintenance nightmare months later. In light of this, it was not uncommon to discard an entire control panel in favor of a new one with the appropriate components wired in a manner suited for the new process. Add to this the unpredictable, and potentially high, cost of maintaining these systemsas on high-volume motor vehicle production lines, and it became clearthat something was needed to improve the control process – to make it more reliable, easier totroubleshoot, and more adaptable to changing control needs.That something, in the late 1960s, was the first programmable controller. This first ‘revolutionary’ systemwan developed as a specific response to the needs of the major automotive manufacturers in the United States. These early controllers, or programmable logic controllers (PLC), represented the first systems that 1 could be used on the factory floor, 2 could have there ‘logic’ changed without extensive rewiring orcomponent changes, and 3 were easy to diagnose and repair when problems occurred.It is interesting to observe the progress that has been made in the past 15 years in the programmable controller area. The pioneer products of the late 1960s must have been confusing and frightening to a greatnumber of people. For example, what happened to the hardwired and electromechanical devices that maintenance personnel were used to repairing with hand tools? They were replaced with ‘computers’ disguised as electronics designed to replace relays. Even the programming tools were designed to appear as relay equivalent presentations. We have the opportunity now to examine the promise, in retrospect, that the programmable controller brought to manufacturing.All programmable controllers consist of the basic functional blocks shown in Fig. 10. 1. We’ll examine each block to understand the relationship to the control system. First we look at the center, as itis the heart ( or at least the brain ) of the system. It consists of a microprocessor, logic memory for the storage of the actual control logic, storage or variable memory for use with data that will ordinarily change as a function power for the processor and memory. Next comes the I/O block. This function takes the control level signals for the CPU and converts them to voltage and current levels suitable for connection with factory grade sensors and actuators. The I/O type can range from digital (discrete or on / off), analog (continuously variable), or a variety of special purpose ‘smart’ I/O which are dedicated to a certain application task. The programmer is shown here, but it is normally used only to initially configure and program a system and is notrequired for the system to operate. It is also used in troubleshooting a system, and can prove to be a valuable tool in pinpointing the exact cause of a problem. The field devices shown here represent the varioussensors and actuators connected to the I/O. These are the arms, legs, eyes, and ears of the system, including push buttons, limit switches, proximity switches, photosensors, thermocouples, RTDS, position sensing devices, and bar code reader as input; and pilot lights, display devices, motor starters, DC and AC drives, solenoids, and printers as outputs.No single attempt could cover its rapidly changing scope, but three basic characteristics can be examined to give classify an industrial control device as a programmable controller. (1) Its basic internal operation is to solve logic from the beginning of memory to somespecified point, such as end of memory or end of program. Once the endis reached, the operation begins again at the beginning of memory. This scanning process continues from the time power is supplied to the timeit it removed.(2) The programming logic is a form of a relay ladder diagram. Normally open, normally closed contacts, and relay coils are used within a format utilizing a left and a right vertical rail. Power flow (symbolic positive electron flow) is used to determine which coil or outputs are energized or deenergized. (3) The machine is designed forthe industrial environment from its basic concept; this protection isnot added at a later date. The industrial environment includesunreliable AC power, high temperatures (0 to 60 degree Celsius), extremes of humidity, vibrations, RF noise, and other similar parameters. General application areasThe programmable controller is used in a wide variety of control applications today, many of which were not economically possible just a few years ago. This is true for two general reasons: 1 there cost effectiveness (that is, the cost per I/O point) has improveddramatically with the falling prices of microprocessors and related components, and 2 the ability of the controller to solve complex computation and communication tasks has made it possible to use it where a dedicated computer was previously used.Applications for programmable controllers can be categorized in a number of different ways, including general and industrial application categories. But it is important to understand the framework in which controllers are presently understood and used so that the full scope of present and future evolution can be examined. It is through the power of applications that controllers can be seen in their full light.Industrial applications include many in both discrete manufacturing and process industries. Automotive industry applications, the genesis of the programmable controller, continue to provide the largest base of opportunity. Other industries, such as food processing and utilities, provide current development opportunities.There are five general application areas in which programmable controllers are used. A typical installation will use one or more of these integrated to the control system problem. The five general areas are explained briefly below.DescriptionThe AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer with 4K bytes of Flash programmable and erasable read only memory (PEROM). The device is manufactured using Atmel’s high-density nonvolatile memory technology and is compatible withthe industry-standard MCS-51 instruction set and pinout. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C51is a powerful microcomputer which provides a highly-flexible and cost-effective solution to many embedded control applications.Function characteristicThe AT89C51 provides the following standard features: 4K bytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bit timer/counters, a five vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator and clock circuitry. In addition, the AT89C51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port andinterrupt system to continue functioning. The Power-down Mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset.Pin Description:VCCSupply voltage.:GNDGround.:Port 0Port 0 is an 8-bit open-drain bi-directional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as highimpedance inputs.Port 0 may also be configured to be the multiplexed loworder address/data bus during accesses to external program and data memory. In this mode P0 has internal pullups.Port 0 also receives the code bytes during Flash programming,and outputs the code bytes during programverification. External pullups are required during programverification.Port 1Port 1 is an 8-bit bi-directional I/O port with internal pullups.The Port 1 output buffers can sink/source four TTL inputs.When 1s are written to Port 1 pins they are pulled high by the internal pullups and can be used as inputs. As inputs,Port 1 pins that are externally being pulled low will source current (IIL) because of the internalpullups.Port 1 also receives the low-order address bytes during Flash programming and verification.Port 2Port 2 is an 8-bit bi-directional I/O port with internal pullups.The Port 2 output buffers can sink/source four TTL inputs.When 1s are written to Port 2 pins they are pulled high by the internal pullups and can be used as inputs. As inputs,Port 2 pins that are externally being pulled low will source current, because of the internal pullups.Port 2 emits the high-order address byte during fetches from external programmemory and during accesses to external data memory that use 16-bit addresses. In this application, it uses strong internal pullupswhen emitting 1s. During accesses to external data memory that use 8-bit addresses, Port 2 emits the contents of the P2 Special Function Register.Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.Port 3Port 3 is an 8-bit bi-directional I/O port with internal pullups.The Port 3 output buffers can sink/source four TTL inputs.When 1s arewritten to Port 3 pins they are pulled high by the internal pullups and can be used as inputs. As inputs,Port 3 pins that are externally being pulled low will source current (IIL) because of the pullups.Port 3 also serves the functions of various special features of the AT89C51 aslisted below:Port 3 also receives some control signals for Flash programming and verification.RSTReset input. A high on this pin for two machine cycles while the oscillator is running resets the device. ALE/PROGAddress Latch Enable output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming.In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may beused for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory.If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.PSENProgram Store Enable is the read strobe to external program memory.When the AT89C51 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory.EA/VPPExternal Access Enable. EA must be strapped to GND in order toenable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset.EA should be strapped to VCC for internal program executions.This pin also receives the 12-volt programming enable voltage(VPP) during Flash programming, for parts that require12-volt VPP.XTAL1Input to the inverting oscillator amplifier and input to theinternal clock operating circuit. XTAL2Output from the inverting oscillator amplifier.Oscillator CharacteristicsXTAL1 and XTAL2 are the input and output, respectively,of aninverting amplifier which can be configured for use as an on-chip oscillator, as shown in Figure 1.Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown inFigure 2.There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed.Figure 1. Oscillator Connections Figure 2. External Clock Drive ConfigurationIdle ModeIn idle mode, the CPU puts itself to sleep while all the onchip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardwarereset.It should be noted that when idle is terminated by a hard ware reset, the device normally resumes program execution,from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate thepossibility of an unexpected write to a port pin when Idle is terminatedby reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory.Power-down ModeIn the power-down mode, the oscillator is stopped, and theinstruction that invokes power-down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the power-down mode is terminated. The only exit from power-down is a hardware reset. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize.Program Memory Lock BitsOn the chip are three lock bits which can be left unprogrammed (U)or can be programmed (P) to obtain the additional features listed in the table below.When lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset. If the device is powered up without a reset, the latch initializes to a random value, and holds that value until reset is activated. It is necessary that the latched value of EA be in agreement with the current logic level介绍可编程控制器从简单的遗产,这些不寻常的系统已经发展到不仅取代机电设备,而是解决问题的控制日益增加的过程和非过程中一系列行业的腾飞。

单片机外文翻译外文文献英文文献单片机的发展与应用

单片机外文翻译外文文献英文文献单片机的发展与应用

单片机外文翻译外文文献英文文献单片机的发展与应用THE Application and Development ofMicrocontroller UnitMonolithic integrated circuits are a computer chip. It uses tec hnology will have a data processing ability of the microprocessor (cpu), storage in rom (program memory and data storage ram ), the input, output interfaces circuit (I/O) integration interface i tu rned around with a chip in that small, constitutes a very good and the computer hardware system, where the application under the c ontrol of a monolithic integrated circuits can be accurate, fast and efficient procedures provided in advance to complete the task. So, a monolithic integrated circuits will have a computer chip of all t he functions.Thus, the microprocessor (monolithic integrated circuits has generally cpu )chips are not functional, it can independently com plete modern industrial control required for intelligent control func tions, it is monolithic integrated circuits of the biggest characteristi c.Monolithic integrated circuits, however, and different from mac hines ( a microprocessor chips, the memory chip and input and o utput interfaces chip in with a piece of printed circuit board of a microcomputer ), Monolithic integrated circuits chip in developing ago, it is only a function vlsi will have a strong, If of application development, it is a small microcomputer control system, but it m achine or a personal computer (pc is essential. the difference betw een).Monolithic integrated circuits of the application of chips at the level of application, the user (monolithic integrated circuits lear ners with users understand the structure of the chip )monolithic integrated circuits and instruction system, and the integrated use o f technology and system design to the theory and techniques, in th is particular chip design application, thereby, the chip with a parti cular function.Different monolithic integrated circuits have different hardware and software, or the technical features are different, Character de pends on a hardware chip monolithic integrated circuits the intern al structure of the user to use some monolithic integrated circuits, we must know this type of product whether to meet the needs of the facilities and application of the indicators required. The tech nical features include functional characteristics, control and electric al attributes, These information to manufacturers in the technical manual. Software features refers to an instruction system and devel opment support of the environment, the quality of instruction or monolithic integrated circuits for reference, data processing and log ical processing, output characteristics and to the power input requi rements, etc. Development support of the environment, including th e instructions of compatible and portable. support software (contai ns can support the development and application software and hard ware resources. resources). To take advantage of the model of deve lopment of a monolithic integrated circuits application systems, lea rn its structural features and technological characteristic is require d.Monolithic integrated circuits to control system will ever use o f sophisticated electronic circuit or circuit, a control system to achi eve the software controls and enable intelligent, It is monolithic in tegrated circuits to control areas, such as communications products and household appliances, the instruments and processes to contr ol and control devices, theapplication of more monolithic integrate d circuits sector.Monolithic integrated circuits, of course, the application is not limited to the application or the category of the economic perfor mance is more important it is a fundamental change in the traditi onal methods designed to control and mind control techniques. it i s a revolution is an important milestone.Can say now is the policy, a hundred schools of thought conte nd "monolithic integrated circuits, World chip all the company unv eiled his monolithic integrated circuits, from 8, 16 to 32 bits, and,with mainstream c51 series of, and there is not compatible with e ach other, but they, as complementary to monolithic integrated circ uits, the application of the world provide a broad.Throughout monolithic integrated circuits of the development p rocess, the trend of a monolithic integrated circuits, has :1.the low TDP COMSMcs -51 8031 a series of TDP for 630mw, and now a monolit hic integrated circuits, and generally in 100mw. As to ask for lowe r TDP monolithic integrated circuits, and now each monolithic inte grated circuits are used in the basic cmos (complementary metal o xides semiconductor technology). Like 80c51 adopt a hmos (the hig h density metal oxides semiconductor technology) and chmos (com plementary high density metal oxides semiconductor technology). C mos although TDP low, but owing to their physical characteristics to their work at a speed isn't high enough, but it has a high-spee d chmos TDP and low, these features are more appropriate to ask for lower TDP in a battery operated applications. so this process will be for a period of development. the main way to monolithic i ntegrated circuits。

单片机英文参考文献

单片机英文参考文献

Progress in ComputersPrestige Lecture delivered to IEE, Cambridge, on 5 February 2004Maurice WilkesComputer LaboratoryUniversity of CambridgeThe first stored program computers began to work around 1950. The one we built in Cambridge, the EDSAC was first used in the summer of 1949.These early experimental computers were built by people like myself with varying backgrounds. We all had extensive experience in electronic engineering and were confident that that experience would stand us in good stead. This proved true, although we had some new things to learn. The most important of these was that transients must be treated correctly; what would cause a harmless flash on the screen of a television set could lead to a serious error in a computer.As far as computing circuits were concerned, we found ourselves with an embarass de richess. For example, we could use vacuum tube diodes for gates as we did in the EDSAC or pentodes with control signals on both grids, a system widely used elsewhere. This sort of choice persisted and the term families of logic came into use. Those who have worked in the computer field will remember TTL, ECL and CMOS. Of these, CMOS has now become dominant.In those early years, the IEE was still dominated by power engineering and w e had to fight a number of major battles in order to get radio engineering along with the rapidly developing subject of electronics.dubbed in the IEE light current electrical engineering.properly recognised as an activity in its own right. I remember that we had some difficulty in organising a conference because the power engineers’ ways of doing things were not our ways. A minor source of irritation was that all IEE published papers were expected to start with a lengthy statement of earlier practice, something difficult to do when there was no earlier practiceConsolidation in the 1960sBy the late 50s or early 1960s, the heroic pioneering stage was over and the computer field was starting up in real earnest. The number of computers in the world had increased and they were much more reliable than the very early ones . To those years we can ascribe the first steps in high level languages and the first operating systems. Experimental time-sharing was beginning, and ultimately computer graphics was to come along.Above all, transistors began to replace vacuum tubes. This change presented a formidable challenge to the engineers of the day. They had to forget what they knew about circuits and start again. It can only be said that they measured up superbly well to the challenge and that the change could not have gone more smoothly.Soon it was found possible to put more than one transistor on the same bit of silicon, and this was the beginning of integrated circuits. As time went on, a sufficient level ofintegration was reached for one chip to accommodate enough transistors for a small number of gates or flip flops. This led to a range of chips known as the 7400 series. The gates and flip flops were independent of one another and each had its own pins. They could be connected by off-chip wiring to make a computer or anything else.These chips made a new kind of computer possible. It was called a minicomputer. It was something less that a mainframe, but still very powerful, and much more affordable. Instead of having one expensive mainframe for the whole organisation, a business or a university was able to have a minicomputer for each major department.Before long minicomputers began to spread and become more powerful. The world was hungry for computing power and it had been very frustrating for industry not to be able to supply it on the scale required and at a reasonable cost. Minicomputers transformed the situation.The fall in the cost of computing did not start with the minicomputer; it had always been that way. This was what I meant when I referred in my abstract to inflation in the computer industry ‘going the other way’. As time goes on people get more for their money, not less.Research in Computer Hardware.The time that I am describing was a wonderful one for research in computer hardware. The user of the 7400 series could work at the gate and flip-flop level and yet the overall level of integration was sufficient to give a degree of reliability far above that of discreet transistors. The researcher, in a university or elsewhere, could build any digital device that a fertile imagination could conjure up. In the Computer Laboratory we built the Cambridge CAP, a full-scale minicomputer with fancy capability logic.The 7400 series was still going strong in the mid 1970s and was used for the Cambridge Ring, a pioneering wide-band local area network. Publication of the design study for the Ring came just before the announcement of the Ethernet. Until these two systems appeared, users had mostly been content with teletype-based local area networks.Rings need high reliability because, as the pulses go repeatedly round the ring, they must be continually amplified and regenerated. It was the high reliability provided by the 7400 series of chips that gave us the courage needed to embark on the project for the Cambridge Ring.The RISC Movement and Its AftermathEarly computers had simple instruction sets. As time went on designers of commercially available machines added additional features which they thought would improve performance. Few comparative measurements were done and on the whole the choice of features depended upon the designer’s intuition.In 1980, the RISC movement that was to change all this broke on the world. The movement opened with a paper by Patterson and Ditzel entitled The Case for the Reduced Instructions Set Computer.Apart from leading to a striking acronym, this title conveys little of the insights into instruction set design which went with the RISC movement, in particular the way it facilitated pipelining, a system whereby several instructions may be in different stages of execution within the processor at the same time. Pipelining was not new, but it was new for small computersThe RISC movement benefited greatly from methods which had rec ently become available for estimating the performance to be expected from a computer design without actually implementing it. I refer to the use of a powerful existing computer to simulate the new design. By the use of simulation, RISC advocates were able to predict with some confidence that a good RISC design would be able to out-perform the best conventionalcomputers using the same circuit technology. This prediction was ultimately born out in practice.Simulation made rapid progress and soon came into universal use by computer designers. In consequence, computer design has become more of a science and less of an art. Today, designers expect to have a roomful of, computers available to do their simulations, not just one. They refer to such a roomful by the attractive name of computer farm.The x86 Instruction SetLittle is now heard of pre-RISC instruction sets with one major exception, namely that of the Intel 8086 and its progeny, collectively referred to as x86. This has become the dominant instruction set and the RISC instruction sets that originally had a considerable measure of success are having to put up a hard fight for survival.This dominance of x86 disappoints people like myself who come from the research wings.both academic and industrial.of the computer field. No doubt, business considerations have a lot to do with the survival of x86, but there are other reasons as well. However much we research oriented people would like to think otherwise. high level languages have not yet eliminated the use of machine code altogether. We need to keep reminding ourselves that there is much to be said for strict binary compatibility with previous usage when that can be attained. Nevertheless, things might have been different if Intel’s major attempt to produ ce a good RISC chip had been more successful. I am referring to the i860 (not the i960, which was something different). In many ways the i860 was an excellent chip, but its software interface did not fit it to be used in a workstation.There is an interesting sting in the tail of this apparently easy triumph of the x86 instruction set. It proved impossible to match the steadily increasing speed of RISC processors by direct implementation of the x86 instruction set as had been done in the past. Instead, designers took a leaf out of the RISC book; although it is not obvious, on the surface, a modern x86 processor chip contains hidden within it a RISC-style processor with its own internal RISC coding. The incoming x86 code is, after suitable massaging, converted into this internal code and handed over to the RISC processor where the critical execution is performed.In this summing up of the RISC movement, I rely heavily on the latest edition of Hennessy and Patterson’s books on computer design as my supporting authority; see in particular Computer Architecture, third edition, 2003, pp 146, 151-4, 157-8.The IA-64 instruction set.Some time ago, Intel and Hewlett-Packard introduced the IA-64 instruction set. This was primarily intended to meet a generally recognised need for a 64 bit address space. In this, it followed the lead of the designers of the MIPS R4000 and Alpha. However one would have thought that Intel would have stressed compatibility with the x86; the puzzle is that they did the exact opposite.Moreover, built into the design of IA-64 is a feature known as predication which makes it incompatible in a major way with all other instruction sets. In particular, it needs 6 extra bits with each instruction. This upsets the traditional balance between instruction word length and information content, and it changes significantly the brief of the compiler writer.In spite of having an entirely new instruction set, Intel made the puzzling claim that chips based on IA-64 would be compatible with earlier x86 chips. It was hard to see exactly what was meant.Chips for the latest IA-64 processor, namely, the Itanium, appear to have special hardware for compatibility. Even so, x86 code runs very slowly.Because of the above complications, implementation of IA-64 requires a larger chipthan is required for more conventional instruction sets. This in turn implies a higher cost. Such at any rate, is the received wisdom, and, as a general principle, it was repeated as such by Gordon Moore when he visited Cambridge recently to open the Betty and Gordon Moore Library. I have, however, heard it said that the matter appears differently from within Intel. This I do not understand. But I am very ready to admit that I am completely out of my depth as regards the economics of the semiconductor industry.AMD have defined a 64 bit instruction set that is more compatible with x86 and they appear to be making headway with it. The chip is not a particularly large one. Some people think that this is what Intel should have done. [Since the lecture was delivered, Intel have announced that they will market a range of chips essentially compatible with those offered by AMD.]The Relentless Drive towards Smaller TransistorsThe scale of integration continued to increase. This was achieved by shrinking the original transistors so that more could be put on a chip. Moreover, the laws of physics were on the side of the manufacturers. The transistors also got faster, simply by getting smaller. It was therefore possible to have, at the same time, both high density and high speed.There was a further advantage. Chips are made on discs of silicon, known as wafers. Each wafer has on it a large number of individual chips, which are processed together and later separated. Since shrinkage makes it possible to get more chips on a wafer, the cost per chip goes down.Falling unit cost was important to the industry because, if the latest chips are cheaper to make as well as faster, there is no reason to go on offering the old ones, at least not indefinitely. There can thus be one product for the entire market.However, detailed cost calculations showed that, in order to maintain this advantage as shrinkage proceeded beyond a certain point, it would be necessary to move to larger wafers. The increase in the size of wafers was no small matter. Originally, wafers were one or two inches in diameter, and by 2000 they were as much as twelve inches. At first, it puzzled me that, when shrinkage presented so many other problems, the industry should make things harder for itself by going to larger wafers. I now see that reducing unit cost was just as important to the industry as increasing the number of transistors on a chip, and that this justified the additional investment in foundries and the increased risk.The degree of integration is measured by the feature size, which, for a given technology, is best defined as the half the distance between wires in the densest chips made in that technology. At the present time, production of 90 nm chips is still building up Suspension of LawIn March 1997, Gordon Moore was a guest speaker at the celebrations of the centenary of the discovery of the electron held at the Cavendish Laboratory. It was during the course of his lecture that I first heard the fact that you can have silicon chips that are both fast and low in cost described as a violation of Murphy’s law.or Sod’s law as it is usually called in the UK. Moore said that experience in other fields would lead you to expect to have to choose between speed and cost, or to compromise between them. In fact, in the case of silicon chips, it is possible to have both.In a reference book available on the web, Murphy is identified as an engineer working on human acceleration tests for the US Air Force in 1949. However, we were perfectly familiar with the law in my student days, when we called it by a much more prosaic name than either of those mentioned above, namely, the Law of General Cussedness. We even had a mock examination question in which the law featured. It was the type of question in which the first part asks for a definition of some law or principle and the second part contains aproblem to be solved with the aid of it. In our case the first part was to define the Law of General Cussedness and the second was the problem;A cyclist sets out on a circular cycling tour. Derive an equation giving the direction of the wind at any time.The single-chip computerAt each shrinkage the number of chips was reduced and there were fewer wires going from one chip to another. This led to an additional increment in overall speed, since the transmission of signals from one chip to another takes a long time.Eventually, shrinkage proceeded to the point at which the whole processor except for the caches could be put on one chip. This enabled a workstation to be built that out-performed the fastest minicomputer of the day, and the result was to kill the minicomputer stone dead. As we all know, this had severe consequences for the computer industry and for the people working in it.From the above time the high density CMOS silicon chip was Cock of the Roost. Shrinkage went on until millions of transistors could be put on a single chip and the speed went up in proportion.Processor designers began to experiment with new architectural features designed to give extra speed. One very successful experiment concerned methods for predicting the way program branches would go. It was a surprise to me how successful this was. It led to a significant speeding up of program execution and other forms of prediction followed Equally surprising is what it has been found possible to put on a single chip computer by way of advanced features. For example, features that had been developed for the IBM Model 91.the giant computer at the top of the System 360 range.are now to be found on microcomputersMurphy’s Law remained in a state of suspension. No longer did it make sense to build experimental computers out of chips with a small scale of integration, such as that provided by the 7400 series. People who wanted to do hardware research at the circuit level had no option but to design chips and seek for ways to get them made. For a time, this was possible, if not easyUnfortunately, there has since been a dramatic increase in the cost of making chips, mainly because of the increased cost of making masks for lithography, a photographic process used in the manufacture of chips. It has, in consequence, again become very difficult to finance the making of research chips, and this is a currently cause for some concern.The Semiconductor Road MapThe extensive research and development work underlying the above advances has been made possible by a remarkable cooperative effort on the part of the international semiconductor industry.At one time US monopoly laws would probably have made it illegal for US companies to participate in such an effort. However about 1980 significant and far reaching changes took place in the laws. The concept of pre-competitive research was introduced. Companies can now collaborate at the pre-competitive stage and later go on to develop products of their own in the regular competitive manner.The agent by which the pre-competitive research in the semi-conductor industry is managed is known as the Semiconductor Industry Association (SIA). This has been active as a US organisation since 1992 and it became international in 1998. Membership is open to any organisation that can contribute to the research effort.Every two years SIA produces a new version of a document known as the International Technological Roadmap for Semiconductors (ITRS), with an update in the intermediate years. The first volume bearing the title ‘Roadmap’ was issued in 1994 but two reports, written in1992 and distributed in 1993, are regarded as the true beginning of the series.Successive roadmaps aim at providing the best available industrial consensus on the way that the industry should move forward. They set out in great detail.over a 15 year horizon. the targets that must be achieved if the number of components on a chip is to be doubled every eighteen months.that is, if Moore’s law is to be maintained.-and if the cost per chip is to fall.In the case of some items, the way ahead is clear. In others, manufacturing problems are foreseen and solutions to them are known, although not yet fully worked out; these areas are coloured yellow in the tables. Areas for which problems are foreseen, but for which no manufacturable solutions are known, are coloured red. Red areas are referred to as Red Brick Walls.The targets set out in the Roadmaps have proved realistic as well as challenging, and the progress of the industry as a whole has followed the Roadmaps closely. This is a remarkable achievement and it may be said that the merits of cooperation and competition have been combined in an admirable manner.It is to be noted that the major strategic decisions affecting the progress of the industry have been taken at the pre-competitive level in relative openness, rather than behind closed doors. These include the progression to larger wafers.By 1995, I had begun to wonder exactly what would happen when the inevitable point was reached at which it became impossible to make transistors any smaller. My enquiries led me to visit ARPA headquarters in Washington DC, where I was given a copy of the recently produced Roadmap for 1994. This made it plain that serious problems would arise when a feature size of 100 nm was reached, an event projected to happen in 2007, with 70 nm following in 2010. The year for which the coming of 100 nm (or rather 90 nm) was projected was in later Roadmaps moved forward to 2004 and in the event the industry got there a little sooner.I presented the above information from the 1994 Roadmap, along with such other information that I could obtain, in a lecture to the IEE in London, entitled The CMOS end-point and related topics in Computing and delivered on 8 February 1996.The idea that I then had was that the end would be a direct consequence of the number of electrons available to represent a one being reduced from thousands to a few hundred. At this point statistical fluctuations would become troublesome, and thereafter the circuits would either fail to work, or if they did work would not be any faster. In fact the physical limitations that are now beginning to make themselves felt do not arise through shortage of electrons, but because the insulating layers on the chip have become so thin that leakage due to quantum mechanical tunnelling has become troublesome.There are many problems facing the chip manufacturer other than those that arise from fundamental physics, especially problems with lithography. In an update to the 2001 Roadmap published in 2002, it was stated that the continuation of progress at present rate will be at risk as we approach 2005 when the roadmap projects that progress will stall without research break-throughs in most technical areas “. This was the most specific statement about the Red Brick Wall, that had so far come from the SIA and it was a strong one. The 2003 Roadmap reinforces this statement by showing many areas marked red, indicating the existence of problems for which no manufacturable solutions are known.It is satisfactory to report that, so far, timely solutions have been found to all the problems encountered. The Roadmap is a remarkable document and, for all its frankness about the problems looming above, it radiates immense confidence. Prevailing opinion reflects that confidence and there is a general expectation that, by one means or another,shrinkage will continue, perhaps down to 45 nm or even less.However, costs will rise steeply and at an increasing rate. It is cost that will ultimately be seen as the reason for calling a halt. The exact point at which an industrial consensus is reached that the escalating costs can no longer be met will depend on the general economic climate as well as on the financial strength of the semiconductor industry itself.。

关于单片机的英文文献

关于单片机的英文文献

关于单片机的英文文献engine-control systems, brakingsystems (ABS). applications thatbenefitThe General Situation of AT89C51Microcontrollers are used in a multitude of commercial applicationssuch as modems, motor-control systems, air conditioner control systems, automotive engine and amongothers. The high processing speed and enhanced peripheral set of these microcontrollers make them suitable for such high-speed event-based applications. However, these critical application domains also require that these microcontrollers are highly reliable. The highreliability and low market risks can be ensured by a robust testing process and a proper tools environment for the validation of these microcontrollers both at the component and at the system level. Intel Platform Engineering department developed an object-oriented multi-threaded test environment for the validation of its AT89C51 automotive microcontrollers. The goals of this environment was not only to provide a robust testing environment for theAT89C51 automotive microcontrollers, but to develop an environment which canbe easilyextended and reused for the validation of several other futuremicrocontrollers. The environment was developed in conjunction withMicrosoft Foundation Classes (AT89C51). The paper describes the design and mechanism of this test environment, its interactions with varioushardware/software environmental components, and how to use AT89C51.1.1 IntroductionThe 8-bit AT89C51 CHMOSmicrocontrollers are designed to handle high-speed calculations and fast input/output operations. MCS 51microcontrollers are typically used for high-speed event control systems. Commercial applications include modems,motor-control systems, printers, photocopiers, air conditioner control systems, disk drives, and medical instruments. The automotive industry use MCS 51 microcontrollers in airbags, suspension systems, and antilock The AT89C51 is especially well suited to from itsprocessing speed and enhanced on-chip dynamicsuspension, antilock braking, and stability control applications.peripheral functions set, such as automotive power-train control, vehicleBecause of these critical applications, the market requires a reliable cost-effective controller with a low interrupt latency response, abilityto service the high number of time and event driven integrated peripherals needed in real time applications, and a CPUwith above average processing power in a single package. The financial and legal risk of having devices that operate unpredictably is very high. Once in the market, particularly in mission critical applications such as an autopilot or anti-lockbraking system, mistakes are financially prohibitive. Redesign costs can run as high as a $500K, much more if the fix means 2 back annotating it across a product family that share the samecore and/or peripheral design flaw. In addition, field replacements of components is extremely expensive, as the devices are typically sealed in modules with a total value several times that of the component. To mitigate these problems, it is essential that comprehensive testing of the controllers be carried out at both the component level and system level under worst case environmental and voltage conditions. This complete and thorough validation necessitates not only a well-defined process but also a proper environment and tools to facilitate and execute the mission successfully. Intel Chandler Platform Engineering group provides post silicon system validation (SV)of various micro-controllers and processors. The system validation process can be broken into three major parts. The type of the device and its application requirements determine which types of testing are performed on the device.1.2 The AT89C51 provides the following standard features:4Kbytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bittimer/counters, a five vector two-level interrupt architecture, a full duple serial port, on-chip oscillator and clock circuitry. In addition, the AT89C51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Modestops the CPUwhile allowing the RAM,timer/counters, serial port and interrupt sys -tem to continue functioning. The Power-down Mode saves the。

单片机英文参考文献(精选120个)

单片机英文参考文献(精选120个)

我国的单片机起步虽然较晚,但经过几十年的发展,也取得了巨大的成就。

不论是工业生产还是社会生活的各个方面都离不开单片机的使用。

下面是搜素整理的单片机英文参考文献的分享,以供参考。

单片机英文参考文献一: [1]Hui Wang. Optimal Design of Single Chip Microcomputer Multi-machine Serial Communication based on Signal VerificationTechnology[J]. International Journal of Intelligent Information and Management Science,2020,9(1)。

[2]Philip J. Basford,Steven J. Johnston,Colin S. Perkins,Tony Garnock-Jones,Fung Po Tso,Dimitrios Pezaros,Robert D. Mullins,Eiko Yoneki,Jeremy Singer,Simon J. Cox. Performance analysis of single board computer clusters[J]. Future Generation ComputerSystems,2020,102. [3]. Computers; Reports from University of Southampton Describe Recent Advances in Computers (Performance Analysis of Single Board Computer Clusters)[J]. Computers, Networks & Communications,2020. [4]Yunyu Cao,Jinjin Dang,Chenxu Cao. Design of Automobile Digital Tire Pressure Detector[J]. Journal of Scientific Research and Reports,2019. [5]Sudad J. Ashaj,Ergun Er?elebi. Reduce Cost Smart Power Management System by Utilize Single Board Computer Artificial Neural Networks for Smart Systems[J]. International Journal of Computational Intelligence Systems,2019. [6]Hanhong Tan*, Yanfei Teng. Design of PWM Lighting brightness Control based on LAN QIAO Cup single Chip Microcomputer[J]. International Journal of Computational and Engineering,2019,4(3)。

单片机英文文献

单片机英文文献

单片机英文文献Microcontrollers, often referred to as the "brains" of a system, are small computers integrated into a single chip. They are designed to perform a specific set of tasks and are widely used in various applications, from householdappliances to automotive systems and industrial automation.The evolution of microcontrollers has been remarkable,with continuous advancements in technology leading to increased processing power, reduced size, and improved energy efficiency. Modern microcontrollers are equipped with various features such as integrated memory, peripherals for communication, and support for multiple programming languages, making them versatile tools for developers.One of the key aspects of microcontroller development is the ability to program them. Programming a microcontroller involves writing code that defines the operations the device will perform. This code is typically written in languagessuch as C, C++, or assembly, and is then compiled anduploaded to the microcontroller's memory.Debugging is another critical component ofmicrocontroller development. It involves testing the code to ensure that it functions as intended and identifying anyerrors that may occur. Debugging tools and techniques are essential for developers to refine their code and achieve optimal performance.In addition to programming and debugging, microcontroller development also encompasses the design of the hardware that the microcontroller will control. This includes selecting appropriate sensors, actuators, and other components thatwill interact with the microcontroller to achieve the desired functionality.The field of microcontroller development is constantly evolving, with new technologies and techniques emerging regularly. As a result, it is important for developers to stay informed about the latest advancements and tocontinually update their skills and knowledge.In conclusion, microcontrollers are integral to the functioning of many modern systems and devices. Their development involves a combination of programming, debugging, and hardware design, and requires a deep understanding of both software and hardware concepts. As technology continues to advance, the role of microcontrollers in our daily livesis likely to become even more significant.。

单片机英文文献

单片机英文文献

Principle of MCUSingle-chip is an integrated on a single chip a complete computer system. Even though most of his features in a small chip, but it has a need to complete the majority of computer components: CPU, memory, internal and external bus system, most will have the Core. At the same time, such as integrated communication interfaces, timers, real-time clock and other peripheral equipment. And now the most powerful single-chip microcomputer system can even voice, image, networking, input and output complex system integration on a single chip.Also known as single-chip MCU (Microcontroller), because it was first used in the field of industrial control. Only by the single-chip CPU chip developed from the dedicated processor. The design concept is the first by a large number of peripherals and CPU in a single chip, the computer system so that smaller, more easily integrated into the complex and demanding on the volume control devices. INTEL the Z80 is one of the first design in accordance with the idea of the processor, From then on, the MCU and the development of a dedicated processor parted ways.Early single-chip 8-bit or all of the four. One of the most successful is INTEL's 8031, because the performance of a simple and reliable access to a lot of good praise. Since then in 8031 to develop a single-chip microcomputer system MCS51 series. Based on single-chip microcomputer system of the system is still widely used until now. As the field of industrial control requirements increase in the beginning of a 16-bit single-chip, but not ideal because the price has not been very widely used. After the 90's with the big consumer electronics product development, single-chip technology is a huge improvement. INTEL i960 Series with subsequent ARM in particular, a broad range of applications, quickly replaced by 32-bit single-chip 16-bit single-chip high-end status, and enter the mainstream market. Traditional 8-bit single-chip performance has been the rapid increase in processing power compared to the 80's to raise a few hundred times. At present, the high-end 32-bit single-chip frequency over 300MHz, the performance of the mid-90's close on the heels of a special processor, while the ordinary price of the model dropped to one U.S. dollars, the most high-end models, only 10 U.S. dollars. Contemporary single-chip microcomputer system is no longer only the bare-metal environment in the development and use of a large number of dedicated embedded operating system is widely used in the full range of single-chip microcomputer. In PDAs and cell phones as the core processing of high-end single-chip or even a dedicated direct access to Windows and Linux operating systems.More than a dedicated single-chip processor suitable for embedded systems, so it was up to the application. In fact the number of single-chip is the world's largest computer. Modern human life used in almost every piece of electronic and mechanical products will have a single-chip integration. Phone, telephone, calculator, home appliances, electronic toys, handheld computers and computer accessories such as a mouse in the Department are equipped with 1-2 single chip. And personal computers also have a large number of single-chip microcomputer in the workplace. Vehicles equipped with more than 40 Department of the general single-chip, complex industrial control systems and even single-chip may have hundreds of work at the same time! SCM is not only far exceeds the number of PC and other integrated computing, even more than the number of human beings.Hardwave introductionThe 8051 family of micro controllers is based on an architecture which is highly optimized for embedded control systems. It is used in a wide variety of applications from militaryequipment to automobiles to the keyboard on your PC. Second only to the Motorola 68HC11 in eight bit processors sales, the 8051 family of microcontrollers is available in a wide array of variations from manufacturers such as Intel, Philips, and Siemens. These manufacturers have added numerous features and peripherals to the 8051 such as I2C interfaces, analog to digital converters, watchdog timers, and pulse width modulated outputs. Variations of the 8051 with clock speeds up to 40MHz and voltage requirements down to 1.5 volts are available. This wide range of parts based on one core makes the 8051 family an excellent choice as the base architecture for a company's entire line of products since it can perform many functions and developers will only have to learn this one platform.The basic architecture consists of the following features:·an eight bit ALU·32 descrete I/O pins (4 groups of 8) which can be individually accessed·two 16 bit timer/counters·full duplex UART· 6 interrupt sources with 2 priority levels·128 bytes of on board RAM·separate 64K byte address spaces for DATA and CODE memoryOne 8051 processor cycle consists of twelve oscillator periods. Each of the twelve oscillator periods is used for a special function by the 8051 core such as op code fetches and samples of the interrupt daisy chain for pending interrupts. The time required for any 8051 instruction can be computed by dividing the clock frequency by 12, inverting that result and multiplying it by the number of processor cycles required by the instruction in question. Therefore, if you have a system which is using an 11.059MHz clock, you can compute the number of instructions per second by dividing this value by 12. This gives an instruction frequency of 921583 instructions per second. Inverting this will provide the amount of time taken by each instruction cycle (1.085 microseconds).单片机原理单片机是指一个集成在一块芯片上的完整计算机系统。

单片机英文文献

单片机英文文献

Adaptive Multi-Sensor Interface System-On-Chip Jinwen Xi, Chao Yang, Andrew Mason and Peixin ZhongDepartment of Electrical and Computer Engineering,Michigan State University, East Lansing, U.S.A.{xijinwen, yangchao, mason, pzhong }@Abstract—This paper presents a system-on-chip using 0.18μm CMOS technology that integrates an 8-channel reconfigurable sensor interface with an 8-bit Σ-Δ A/D converter and a 16-bit sensor signal processor. The configurable sensor interface employs Wheatstone bridge and switched-capacitor topologies to efficiently perform signal conditioning for a wide range of resistive and capacitive sensors. The customized processor executes software for sensor interface configuration and calibration, data conversion control, sensor data calibration and compensation, and communication with external systems. On the 4x4mm chip with a 1.8V supply, the sensor readout circuit requires only 300μA and the processor power consumption is 209μW/MHz. The adaptive multi-sensor interface provides a platform solution with the flexibility crucial for implementing low-cost microsystems of the future.I. I NTRODUCTIONIn ultra-miniature and low power multi-sensor systems, the level of integration and functional flexibility are essential considerations for platform design. The sensor interface circuitry (signal conditioning and processing) is a key component in the whole system. Low-cost smart sensor systems increasingly contain multiple sensors of different types, which require heterogeneous interfaces for pre-amplification and pre-filtering. Integrating a programmable processor and an adaptive sensor interface into one system-on-chip (SoC) combines analog and digital processing capability and permits rapid customization to different applications using the same integrated circuit. Single-chip integration of these components enhances performance while simultaneously reducing size, cost and power consumption.This paper presents a sensor application SoC that integrates an 8-channel reconfigurable sensor interface, an 8-bit Σ-Δ A/D converter (ADC) and a 16-bit sensor signal processor (SSP). The sensor interface employs Wheatstone bridge and switched-capacitor topologies to perform signal readout for resistive and capacitive sensors, providing a unified interface for heterogeneous mix of sensors. The customized SSP executes software to support interface configuration and calibration, ADC control, and sensor data processing. This multi-sensor interface can intelligently adapt to the readout and signal processing needs of many different sensor applications, providing flexibility that is crucial for the implementation of low-cost microsystems.Recently there has been a lot of focus on intelligent sensory systems and universal sensor interfaces. In previous work [1,2] we have realized a generic multi-channel interface circuit that utilizes different circuit modules to readout different types of sensors. An SoC implementation of a fingerprint sensor with 32-bit RISC microprocessor and embedded memory has been presented [3]. A monolithic CMOS microplate-based gas sensor SoC has been proposed [4]. Compared with these efforts, the chip described here 1) provides a more highly configurable sensor interface for heterogeneous sensor types, and 2) utilizes a transaction-level design flow in the architectural design of the system, especially the digital sub-systems, to permit better system-level design and verification.II. S YSTEM A RCHITECTURE A ND D ESIGN M ETHODOLOGYFigure 1 depicts the system architecture of the proposed SoC, which is composed of three main functional blocks: Universal Sensor Interface (USI), A/D converter (ADC) and Sensor Signal Processor (SSP). The USI provides adaptive pre-amplification and pre-filtering of sensor-array signals by programming its control words via the SSP. Using the programmable sensor interface makes it more flexible when dealing with heterogeneous sensors in multi-sensor systems. The pre-conditioned sensor signal in the analog domain will be converted to digital format using an ADC featuring sigma-delta architecture. Both USI and ADC are controlled by SSP with 8-bit GPIOs mapped onto its memory addresses. The SSP is a 16-bit microprocessor featuring conventional Von-Neumann architecture with a simple 16-bit instruction set. The 16-bit address and data buses provide on-chip interconnection between the SSP and other functional blocks including on-chip RAM/ROM, multiplier, clock management unit, UART/SPI, and 8-bit GPIOs. One of the most important roles of the GPIOs is to provide controllability for the USI and ADC by setting theircorresponding control bits. The motivation of employing SSP and configurable USI in this architecture is to provide flexible configuration of the multi-sensor system for tens of different types of sensors. The ADC is time-multiplexed for multiple sensor inputs. On-chip SRAM provides buffering for data calculations as well as program code storage, and UART/SPI offers the communication interface between the SoC with external devices or host PC for data post-processing.A shared medium bus provides the interconnection between components. The programming of each functional block is mapped onto the central microprocessor’s 64KB address range. Some high performance SoC architectures with multi-processors, such as OMAP [5] and Nexperia [6], use dedicated bus-bridge for the translation between multi-buses. However, the sensor applications targeted by this SoC do not require high data throughput. Instead, simplicity and power efficiency are more valued in this design. Thus the proposed architecture provides easy control of the configurable sensor interface with low power overhead. The base system can be augmented with additional accelerators. For example, in this implementation, computation-intensive sensor applications can take advantage of an embedded 16-bit hardware multiplier that can perform a 16-bit MAC (multiplication and accumulation) operation in single clock cycle.The design flow employed in the proposed SoC integrates standard Synthesis and Placement & Route (SPR) flow in the digital blocks with full custom design flow in theanalog mixed-signal blocks. SPR flow automates most of thedesign process for the digital blocks using a vendor-specific standard-cell library, and it gives high fidelity of the success of the first-silicon. For analog parts, each transistor needs to be sized properly according to design specification, and there are no mature automated methodologies that are silicon-proven, so full custom design is applied. Using different design flows generates a challenge in verifying that the whole system integrates both digital and analog blocks with good coverage and fast simulation speed. Due to the design tool resource limit, full chip-level verification before signing-off is not performed in this design. Alternatively, digital and analog sub-systems are verified at the layout-level separately with their specific stimuli vectors before the final SoC integration is performed.A. Sensor Signal Processor (SSP) The target of the SSP is to provide maximum control to other functional blocks by running software code. Its 16-bit address bus provides the SSP’s 64KB address map, onto which all the digital peripherals are mapped as shown in Figure 2(a). The lowest 512 bytes of the 64KB address map are occupied by digital peripherals, in which the GPIO, UART/SPI, DCM are 8-bit peripherals, while the hardware multiplier is treated as 16-bit peripheral. The 16KB on-chip SRAM is partitioned into two blocks: Data SRAM (DSRAM: 0x0200~0x21FF) provides buffering for computation, and Program SRAM (PSRAM:After power-up, the on-chip boot loader fetches the program code from off-chip Flash/ROM to PSRAM, from which the code is executed. Using the boot loader and on-chip PSRAM reduces the signal transition on the external memory bus, and in turn reduces the dynamic power consumption.The architecture of the SSP is presented in Figure 2(b), which describes the interconnection among the main functional blocks: ALU (Arithmetic Logic Unit), GPR (General Purpose Registers), IDU (Instruction Decoding Unit) and CU (Control Unit). Internal MUXes andDeMUXes manipulated by the control signals that are decoded by the IDU provide control over the data path. Toreduce dynamic power consumption, clock gating is employed on the register file. In SSP execution, each instruction is fetched from the code memory, which may be mapped on-chip or off-chip. It is then processed by IDU, which decodes the current instruction to the fields of op-code, addressing mode, access type (read/write) and the source/target registers. The IDUalso calculates the absolute address by the addressing mode and decoded address, which are used to drive the address bus. The CU selects register files and set the corresponding signals for operation based on the decoded op-code. The data is fetched from the memory addressed by IDU, the GPR, or the ALU itself under the control of CU. Then the ALU will perform the specified operation before writing the results to the memory or register files. B. System Level Design MethodologyIt is widely believed that the earlier the software is developed along with the hardware, the more design time saving will be achieved by overlapping hardware and software design periods. To facilitate this hardware-software co-design methodology, SystemC [8] design flow was utilized for the SSP design and validation. SystemC is a system description language with a set of library routines and macros that extend C++, making it possible to model hardware, concurrency, and communication. The simulation is much faster than a typical VHDL/Verilog simulation. During execution, the modules can communicate in a simulated real-time environment, using signals of any datatype (provided in C++, SystemC, or user-defined). The simulation in SystemC provides visibility into the system at an early stage that is useful in debugging and determining areas for improvements, whether the modifications are in hardware and/or software.Shown in Figure 3, the SSP’s SystemC model was developed to allow for co-design of hardware and software for the digital part of the SoC. The SSP BFM (Bus Function Model) comprises five functional modules: processor, on-chip/off-chip memory and other digital peripherals. The processor ISA is modeled as simplified cycle-based, while the processor bus transactions, which are of interest in this early model since they control other functional blocks, are modeled by cycle-accurate bus_write and bus_read functions. The SSP SystemC model provides an early execution platform for the software code, which is developed using ANSI C. To reduce the software development overhead by using the available GNU tool flows, the ISA of the SSP is fully compatible with the Texas Instruments MSP430, a widely used commercial processor. With this SSP SystemC platform, the application code can be compiled and executed to verify the correctness of the software before an FPGA prototype or real silicon is ready. Moreover, the SystemC model provides an executable reference model for the RTL model that will be synthesized to the netlist, which will be used to generate the final GDS-II layout.Based on the SSP SystemC BFM reference model, the functionality-equivalent RTL model was designed and verified. The Xilinx Spartan-3 FPGA was used in the SSP design flow to provide a hardware emulation platform to verify the digital system’s timing and functionality. DuringFPGA emulation, the Block RAM (BRAM) in Spartan FPGA is used to map the on-chip memory blocks. Once the application code was compiled and linked, the output binary was converted into the BRAM map file where Block RAM was initialized in the specified format for the FPGA post-layout simulation and bit-stream generation. The generated bit-stream with both hardware and software designs was download to the FPGA platform shown in Figure 4(a) for execution.The final SSP RTL model was implemented using IBM 0.18μm standard cell design flow. Figure 4(b) shows the SSP layout with the size of 1.5mm×1.8mm, where on-chip memory blocks take ~50% of the total silicon area. The SSP achieves the clock speed of 15.2MHz with active energy consumption of 209μW/MHz at 1.8V during gate-level simulation. In sensor applications, the SSP will operate at under 10MHz to lower power consumption.C. Universal Sensor Interface (USI)The sensor interface in this SoC is capable of reading out resistive and capacitive sensors, which are extensively present in a wide variety of smart sensor systems. To cope with the dramatically varied sensor sensitivities and dynamic ranges, the interface is highly configurable and capable of dynamic calibration. To improve the hardware efficiency and capacitive readout shares hardware as much as possible. To achieve this, the capacitive and resistive information are converted to the uniform output and then processed with the shared hardware. For details of the sensor interface design are presented in [7].D. Analog to Digital ConverterThe overall design goal of the SoC is to achieve low power consumption and small system size with a moderate system speed. To meet these constraints, a Σ-Δ architecture that features low power, low hardware complexity and good robustness was chosen for the ADC. The ADC consists of five major function blocks shown in Figure 6: integrator, comparator, 1-bit sub-DAC, clock generator and digital counter. The switch-capacitor technique was employed to implement the ADC. To solve the charge injection issue in switch-capacitor circuits, a multiphase non-overlapping clock was used. The multiphase clocks are generated from an external main clock through an inverter-based delay chain.The ADC design achieves the maximum sampling rate of 4KS/s with a maximum 2.5MHz oversampling rate. The input dynamic range was simulated to be 1.2V, and the maximum power consumption was determined to be 2.025mW with 1.8V power supply.Code (C/C++)Compiler(TI/GNU)Binary CodeSystemCModelSimulation/VerificationSSP coreModelBus ModelPeripheral/Mem ModelHardware modelApplication codeFigure 3. SSP co-design flow with SystemC.(a) (b)Figure 4 (a). SSP FPGA emulation platform, (b). SSP layout.III. S ENSOR S O C CMOS I MPLEMENTATION The final multi-sensor SoC has been implemented usingIBM 0.18μm mixed-signal CMOS technology. The 4.0mm ×4.0mm chip is shown in Figure 7(b) with functional blockscovered by top layer metal labeled in Figure 7(a). A second USI block (bottom left) not connected to the ADC was added to facilitate analog testing. A dedicated 1-to-2 MUX controlled by a pin is used to select which of the USI blocks the SSP’s control signals are passed to.The test platform is shown in Figure 8. An external FPGA board is connected to the chip to provide the testing vectors. BRAM in the FPGA is configured to emulate the SoC’s external ROM. An RS-232 serial interface is also included in the test platform to communicate data with host PC. 8 LEDs connected to one of the SSP’s GPIO indicate the SoC’s current work status. The fabricated chip is currently under test.IV. C ONCLUSIONThis paper presented a multi-sensor SoC integrating programmable processor, universal sensor interface and ADC as well as other on-chip resources. The USI utilizes a configurable architecture for resistive and capacitive sensors, and offers 0.33~15 and 0.035~31.75 gain ranges for resistive and capacitive sensors, respectively. By sharing hardware resource, the USI achieves a low power consumption of 300μA with a 1.8V supply. The on-chip ADC features a single-stage Σ-Δ architecture and 8-bit resolution with a power consumption of 2.02mW at a 2.5MHz oversampling rate. The USI and ADC, along with other functional blocks, are controlled by the SSP, which executes software to orchestrate the whole system’s operation. With simplified RISC architectural design, the SSP achieves 209μW/MHz power consumption at 1.8V supply. The SystemC-based hardware/software co-design flow employed in the SSP design enables early software development, shortening the overall system design time. The SoC has been fabricated in IBM 0.18μm CMOS technology and is currently under final functional test.R EFERENCES[1] J. Zhang, J. Zhou, P. Balasundaram, and A. Mason, “A HighlyProgrammable Sensor Network Interface with Multiple Sensor Readout Circuits,” Proc. of IEEE Sensors 2003, vol. 2, pp. 748-752, Oct. 2003.[2] J. Zhang, and A. Mason, “Characterization of a configurable sensorsignal conditioning circuit for multi-sensor Microsystems,” Proc. of IEEE Sensors 2004, vol. 1, pp. 198-201, Oct. 2004[3] S.M. Jung, J.M. Nam et. al., “A CMOS Integrated CapacitiveFingerprint Sensor With 32-bit RISC Microcontroller”, In IEEE Journal of Solid-State Circuits, Vol. 40, pp. 1745-1750, Aug. 2005 [4] M. Y. Afridi, J. S. Suehle, M. E. Zaghloul, D. W. Berning, A. R.Hefner, R. E. Cavicchi, S. Semancik, C. B. Montgomery, and C.J.Taylor, “A Monolithic CMOS Microhotplate-Based Gas Sensor System,” IEEE Sensors Journal, vol. 2, pp. 644-655, Dec. 2002.[5] /general/docs/wtbu/[6] /applications/portable/high_end_vas/6120/index.html[7] C. Yang, J. Xi, A. Mason, P. Zhong, “Configurable Hardware-Efficient Interface Circuit for Multi-Sensor Microsystems”, will be presented atIEEE Sensors Conference2006, Daegu, Korea, Oct.2006[8] Figure 6. The system-level architecture of ADC.DataSRAMDataSRAMCodeSRAMROMSSPMAC + UART +GPIOSensorInterface SensorInterfaceADCFigure 7 (a) SoC layout with IBM 0.18μm CMOS process, (b) Fabricated SoC die micrograph.Figure 8. SoC chip test platform and the FPGA board islocated on the left side.。

单片机英文参考文献 带页码

单片机英文参考文献 带页码

单片机英文参考文献带页码单片机作为一种重要的电子设备,广泛应用于工业控制、智能仪表、数据采集等领域。

随着科技的发展,单片机技术也在不断进步,因此,了解单片机的发展历程、技术特点和应用领域等方面的参考文献对于学习和研究单片机技术是非常重要的。

一、单片机的发展历程单片机的发展可以追溯到20世纪70年代,当时计算机技术刚刚进入微型化阶段,一些工程师开始尝试将计算机技术应用到工业控制领域,从而发明了单片机。

随着技术的不断进步,单片机的种类和性能也在不断改进,目前已经形成了多种不同的系列和型号。

二、单片机的技术特点单片机是一种集成度非常高的芯片,它集成了中央处理器(CPU)、内存、输入输出接口等重要部件,因此具有很高的灵活性和可定制性。

同时,单片机也具有很高的可靠性和稳定性,因此广泛应用于各种需要高精度控制和数据采集的场合。

此外,单片机还可以通过编程和调试等方式进行二次开发,从而满足不同用户的需求。

三、单片机的主要应用领域1. 工业控制领域:单片机在工业控制领域中的应用最为广泛,它可以实现对生产线的自动化控制、机器人的运动控制等。

2. 智能仪表领域:单片机可以用于智能仪表的控制系统,可以实现自动化测量、数据采集、显示等功能。

3. 数据采集领域:单片机可以通过接口与各种传感器相连,实现对各种数据的采集和处理,广泛应用于各种需要大量数据处理的场合。

4. 消费电子领域:单片机也可以用于一些简单的智能设备,如智能家居、智能门锁等。

四、参考文献[1] 王洪伟. 单片机技术的发展与应用[J]. 信息技术, 2019,43(2): 34-37.[2] 张涛. 单片机的技术特点及应用领域[J]. 电子技术与软件工程, 2020(10): 108-110.[3] 李晓明. 单片机在智能仪表中的应用[J]. 自动化仪表, 2018, 39(5): 56-59.[4] 王伟. 单片机的可靠性设计[J]. 电子技术应用, 2021,47(6): 55-58.[5] 刘洋. 单片机的二次开发与应用[J]. 自动化技术与应用, 2017, 36(3): 69-72.以上参考文献均为英文文献,其中第一篇文献提供了单片机技术的发展历程和应用领域的详细介绍;第二篇文献介绍了单片机的主要技术特点;第三篇文献介绍了单片机在智能仪表中的应用;第四篇文献从可靠性设计角度介绍了单片机的重要特点;第五篇文献则从二次开发的角度介绍了单片机的重要应用。

(完整版)单片机毕业参考英文文献及翻译

(完整版)单片机毕业参考英文文献及翻译

Structure and function of the MCS-51 seriesStructure and function of the MCS-51 series one-chip computer MCS-51 is a name of a piece of one-chip computer series which Intel Company produces。

This company introduced 8 top-grade one—chip computers of MCS—51 series in 1980 after introducing 8 one-chip computers of MCS-48 series in 1976. It belong to a lot of kinds this line of one—chip computer the chips have,such as 8051, 8031, 8751, 80C51BH, 80C31BH,etc。

, their basic composition, basic performance and instruction system are all the same. 8051 daily representatives— 51 serial one-chip computers 。

An one—chip computer system is made up of several following parts: ( 1) One microprocessor of 8 (CPU)。

( 2) At slice data memory RAM (128B/256B),it use not depositting not can reading /data that write, such as result not middle of operation,final result and data wanted to show, etc. ( 3) Procedure memory ROM/EPROM (4KB/8KB ),is used to preserve the procedure , some initial data and form in slice. But does not take ROM/EPROM within some one-chip computers, such as 8031 , 8032, 80C ,etc。

单片机英文资料+英文文献

单片机英文资料+英文文献

Dormancy of the one-chip computer---restore to the throne in the operation way and improve anti- interference abilityAbstract:Introduce a kind of dormancy of using- restore to the throne in theoperation way and improve the anti-interference ability method of the one-chip computer;Analyse its scope of application, provide and use the circuit concretly; Combine the instance, analyse the characteristic of the hardware and software design under these kind of operation way.Keyword: One-chip computer Restore to the throne /dormancyanti-interference ForewordIntroduction:With the development at full speed of the microelectric technique, the performance of the one-chip computer improves rapidly, demonstrate the outstanding advantage in the operation, logic control, intelligent respect, replaced and enlarged the measuring that the circuit made up, control circuit by digital logical circuit, operation originally to a great extent, use very extensivly. But because it have system halted, procedure run critical defect of flying etc, make it limit in a lot of important application of occasion. A lot of technology inanti-interference , for example set up the software trap, add thehardware to guard the gate in dog's circuit etc, can make this problem havebetter settlement, but still the existing problem: ① Guard the gate dog at the movement, mean and appear mistake already and run some time, this is not allowed in some occasions; ②Procedure appear circulation mistake very much sometimes, but just guard the gate dog control link include and enter, adopt and guard the gate as to such a mistake dog unable to discern; ③In measure and control cycle among the long system, one-chip computer spend wait for the peripheral hardware a large amount of time, will be interfered too when carry out and wait for the order. To these situations, we have tried the method restored to the throne voluntarily in practice, alternate pulse of adopting etc or restore to the throne waking according to external terms to the one-chip computer up. After being restored to the throne each time, the one-chip computer carries out the corresponding procedure, enters dormancy in time after finishing carrying out the task, wait to be restored to the throne nextly. Have solved above-mentioned problems well with this method , and has got better result in the agricultural voltage transformer comprehensive protector experiment. Now take 51 serial one-chip computers as an example and probe into the concrete principle and implementation method, restored to the throne the signal as the high level.1.A principle and implementation method1.1 Restored to the throne the law regularly unconditionallyUse timer, special-purpose clock chip or other pulse generator, produce signal of restoring to the throne regularly according to interval that set for. This kind of method is especially suitable for the measuring instrument. In not running actually, sample the analog quantity of introduction with A/D converter often, then store showing. This course is very fast, but steady for reading, the data per second are only upgraded 1 -2 times, a large amount of time of CPU is used for waiting. Let CPU carry out and enter dormancy directly after the task , restore to the throne and wake by external world up It carry out the next operation, this is to restore to the throne the law regularly In this way can makeanti-interference ability strengthen greatly , have 2 points mainly: ①. At the dormancy, procedure stop run, can appear PC indicator disorderly procedure that causes run and fly. Work time in dormancy proportion 1:9, that is to say 1 s have 0.1 time of s used for measuring, sending off showing, there is time dormancy of 0.9s, the probability that the procedure is interfered is 1/10 while running at full speed, whole anti-interference ability raise by 10 times. ② Because every 1s is restored to the throne once unconditionally, once present the system halted during a job, can certainly resume when restored to the throne next time. As to only instrument that show, some reading mistake that 1s appear accidentally there is no memory to the next measurement, be could bear , belong to “pass” mistake. This kind is restored to the throne the advantage of dog's circuit for guarding the gate regularly, first, change waiting time into a dormancy state, time to shorten and may be interfered; Second, avoided happenning that the dog controls the death circulation of the link to include guarding the gate.1.2 The external condition is restored to the throne the lawSome arrival that export or measure is controlled by the outside. For instance, the hot form. of heating, rotate the pulse produced and calculate heat by hot water water wheels, there is no hot water to flow, there is no heat to export, CPU only need in fact keep number value, do not need to count. Can imagine hot water water wheels rotate when parking warm , CPU idle in will it be will it be one season autumn spring and summer, If let dormancy its , measure have water wheels pulse constantly,anti-interference ability can strengthen greatly. So, so long as link up the restoring to the throne of the pulse of the water wheels and CPU, the water wheels rotate a circle each time, CPU is restored to the throne once, hot form. can work normally , this is restored to the throne the law by the external condition . Similar application have half electron kilowatt-hour meter , go on one count just when the machinery degree wheels and transfers to a circle, users do not need the electricity, CPU has beenknowing the dormancy all the time . The restoring to the throne in the interval not to be regular, but confirmed according to the external condition of this method. In some occasions, the time of the dormancy will be very long, very effective to improving anti-interference ability.2 .The hardware realizes the main point2.1 Restored to the throne regularly unconditionallyGenerally have 2 kinds of methods. ① Use theitimer or thespecial-purpose clock chip to be restored to the throne. Fig1, in order to use the timing circuit that 555 circuit makes up; Can use the clock chips of X1126 ,etc too , wake CPU up with the alarm signal after setting up warning time. This kind of method is suitable when the long interval is made, can also follow the result of this operation ,determine to wake time up in alarm next time temporarily, very flexible and convenient. ②The signal of using the system to be inherent is as reducing the pulse regularly. Use 50Hz worker power make reducing after having a facelift frequently, already omit the timer, gathered the corresponding signal for the phase place which measured the electric current signal at the same time, as Fig. 2 shows.2.2 External conditions are restored to the throneSend external condition pulse to and is restored to the throne the end son after having a facelift. To that above-mentioned water wheels or the ammeter spend a pulse produced, can use Schmitt's trigger to have a facelift; For writing down the instrument of the biggest or minimum,can use the window comparator. In order to realize the electronization that is regulated,can use the electronic electric potential device, establish upper and lower limits with the order of the one-chip computer.2.3 Reduce cycle and restored to the throne the high electricity at ordinary timesIn Fig3, restored to the throne the signal during high level Tr, the one-chip computer is in the state of restoring to the throne, the procedure does not run, anti-interference ability is the strongest; After the high level, the one-chip computer begins to hold the conduct procedure. That is to say, are restored to the throne and suitable for the time that the procedure carries out during the low level Td of the signal, this time should be greater than the execution cycle of the procedure each time. It is restore to the throne cycle and restore to the throne high level of signal take empty than very much important to choose rationally. As to simple to show instrument, restore to the throne cycle determine data break cycle, low electricity is it measure, hancl over all time shown to greater than to want at ordinary times; Otherwise, cant present forever the mistake of the intact executive program.Monolithic integrated circuit in Ts and Tr period all can effectively the antijamming, but is best the unnecessary time arrangement in Tr. When the program time is long, when as far as possible the request reduces Tr, may join the differentiating circuit, like chart 1 center C30, R26, D9.2.4 Treatment of output end sons(1) Restore to the throne straight pulseDuring all I/O mouth of one-chip computer turn into the high level when restoring to the throne. That is to say output for low pin normally, will according to restore to the throne cycle appear the width for the straight pulse of Tr. This straight pulse will influence the normal output, 2 methods are dealt with: ① Connect in parallel electric capacity suppress , capacity confirm according to Tr time that restore to the throne on the son in end. Reducing Tr can be reduced and connected the electric capacity in parallel. ② It is invalid to design the peripheral circuit into the high level. (2) Fault-tolerantChoose the capacity that the output end connects the electric capacity in parallel fault-tolerantly and properly, can realize fault-tolerant control. Reduced cycle in a certain, because interfered exporting the wrong level. Because the keeping function of electric capacity, can't still enable exporting the change to the valid level within this cycle; Next cycle , the mistake is corrected. So, so long as does not make mistakes in 2 cycles in succession, it is very fault-tolerant to export Certainly, this kind of method will make the normal output change lag behind for one cycle, just really reflect the output end son.2.5 has the electricity to measure and restore to the throne manuallySome system is it make some initialize and operate to want at electricity for the first time. Restored to the throne and already become the beginning condition of normal running each time while adopting the way of restoring to the throne to run , it is unable to distinguish and have the electricity for the first time. In some pin connects the electric capacity of one ljIF to the ground, measure this pin after being restored to the throne, if low level to have electricity for the first time. Give system set up one restore to the throne button, that is to say a common one manual to restore to the throne, this button is not joined and being restored to the throne in the end, is connected in parallel in the electric capacity both ends to the ground of above-mentioned pins.3. The software realizes the main point3.1 is it resume with zero clearing RAM to outputRestore to the throne the last all pin turn high level into , is it should taKe place unnecessary change for low pin to make regularly, so, should resume the state.of all pins immediately after being restored to the throne. There are 2 kinds of methods : ① Analyse and judge immediately after being restored to the throne this time, provide the state of the pin according to the need; ② In being RAM it is the last last state that come down,these RAMs when restored.To the throne regularly can the zero clearing one; But electricity or manual to rstore to the throne when pushing in conformity with zero clearing, is it embody to want when the software is worked outing at the beginning. If calculate time allows, try one's best to take method 1. Restore to the throne cycle probability made mistakes to calculate very little, according to 2 for the 2nd time in succession. 4 output end son that narrate connect treatment method of electric capacity in parallel, can reach kind anti-interference result very.3.2 realizes crossing over and is restored to the throne alternate time sequenceregularly to controlWork in way of restoring to the throne now, start anew and carry out the same procedure repeatedly each time. Can be divided into 2 kinds of situations: ① As to simple to show instrument, carry on measurement ,send off showing after being restored to the throne each time, have causality between restoring to the throne twice . need is it switch over to the dormancy to waiting original only. Should pay attention to,measurement, give total time used to show is it is it restore to the throne low electricity at ordinary times to smaller than to want, otherwise can't present forever the mistake of the intact executive program. ② For having application that time sequence controlled , after being restored to the throne each time , should check first that see the sign left last cycle , in order to determine what is done this cycle . That is to say every is it restore to the throne operation of cycle to stride , by is it transmit to indicate all, these indicate while leaving in inside RAM , the zero clearing only when have the electricity for the first time. For example, the protecting synthetically device of above-mentioned voltage transformer , is restored to the throne regularly according to the interval of 20ms. It reaches the normal working state through, certain movement order after having the electricity, such as Fig. 4; Write a part of the procedure of the software according to this movement, such as Fig.5.In 4 Fig, act as person who protect the beginning at the electricity, is it transmit power 0 to try at first. 5s, points out and transmits power soon; Transmit power formally after waiting for 30s. It is start-up time in 1s after transmitting power, does not measure the electric current. Start after finishing, if all going well, the location is put" normal sign ", person who protect restore to the throne cycle enter normal running in the next one. Try 0 that transmits power. 5s is it is it realize to count once restoring to the throne to delay time, restore to the throne time 20ms each time. At having electricity for the first time, make all zero clearing to inside RAM, make it is it time Ts to transmit power not to try =Dormancy after 25. After restoring to the throne, is it have electric pin to have electricity for the first time already, is it is it is it is it time the measuring of Ts to transmit power to try to get to go on to measure next time. If Ts * 0, is it in is it prolong period to transmit power, is it enter dormancy after the 1 to reduce Ts to prove. Act as Ts-1 = 0, the course which waited for 30s that should enter and lose electrical power. Just when Ts decreases progressively to 0, make it is it indicate to wait for not to lose electrical power Td =1500. When the procedure is restored to the throne beginning again, measure to Ts =0 but Td * 0, is it is it is it transmit power to try to cross already to indicate, at is it wait for the course of 30s to lose electrical power now. In this way, the whole process is transmitted each other by such these parameters as Tr, Td , Ts etc, go on step by step.Result:Conclusion Anti-interference is an important problem in an electronic design, especially Important in the one-chip computer. This is because the one-chip computer has procedures to run particularity that flies, the consequence that it is interfered may be the system halted, may send out various kinds of mistakes or illegal movements before the system halted too, make the whole system produce the mortality mistake. So, only guarantee it is not enough yet for one-chip computer not to crash, study how to reduce the risk interfered, it can befault-toierant how is it after and make mistakes. This text is it act as some exploration from two these to try hard, hope these elementary opinions can play some function of casting a brick to attract jade, helpful to everybody; Hope too every colleague explore together, improve our design level together.在一个芯片的计算机恢复到休眠---宝座的运作方式,提高抗干扰能力摘要:介绍了一种使用休眠,恢复到在theoperation方式的宝座,提高了单芯片计算机抗干扰能力的方法,分析其应用范围,提供和使用的电路concretly;结合实例,分析的运作方式下,这些种类的硬件和软件的设计特点。

单片机的外文文献及中文翻译

单片机的外文文献及中文翻译

单片机的外文文献及中文翻译一、外文文献Title: The Application and Development of SingleChip Microcontrollers in Modern ElectronicsSinglechip microcontrollers have become an indispensable part of modern electronic systems They are small, yet powerful integrated circuits that combine a microprocessor core, memory, and input/output peripherals on a single chip These devices offer significant advantages in terms of cost, size, and power consumption, making them ideal for a wide range of applicationsThe history of singlechip microcontrollers can be traced back to the 1970s when the first microcontrollers were developed Since then, they have undergone significant advancements in technology and performance Today, singlechip microcontrollers are available in a wide variety of architectures and capabilities, ranging from simple 8-bit devices to complex 32-bit and 64-bit systemsOne of the key features of singlechip microcontrollers is their programmability They can be programmed using various languages such as C, Assembly, and Python This flexibility allows developers to customize the functionality of the microcontroller to meet the specific requirements of their applications For example, in embedded systems for automotive, industrial control, and consumer electronics, singlechip microcontrollers can be programmed to control sensors, actuators, and communication interfacesAnother important aspect of singlechip microcontrollers is their low power consumption This is crucial in batterypowered devices and portable electronics where energy efficiency is of paramount importance Modern singlechip microcontrollers incorporate advanced power management techniques to minimize power consumption while maintaining optimal performanceIn addition to their use in traditional electronics, singlechip microcontrollers are also playing a significant role in the emerging fields of the Internet of Things (IoT) and wearable technology In IoT applications, they can be used to collect and process data from various sensors and communicate it wirelessly to a central server Wearable devices such as smartwatches and fitness trackers rely on singlechip microcontrollers to monitor vital signs and perform other functionsHowever, the design and development of systems using singlechip microcontrollers also present certain challenges Issues such as realtime performance, memory management, and software reliability need to be carefully addressed to ensure the successful implementation of the applications Moreover, the rapid evolution of technology requires developers to constantly update their knowledge and skills to keep up with the latest advancements in singlechip microcontroller technologyIn conclusion, singlechip microcontrollers have revolutionized the field of electronics and continue to play a vital role in driving technological innovation Their versatility, low cost, and small form factor make them an attractive choice for a wide range of applications, and their importance is expected to grow further in the years to come二、中文翻译标题:单片机在现代电子领域的应用与发展单片机已成为现代电子系统中不可或缺的一部分。

单片机英文文献 免费

单片机英文文献 免费

单片机英文文献Principle of MCUSingle-chip is an integrated on a single chip a complete computer system. Even though most of his features in a small chip, but it has a need to complete the majority of computer components: CPU, memory, internal and external bus system, most will have the Core. At the same time, such as integrated communication interfaces, timers, real-time clock and other peripheral equipment. And now the most powerful single-chip microcomputer system can even voice, image, networking, input and output complex system integration on a single chip.Also known as single-chip MCU (Microcontroller), because it was first used in the field of industrial control. Only by the single-chip CPU chip developed from the dedicated processor. The design concept is the first by a large number of peripherals and CPU in a single chip, the computer system so that smaller, more easily integrated into the complex and demanding on the volume control devices. INTEL the Z80 is one of the first design in accordance with the idea of the processor, From then on, the MCU and the development of a dedicated processor parted ways.Early single-chip 8-bit or all of the four. One of the most successful is INTEL's 8031, because the performance of a simple and reliable access to a lot of good praise. Since then in 8031 to develop a single-chip microcomputer system MCS51 series. Based on single-chip microcomputer system of the system is still widely used until now. As the field of industrial control requirements increase in the beginning of a 16-bit single-chip, but not ideal because the price has not been very widely used. After the 90's with the big consumer electronics product development, single-chip technology is a huge improvement. INTEL i960 Series with subsequent ARM in particular, a broad range of applications, quickly replaced by 32-bit single-chip 16-bit single-chip high-end status, and enter the mainstream market. Traditional 8-bit single-chip performance has been the rapid increase in processing power compared to the 80's to raise a few hundred times. At present, the high-end 32-bit single-chip frequency over 300MHz, the performance of the mid-90's close on the heels of a special processor, while the ordinary price of the model dropped to one U.S. dollars, the most high-end models, only 10 U.S. dollars. Contemporary single-chip microcomputer system is no longer only the bare-metal environment in the development and use of a large number of dedicated embedded operating system is widely used in the full range of single-chip microcomputer. In PDAs and cell phones as the core processing of high-end single-chip or even a dedicated direct access to Windows and Linux operating systems.More than a dedicated single-chip processor suitable for embedded systems, so it was up to the application. In fact the number of single-chip is the world's largest computer. Modern human life used in almost every piece of electronic and mechanical products will have a single-chip integration. Phone, telephone, calculator, home appliances, electronic toys, handheld computers and computer accessories such as a mouse in the Department are equipped with 1-2 single chip. And personal computers also have a large number of single-chip microcomputer in the workplace. Vehicles equipped with more than 40 Department of the general single-chip, complex industrial control systems and even single-chip may have hundreds of work at the same time! SCM is not only far exceeds the number of PC and other integrated computing, even more than the number of human beings.Hardwave introductionThe 8051 family of micro controllers is based on an architecture which is highly optimized for embedded control systems. It is used in a wide variety of applications from military equipment to automobiles to the keyboard on your PC. Second only to the Motorola 68HC11 in eight bit processors sales, the 8051 family of microcontrollers is available in a wide array of variations from manufacturers such as Intel, Philips, and Siemens. These manufacturers have added numerous features and peripherals to the 8051 such as I2C interfaces, analog to digital converters, watchdog timers, and pulse width modulated outputs. Variations of the 8051 with clock speeds up to 40MHz and voltage requirements down to 1.5 volts are available. This wide range of parts based on one core makes the 8051 family an excellent choice as the base architecture for a company's entire line of products since it can perform many functions and developers will only have to learn this one platform.The basic architecture consists of the following features:·an eight bit ALU·32 descrete I/O pins (4 groups of 8) which can be individually accessed·two 16 bit timer/counters·full duplex UART· 6 interrupt sources with 2 priority levels·128 bytes of on board RAM·separate 64K byte address spaces for DA TA and CODE memoryOne 8051 processor cycle consists of twelve oscillator periods. Each of the twelve oscillator periods is used for a special function by the 8051 core such as op code fetches and samples of the interrupt daisy chain for pending interrupts. The time required for any 8051 instruction can be computed by dividing the clock frequency by 12, inverting that result and multiplying it by the number of processor cycles required by the instruction in question. Therefore, if you have a system which is using an 11.059MHz clock, you can compute the number of instructions per second by dividing this value by 12. This gives an instruction frequency of 921583 instructions per second. Inverting this will provide the amount of time taken by each instruction cycle (1.085 microseconds).单片机原理单片机是指一个集成在一块芯片上的完整计算机系统。

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Structure and function of the MCS-51 seriesThe MCS-51 series one-chip computer MCS-51 is a name of a piece of one-chip computer series which Intel Company produces. This company introduced 8 top-grade one-chip computers of MCS-51 series in 1980 after introducing 8 one-chip computers of MCS-48 series in 1976. It belong to a lot of kinds this line of one-chip computer the chips have,such as 8051, 8031, 8751, 80C51BH, 80C31BH,etc., their basic composition, basic performance and instruction system are all the same. 8051 daily representatives- 51 serial one-chip computers .51系列单片机是由英特尔公司生产的的单片机产品。

该家公司在1976年发行了8位MCS-48系列。

然后又在在1980年推出了高8位的MCS-51系列单片机。

它属于这一类型很多行一个芯片的电脑芯片都如8051、8031、8751、80c51bh,80c31bh等,其基本组成、性能和基本教学制度,都是一样的. 8051通常是51系列的代表。

An one-chip computer system is made up of several following parts: ( 1) One microprocessor of 8 (CPU). ( 2) At slice data memory RAM (128B/256B),it use not depositting not can reading /data that write, such as result not middle of operation, final result and data wanted to show, etc. ( 3) Procedure memory ROM/EPROM (4KB/8KB ), is used to preserve the procedure , some initial data and form in slice. But does not take ROM/EPROM within some one-chip computers, such as 8031 , 8032, 80C ,etc.. ( 4) Four 8 run side by side I/O interface P0 four P3, each mouth can use as introduction , may use as exporting too. ( 5) Two timer / counter, each timer / counter may set up and count in the way, used to count to the external incident, can set up into a timing way too, and can according to count or result of timing realize the control of the computer. ( 6) Five cut off cutting off the control system of the source . ( 7) One all duplexing serial I/O mouth of UART (universal asynchronousreceiver/transmitter (UART) ), is it realize one-chip computer or one-chip computer and serial communication of computer to use for. ( 8) Stretch oscillator and clock produce circuit, quartz crystal finely tune electric capacity need outer. Allow oscillation frequency as 12 megahertas now at most. Every the above-mentioned part was joined through the inside data bus .Among them, CPU is a core of the one-chip computer, it is the control of the computer and command centre, made up of such parts as arithmetic unit and controller , etc.. The arithmetic unit can carry on 8 persons of arithmetic operation and unit ALU of logic operation while including one, the 1 storing device temporarilies of 8, storing device 2 temporarily, 8's accumulation device ACC, register B and procedure state register PSW, etc. Person who accumulate ACC count by 2 input ends entered of checking etc. temporarily as one operation often, come from person who store 1 operation is it is it make operation to go on to count temporarily , operation result and loopback ACC with another one. In addition, ACC is often regarded as the transfer station of data transmission on 8051 inside . The same as general microprocessor, it is the busiest register. Help remembering that agreeing with A expresses in the order. The controller includes the procedure counter , the order is depositted, the order decipher, the oscillator and timing circuit, etc. The procedure counter is made up of counter of 8 for two, amounts to 16. It is a byte address counter of the procedure in fact, the content is the next IA that will carried out in PC. The content which changes it can change the direction that the procedure carries out . Shake the circuit in 8051 one-chip computers, only need outer quartz crystal and frequency to finely tune the electric capacity, its frequency range is its 12MHZ of 1.2MHZ. This pulse signal, as 8051 basic beats of working, namely the minimum unit of time. 8051 is the same as other computers, the work in harmony under the control of the basic beat, just like an orchestra according to the beat play that is commanded.There are ROM (procedure memory , can only read ) and RAM in 8051 slices (data memory, can is it can write ) two to read, they have each independent memory address space, dispose way to be the same with general memory of computer. Procedure 8051 memory and 8751 slice procedure memory capacity 4KB, address begin from 0000H, used for preserving the procedure and form constant. Data 8051- 8751 8031 of memory data memory 128B, address false 00FH, use for middle result to deposit operation, the data are stored temporarily and the data are buffered etc.. In RAM of this 128B, there is unit of 32 byteses that can be appointed as the job register, this and general microprocessor is different, 8051 slice RAM and job register rank one formation the same to arrange the location. It is not very the same that the memory of MCS-51 series one-chip computer and general computer disposes the way in addition. General computer for first address space, ROM and RAM can arrange in different space within the range of this address at will, namely the addresses of ROM and RAM, with distributing different address space in a formation. While visiting the memory, corresponding and only an address Memory unit, can ROM, it can be RAM too, and by visiting the order similarly. This kind of memory structure is called the structure of Princeton. 8051 memories are divided into procedure memory space and data memory space on the physics structure, there are four memory spaces in all: The procedure stores in one and data memory space outside data memory and one in procedure memory space and one outside one, the structure forms of this kind of procedure device and data memory separated form data memory, called Harvard structure. But use the angle from users, 8051 memory address space is divided into three kinds: (1) In the slice, arrange blocks of FFFFH , 0000H of location , in unison outside the slice (use 16 addresses). (2) The data memory address space outside one of 64KB, the address is arranged from 0000H 64KB FFFFH (with 16 addresses ) too to the location. (3) Data memory address space of 256B(use 8 addresses). Three above-mentioned memory space addresses overlap, for distinguishing and designing the order symbol of different data transmission in the instruction system of 8051: CPU visit slice, ROM order spend MOVC , visit block RAM order uses MOVX outside the slice, RAM order uses MOV to visit in slice.8051 one-chip computer have four 8 walk abreast I/O port, call P0, P1, P2 and P3. Each port is 8 accurate two-way mouths, accounts for 32 pins altogether. Every one I/O line can be used as introduction and exported independently. Each port includes a latch (namely special function register ), one exports the driver and a introduction buffer . Make data can latch when outputting, data can buffer when making introduction , but four function of passway these self-same. Expand among the system of memory outside having slice, four port these may serve as accurate two-way mouth of I/O in common use. Expand among the system of memory outside having slice, P2 mouth see high 8 address off; P0 mouth is a two-way bus, send the introduction of 8 low addresses and data / export in timesharing8051单片机有4组并排的8位I/O口,叫做P0, P1, P2 和P3.每一个端口都是8位准双向口,共占32根引脚。

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