EDA课后答案(适用于《EDA技术及应用》)

1.1、设计集成计数器74161，设计要求如下：
4-BIT BINARY UP COUNTER WITH SYNCHRONOUS LOAD AND ASYNCHRONOUS CLEAR NOTE
INPUTS： CLK LDN CLRN D C B A
OUTPUTS：QD QC QB QA RCO
*RCO = QD & QC & QB & QA
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CNT4 IS
PORT(
CLK,LDN,CLRN : IN STD_LOGIC;
D,C,B,A : IN STD_LOGIC;
CARRY : OUT STD_LOGIC;
QD,QC,QB,QA : OUT STD_LOGIC
);
END;
ARCHITECTURE A OF CNT4 IS
SIGNAL DATA_IN: STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
DATA_IN<=D&C&B&A;
PROCESS(DATA_IN,CLK,LDN,CLRN)
VARIABLE CNT:STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
IF CLRN='0' THEN
CNT:=(OTHERS=>'0');
ELSIF CLK'EVENT AND CLK='1' THEN
IF LDN='0' THEN
CNT:=DATA_IN;
ELSE
CNT:=CNT+1;
END IF;
END IF;
CASE CNT IS
WHEN "1111"=> CARRY<='1';
WHEN OTHERS=> CARRY<='0';
END CASE;
QA<=CNT(0);
QB<=CNT(1);
QC<=CNT(2);
QD<=CNT(3);
END PROCESS;
END A;
1.2、设计一个通用双向数据缓冲器，要求缓冲器的输入和输出端口的位数可以由参数决定。

设计要求：N BIT数据输入端口A，B。

工作使能端口EN=0时双向总线缓冲器选通，
DIR=1，则A=B；反之B=A。

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY BIDIR IS
GENERIC(N:INTEGER:=8);
PORT( A,B : INOUT STD_LOGIC_VECTOR(N-1 DOWNTO 0);
EN,DIR : IN STD_LOGIC);
END;
ARCHITECTURE A OF BIDIR IS
BEGIN
PROCESS(EN,DIR)
BEGIN
IF EN='0' THEN
A<=(OTHERS=>'Z');
B<=(OTHERS=>'Z');
ELSE
IF DIR='1' THEN
B<=A;
ELSE
A<=B;
END IF;
END IF;
END PROCESS;
END A;
2.1、用VHDL语言编程实现十进制计数器，要求该计数器具有异步复位、同步预置功能。

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY CNT_10_2 IS
PORT(
CLK,CLR : IN STD_LOGIC;
COUNT : OUT STD_LOGIC
);
END;
ARCHITECTURE A OF CNT_10_2 IS
SIGNAL CNT_10 : INTEGER RANGE 0 TO 10;
BEGIN
PROCESS(CLK,CLR)
BEGIN
IF CLR='1' THEN
CNT_10<=0;
ELSIF CLK'EVENT AND CLK='1' THEN
CNT_10<=CNT_10+1;
IF CNT_10=9 THEN
CNT_10<=0;
COUNT<='1';
ELSE
COUNT<='0';
END IF;
END IF;
END PROCESS;
END A;
2.2、设计实现一位全减器。

行为描述: F_SUB4
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY F_SUB4 IS
PORT(
A,B,CIN : IN STD_LOGIC;
DIFF,COUT : OUT STD_LOGIC
);
END;
ARCHITECTURE A OF F_SUB4 IS
BEGIN
DIFF<=A XOR B XOR CIN;
COUT<=(NOT A AND B) OR (NOT A AND CIN) OR (B AND CIN); END A;
数据流描述F_SUB1
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY F_SUB1 IS
PORT(
A,B :IN STD_LOGIC;
CIN :IN STD_LOGIC;
DIFF,COUT : OUT STD_LOGIC
);
END;
ARCHITECTURE A OF F_SUB1 IS
SIGNAL S :STD_LOGIC_VECTOR(2 DOWNTO 0); BEGIN
S<=CIN&A&B;
PROCESS(A,B,CIN)
BEGIN
CASE S IS
WHEN "000" => DIFF<='0';COUT<='0'; WHEN "001" => DIFF<='1';COUT<='1'; WHEN "010" => DIFF<='1';COUT<='0'; WHEN "011" => DIFF<='0';COUT<='0'; WHEN "100" => DIFF<='1';COUT<='1'; WHEN "101" => DIFF<='0';COUT<='1'; WHEN "110" => DIFF<='0';COUT<='0'; WHEN "111" => DIFF<='1';COUT<='1'; WHEN OTHERS=> DIFF<='X';COUT<='X'; END CASE;
END PROCESS;
END A;
数据流描述F_SUB2
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY F_SUB2 IS
PORT(
A,B,CIN : IN STD_LOGIC;
DIFF,COUT : OUT STD_LOGIC
);
END;
ARCHITECTURE A OF F_SUB2 IS
SIGNAL S :STD_LOGIC_VECTOR(2 DOWNTO 0); SIGNAL C :STD_LOGIC_VECTOR(1 DOWNTO 0); BEGIN
S<=CIN&A&B;
DIFF<=C(1);
COUT<=C(0);
C<="00" WHEN S="000" ELSE
"11" WHEN S="001" ELSE
"10" WHEN S="010" ELSE
"00" WHEN S="011" ELSE
"11" WHEN S="100" ELSE
"01" WHEN S="101" ELSE
"00" WHEN S="110" ELSE
"11" ;
END A;
数据流描述F_SUB3
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY F_SUB3 IS
PORT(
A,B,CIN : IN STD_LOGIC;
DIFF,COUT : OUT STD_LOGIC
);
END;
ARCHITECTURE A OF F_SUB3 IS
SIGNAL S :STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL C :STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN
S<=CIN&A&B;
DIFF<=C(1);
COUT<=C(0);
WITH S SELECT
C<="00" WHEN "000",
"11" WHEN "001",
"10" WHEN "010",
"00" WHEN "011",
"11" WHEN "100",
"01" WHEN "101",
"00" WHEN "110",
"11" WHEN OTHERS;
END A;
3.1、阅读教材P181页，例[5-55]并回答下列问题：
（1）、该程序的功能是什么？
（2）、请写出该程序所有端口的功能描述。

3.2、试描述一个十进制——BCD码编码器，输出使能为低电平有效。

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY BIN_BCD IS
PORT(
BIN : IN INTEGER RANGE 0 TO 20;
--ENA : IN STD_LOGIC;
BCD_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END;
ARCHITECTURE A OF BIN_BCD IS
BEGIN
BINARY_BCD : BLOCK
BEGIN
BCD_OUT <= "00000000" WHEN BIN = 0 ELSE
"00000001" WHEN BIN = 1 ELSE
"00000010" WHEN BIN = 2 ELSE
"00000011" WHEN BIN = 3 ELSE
"00000100" WHEN BIN = 4 ELSE
"00000101" WHEN BIN = 5 ELSE
"00000110" WHEN BIN = 6 ELSE
"00000111" WHEN BIN = 7 ELSE
"00001000" WHEN BIN = 8 ELSE
"00001001" WHEN BIN = 9 ELSE
"00010000" WHEN BIN = 10 ELSE
"00010001" WHEN BIN = 11 ELSE
"00010010" WHEN BIN = 12 ELSE
"00010011" WHEN BIN = 13 ELSE
"00010100" WHEN BIN = 14 ELSE
"00010101" WHEN BIN = 15 ELSE
"00010110" WHEN BIN = 16 ELSE
"00010111" WHEN BIN = 17 ELSE
"00011000" WHEN BIN = 18 ELSE
"00011001" WHEN BIN = 19 ELSE
"00100000" WHEN BIN = 20 ELSE
"00000000";
END BLOCK;
END A;
4.1、读教材P151页，例[5-32]的程序，并回答以下问题：
（1）请画出该程序所描述的电路结构图，要求标清楚每一个端口以及内部信号。

（串入/串出移位寄存器）
4.2、用VHDL语言设计一个能够实现任意整数进制的计数器。

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
--**********************************************
ENTITY FREQDV_N IS
GENERIC(N:INTEGER:=6);
PORT(
CLK :IN STD_LOGIC;
CLK_DIV : OUT STD_LOGIC
);
END;
ARCHITECTURE A OF FREQDV_N IS
SIGNAL CNT : INTEGER RANGE 0 TO N;
BEGIN
PROCESS(CLK)
BEGIN
IF RISING_EDGE(CLK) THEN
IF CNT=0 THEN
CNT<=N-1;
CLK_DIV<='1';
ELSE
CLK_DIV<='0';
CNT<=CNT-1;
END IF;
END IF;
END PROCESS;
END A;
5.1、设计一个序列信号发生器，要求能够循环输出序列“01101001”。

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY RS_1 IS
PORT(
CP,S,R : IN STD_LOGIC;
Q,NQ : OUT STD_LOGIC
);
END;
ARCHITECTURE A OF RS_1 IS
SIGNAL S1,R1,Q1,NQ1:STD_LOGIC;
BEGIN
S1<=S NAND CP;
R1<=R NAND CP;
Q1<=S1 NAND NQ1;
NQ1<=R1 NAND Q1;
Q<=Q1;
NQ<=NQ1;
END A;
5.2、设计一个带复位端、置位端、CP下降沿触发的JK触发器。

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY JKFF IS
PORT(
J,K,RST,CLR : IN BIT;
CLK : IN BIT;
Q,NQ : OUT BIT
);
END;
ARCHITECTURE A OF JKFF IS
SIGNAL Q_S,NQ_S : BIT;
BEGIN
PROCESS(J,K,RST,CLR,CLK)
BEGIN
IF RST='1' THEN
Q_S<='1';
NQ_S<='0';
ELSIF CLK'EVENT AND CLK='0' THEN
IF CLR='1' THEN
Q_S<='0';
NQ_S<='1';
ELSIF J='0' AND K='1' THEN
Q_S<='0';
NQ_S<='1';
ELSIF J='1' AND K='0' THEN
Q_S<='1';
NQ_S<='0';
ELSIF J='1' AND K='1' THEN
Q_S<=NOT Q_S;
NQ_S<=NOT NQ_S;
END IF;
ELSE
NULL;
END IF;
Q<=Q_S;
NQ<=NQ_S;
END PROCESS;
END A;
6.1、用VHDL语句描述一个三态输出的双4选一的数据选择器，其地址信号共用，且各有一个低电平有效的使能端。

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY DUAL_MUX_41 IS
PORT(
A,B,C,D : IN STD_LOGIC;
ENA_N,ENB_N : IN STD_LOGIC;
S : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
OUTA,OUTB : OUT STD_LOGIC
);
END;
ARCHITECTURE A OF DUAL_MUX_41 IS
SIGNAL P,Q : STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
P<=ENA_N & S;
Q<=ENB_N & S;
WITH P SELECT
OUTA<=A WHEN "000",
B WHEN "001",
C WHEN "010",
D WHEN "011",
'Z' WHEN OTHERS;
WITH Q SELECT
OUTB<=A WHEN "000",
B WHEN "001",
C WHEN "010",
D WHEN "011",
'Z' WHEN OTHERS;
END A;
6.2、用并行信号赋值语句实现3—8译码器。

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY DECODER38 IS
PORT(A,B,C,G1,G1A,A2B:IN STD_LOGIC;
Q:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END DECODER38;
ARCHITECTURE BEHAVE38 OF DECODER38 IS
SIGNAL INDA: STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
INDA<=C&B&A;
PROCESS(INDATA,G1,G2A,G2B)
BEGIN
IF(G1='1' AND G2A='0' AND G2B='0') THEN
CASE INDA IS
WHEN "000"=>Q<="11111110";
WHEN "001"=>Q<="11111101";
WHEN "010"=>Q<="11111011";
WHEN "011"=>Q<="11110111";
WHEN "100"=>Q<="11101111";
WHEN "101"=>Q<="11011111";
WHEN "110"=>Q<="10111111";
WHEN "111"=>Q<="01111111";
WHEN OTHERS =>Q<="XXXXXXXX";
END CASE;
ELSE
Q<="11111111";
END IF;
END PROCESS;
END BEHAVE38;
7.1、用并行信号赋值语句实现8选一数据选择器，要求有工作使能
端。

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY MUX8 IS
PORT(D0,D1,D2,D3,D4,D5,D6,D7:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S0,S1,S2:IN STD_LOGIC; Q:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END MUX8;
ARCHITECTURE BEHAVE OF MUX8 IS
SIGNAL S: STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
S <=S2&S1&S0;
WITH S SECLECT
D <=D0 WHEN "000",
D1 WHEN "001",
D2 WHEN "010",
D3 WHEN "011",
D4 WHEN "100",
D5 WHEN "101",
D6 WHEN "110",
D7 WHEN "111",
‘X’WHEN OTHERS;
END BEHAVE;
7.2、用VHDL语言设计实现输出占空比为50%的1000分频器。

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY DIV_1000 IS
PORT(
CLK ,CLR: IN STD_LOGIC;
DIV : OUT STD_LOGIC
);
END;
ARCHITECTURE A OF DIV_1000 IS
SIGNAL Q : STD_LOGIC;
BEGIN
DIV<=Q;
PROCESS(CLK,CLR)
VARIABLE CNT : INTEGER RANGE 0 TO 499;
BEGIN
IF CLR='1' THEN
CNT:=0; Q<='0';
ELSIF RISING_EDGE(CLK) THEN
IF CNT=499 THEN
CNT:=0;
Q<=NOT Q;
ELSE
CNT:=CNT+1;
END IF;
END IF;
END PROCESS;
END A;
8.1、设计一个一位全减器。

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY F_SUB3 IS
PORT(
A,B,CIN : IN STD_LOGIC;
DIFF,COUT : OUT STD_LOGIC
);
END;
ARCHITECTURE A OF F_SUB3 IS
SIGNAL S :STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL C :STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN
S<=CIN&A&B;
DIFF<=C(1);
COUT<=C(0);
WITH S SELECT
C<="00" WHEN "000",
"11" WHEN "001",
"10" WHEN "010",
"00" WHEN "011",
"11" WHEN "100",
"01" WHEN "101",
"00" WHEN "110",
"11" WHEN OTHERS;
END A;
8.2、用元件例化语句描述一个四位的全减器。

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY F_SUB4_1 IS
PORT(
A,B : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
CIN : IN STD_LOGIC;
DIFF: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
COUT: OUT STD_LOGIC
);
END;
ARCHITECTURE A OF F_SUB4_1 IS
COMPONENT F_SUB1 IS
PORT(
A,B,CIN : IN STD_LOGIC;
DIFF,COUT : OUT STD_LOGIC
);
END COMPONENT;
SIGNAL C :STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
U1: F_SUB1 PORT MAP(A(0),B(0),CIN,DIFF(0),C(0));
U2: F_SUB1 PORT MAP(A(1),B(1),C(0),DIFF(1),C(1));
U3: F_SUB1 PORT MAP(A(2),B(2),C(1),DIFF(2),C(2));
U4: F_SUB1 PORT MAP(A(3),B(3),C(2),DIFF(3),C(3));
COUT<=C(3);
END A;
9.1、利用生成语句描述一个由N个一位全减器构成的N位减法器，N 的默认值为4。

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY F_SUB4_2 IS
GENERIC (N : INTEGER := 4);
PORT(
A,B : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0);
CIN : IN STD_LOGIC;
DIFF: OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0);
COUT: OUT STD_LOGIC
);
END;
ARCHITECTURE A OF F_SUB4_2 IS
COMPONENT F_SUB1 IS
PORT(
A,B,CIN : IN STD_LOGIC;
DIFF,COUT : OUT STD_LOGIC
);
END COMPONENT;
SIGNAL C :STD_LOGIC_VECTOR(N DOWNTO 0);
BEGIN
C(0)<=CIN;
N1: FOR I IN 0 TO N-1 GENERATE
U1: F_SUB1 PORT MAP(A(I),B(I),C(I),DIFF(I),C(I+1));
END GENERATE;
COUT<=C(N);
END A;
9.2、设计一个模为60、具有异步复位、同步置数功能的8421码计数器。

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY COUNT_60 IS
CLK ,CLR,PST: IN STD_LOGIC;
A : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
Q : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
CO: OUT STD_LOGIC
);
END;
ARCHITECTURE A OF COUNT_60 IS
SIGNAL CNT: STD_LOGIC_VECTOR(5 DOWNTO 0);
BEGIN
Q<=CNT;
PROCESS(CLK,CLR,PST,A)
BEGIN
IF CLR='1' THEN
CNT<=(OTHERS=>'0');
CO<='0';
ELSIF RISING_EDGE(CLK) THEN
IF PST='1' THEN
CNT<=A;
ELSIF CNT=59 THEN
CNT<=(OTHERS=>'0');
CO<='1';
ELSE
CNT<=CNT+1;
CO<='0';
END IF;
END IF;
END PROCESS;
END A;
10.1、用VHDL描述一个单稳态触发器，定时时间由类属参数决定。

该触发器有一个触发信号输入端A，上升沿触发。

输出端为Y。

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY MONO_TRIGGER_TOP IS
PORT(
TRIGGER_IN,CLK: IN STD_LOGIC;
MONO_OUT : OUT STD_LOGIC
);
END;
ARCHITECTURE A OF MONO_TRIGGER_TOP IS
COMPONENT MONO_TRIGGER IS
GENERIC(N:INTEGER:=5;
M:INTEGER:=10);
A,CLK: IN STD_LOGIC;
Y : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
U0: MONO_TRIGGER GENERIC MAP(N=>6,M=>10)
PORT MAP(A=>TRIGGER_IN,CLK=>CLK,Y=>MONO_OUT);
END A;
10.2、设计实现一个8—3优先编码器。

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY MONO_TRIGGER IS --非可重复触发单稳态触发器GENERIC(N:INTEGER:=5; --单稳态定时参数
M:INTEGER:=10); --定义定时参数取值范围PORT(
A,CLK: IN STD_LOGIC;
Y : OUT STD_LOGIC
);
END;
ARCHITECTURE A OF MONO_TRIGGER IS
TYPE STATE IS(ST0,ST1,ST2);
SIGNAL CURRENT_STATE,NEXT_STATE : STATE;
SIGNAL Q:STD_LOGIC;
BEGIN
REG:PROCESS(A,CLK)
BEGIN
IF CLK'EVENT AND CLK='1' THEN
CURRENT_STATE<=NEXT_STATE;
END IF;
END PROCESS;
COM:PROCESS(CURRENT_STATE,A)
BEGIN
CASE CURRENT_STATE IS
WHEN ST0 =>
IF A='0' THEN
NEXT_STATE<=ST0;
Y<='0';
ELSE
NEXT_STATE<=ST1;
END IF;
WHEN ST1 =>
IF Q='1' THEN
NEXT_STATE<=ST2;
Y<='0';
ELSE
NEXT_STATE<=ST1;
Y<='1';
END IF;
WHEN ST2 =>
IF A='1' THEN
NEXT_STATE<=ST2;
Y<='0';
ELSE
NEXT_STATE<=ST0;
Y<='0';
END IF;
WHEN OTHERS => NEXT_STATE<=ST0;
END CASE;
END PROCESS;
AUX_COUNT:PROCESS(CURRENT_STATE,CLK)
VARIABLE COUNT : INTEGER RANGE 0 TO M; BEGIN
IF CLK'EVENT AND CLK='1' THEN
IF CURRENT_STATE/=ST1 THEN
COUNT:=N;
ELSE
COUNT:=COUNT-1;
END IF;
END IF;
IF COUNT=0 THEN
Q<='1';
ELSE
Q<='0';
END IF;
END PROCESS;
END A;
10-19
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY CODE_PAN IS
PORT(
X,RST,CLK : IN STD_LOGIC;
Y : OUT STD_LOGIC
);
END;
ARCHITECTURE A OF CODE_PAN IS
SIGNAL Q :STD_LOGIC_VECTOR(6 DOWNTO 0);
BEGIN
PROCESS(CLK,X,RST)
BEGIN
IF RST='1' THEN
Q<=(OTHERS=>'0');
ELSIF CLK'EVENT AND CLK='1' THEN
Q(0)<=X;
Q(1)<=Q(0);
Q(2)<=Q(1);
Q(3)<=Q(2);
Q(4)<=Q(3);
Q(5)<=Q(4);
Q(6)<=Q(5);
END IF;
END PROCESS;
WITH Q SELECT
Y<='1' WHEN "1110010",
'0' WHEN OTHERS;
END A;
8-3优先编码器(when-else实现)：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY CODER IS
PORE(
D:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
OUTPUT:OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
);
END CODER;
ARCHITECTURE ART1 IS
BEGIN
OUTPUT<="000" WHEN D(7)='0' ELSE
"001" WHEN D(6)='0' ELSE
"010" WHEN D(5)='0' ELSE
"011" WHEN D(4)='0' ELSE
"100" WHEN D(3)='0' ELSE
"101" WHEN D(2)='0' ELSE
"110" WHEN D(1)='0' ELSE
"111";
END ART1;
3.5四选一多路选择器
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY MAX4_1 IS
PORT(A,B,C,D,S1,S2 : IN STD_LOGIC;
Y : OUT STD_LOGIC);
END ENTITY MAX4_1;
ARCHITECTURE HF1 OF MAX4_1 IS
SIGNAL SS : STD_LOGIC_VECTOR (0 TO 1);
BEGIN
SS<=S2&S1;
PROCESS(SS)
BEGIN
CASE SS IS
WHEN "00" => Y<=A;
WHEN "01" => Y<=B;
WHEN "10" => Y<=C;
WHEN "11" => Y<=D;
WHEN OTHERS => NULL;
END CASE;
END PROCESS;
END HF1;
3.6设计一个7人表决电路，参加表决者7人，同意为1，不同意为0，同意者过半则表决通过，绿指示灯亮；表决不通过则红指示灯亮。

设计思路：根据7人表决电路设计要求，7人中至少有4个通过才可以表决通过，故可以在程序中设置一个变量TEMP，使其在表决电路中遇1则加1，遇0则加0（设计中1表示通过，0表示不通过）。

当TEMP>=4时，表示表决通过，当TEMP<4时表决不通过。

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY VOTE7 IS
PORT (MEN:IN STD_LOGIC_VECTOR(6 DOWNTO 0);
OUTPUT: OUT BIT);
END VOTE7;
ARCHITECTURE BEHAVE OF VOTE7 IS
BEGIN
PROCESS(MEN)
VARIABLE TEMP: INTEGER RANGE 0 TO 7;
BEGIN
TEMP:=0;
FOR I IN 0 TO 6 LOOP
IF(MEN(I)='1')THEN
TEMP:=TEMP+1;
ELSE
TEMP:=TEMP;
END IF;
END LOOP;
CASE TEMP IS
WHEN 0 TO 3 =>OUTPUT<='0';
WHEN 4 TO 7 =>OUTPUT<='1';
END CASE ;
END PROCESS;
END BEHAVE;
4-7给出1位全减器的VHDL描述,要求:首先设计1位半减器,然后用例化语句将它们连接起来。

设X为被减数，Y为减数，DIFF是输出差(DIFF=X-Y),SUB_OUT是借位输出(SUB_OUT=1,X<Y),SUB_IN是借位输入。

(1.1)：实现1位半减器H_SUBER(DIFF=X-Y；S_OUT=1,X<Y)
LIBRARY IEEE; --半减器描述(1):布尔方程描述方法
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY H_SUBER IS
PORT( X,Y: IN STD_LOGIC;
DIFF,S_OUT: OUT STD_LOGIC);
END ENTITY H_SUBER;
ARCHITECTURE HS1 OF H_SUBER IS
BEGIN
DIFF <= X XOR (NOT Y);
S_OUT <= (NOT X) AND Y;
END ARCHITECTURE HS1;
--解(1.2)：采用例化实现图4-20的1位全减器
LIBRARY IEEE; --1位二进制全减器顺层设计描述
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY F_SUBER IS
PORT(XIN,YIN,SUB_IN: IN STD_LOGIC;
SUB_OUT,DIFF_OUT: OUT STD_LOGIC);
END ENTITY F_SUBER;
ARCHITECTURE FS1 OF F_SUBER IS
COMPONENT H_SUBER --调用半减器声明语句
PORT(X, Y: IN STD_LOGIC;
DIFF,S_OUT: OUT STD_LOGIC);
END COMPONENT;
SIGNAL A,B,C: STD_LOGIC; --定义1个信号作为内部的连接线。

BEGIN
U1:H_SUBER PORT MAP(X=>XIN,Y=>YIN, DIFF=>A, S_OUT=>B); U2:H_SUBER PORT MAP(X=>A, Y=>SUB_IN, DIFF=>DIFF_OUT,S_OUT=>C); SUB_OUT <= C OR B;
END ARCHITECTURE FS1;
二进制全加器，元件声明与元件例化（COMPONENT,PORT MAP）//或门
LIBRARY IEEE; ；
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY OR2A IS
PORT(A,B : IN STD_LOGIC;
C : OUT STD_LOGIC);
END OR2A;
ARCHITECTURE ART1 OF OR2A IS
BEGIN
C<=A OR B;
END ART1;
//半加器；
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY H_ADDER IS
PORT(A,B : IN STD_LOGIC;
CO,SO: OUT STD_LOGIC);
END H_ADDER;
ARCHITECTURE ART2 OF H_ADDER IS
BEGIN
SO <= A XOR B;
CO <= A AND B;
END ART2;
1位二进制全加器顶层设计：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164。

ALL;
ENTITY F_ADDER IS
PORT(AIN,BIN,CIN : IN STD_LOGIC;
COUT,SUM : OUT STD_LOGIC);
END F_ADDER;
ARCHITECTURE ART3 OF F_ADDER IS
COMPONENT H_ADDER //元件声明；
PORT(A,B : IN STD_LOGIC;
CO,SO: OUT STD_LOGIC);
END COMPONENT;
COMPONENT OR2A
PORT(A,B : IN STD_LOGIC;
C : OUT STD_LOGIC);
END COMPONENT;
SIGNAL D,E,F : STD_LOGIC;
BEGIN
U1:H_ADDER PORT MAP(AIN,BIN,D,E); //元件例化；U2:H_ADDER PORT MAP(A=>E,B=>CIN,CO=>F,SO=>SUM);
U3:OR2A PORT MAP(D,F,COUT);
END ART3;
10进制异步复位计数器
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY CNT_10_2 IS
PORT(
CLK,CLR : IN STD_LOGIC;
COUNT : OUT STD_LOGIC
);
END;
ARCHITECTURE A OF CNT_10_2 IS
SIGNAL CNT_10 : INTEGER RANGE 0 TO 10;
BEGIN
PROCESS(CLK,CLR)
BEGIN
IF CLR='1' THEN
CNT_10<=0;
ELSIF CLK'EVENT AND CLK='1' THEN
CNT_10<=CNT_10+1;
IF CNT_10=9 THEN
CNT_10<=0;
COUNT<='1';
ELSE
COUNT<='0';
END IF;
END IF;
END PROCESS;
END A;
10进制异步复位可调占空比
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY CNT_10_1 IS
PORT(
CLK,CLR : IN STD_LOGIC;
COUNT : OUT STD_LOGIC
);
END;
ARCHITECTURE A OF CNT_10_1 IS
BEGIN
PROCESS(CLK,CLR)
VARIABLE CNT_10 : INTEGER RANGE 0 TO 10; BEGIN
IF CLR='1' THEN
CNT_10:=0;
ELSIF CLK'EVENT AND CLK='1' THEN
CNT_10:=CNT_10+1;
IF CNT_10=10 THEN
CNT_10:=0;
COUNT<='1';
ELSE
COUNT<='0';
END IF;
END IF;
END PROCESS;
END A;
10进制同步复位计数器（用信号）
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY CNT_10_2 IS
PORT(
A : IN INTEGER RANGE 0 TO 10;
CLK,CLR,PST : IN STD_LOGIC;
COUNT : OUT STD_LOGIC
);
END;
ARCHITECTURE A OF CNT_10_2 IS
SIGNAL CNT_10: INTEGER RANGE 0 TO 9;
BEGIN
PROCESS(CLK,CLR,PST)
--VARIABLE CNT_10 : INTEGER RANGE 0 TO 9; BEGIN
IF CLR='1' THEN
CNT_10<=0;
ELSIF CLK'EVENT AND CLK='1' THEN
IF PST='1' THEN
CNT_10<=A;
ELSIF CNT_10=9 THEN
CNT_10<=0;
COUNT<='1';
ELSE
COUNT<='0';
CNT_10<=CNT_10+1;
END IF;
END IF;
END PROCESS;
END A;
N位全减器
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY F_SUB4_2 IS
GENERIC (N : INTEGER := 4);
PORT(
A,B : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0); CIN : IN STD_LOGIC;
DIFF: OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0);
COUT: OUT STD_LOGIC
);
END;
ARCHITECTURE A OF F_SUB4_2 IS
COMPONENT F_SUB1 IS
PORT(
A,B,CIN : IN STD_LOGIC;
DIFF,COUT : OUT STD_LOGIC
);
END COMPONENT;
SIGNAL C :STD_LOGIC_VECTOR(N DOWNTO 0);
BEGIN
C(0)<=CIN;
N1: FOR I IN 0 TO N-1 GENERATE
U1: F_SUB1 PORT MAP(A(I),B(I),C(I),DIFF(I),C(I+1)); END GENERATE;
COUT<=C(N);
END A;
带异步复位的能自启动的4位l环形计数器
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY HUANXINGJISHU IS
PORT(CLK,RS:IN STD_LOGIC;
COUNTOUT:OUT STD_LOGIC_VECTOR(3 DOWNTO 0) );
END HUANXINGJISHU;
ARCHITECTURE BEHAVE OF HUANXINGJISHU IS
SIGNAL Q:STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
PROCESS(RS,CLK)
BEGIN
IF RS='0' THEN Q<="0011";
ELSIF(CLK'EVENT AND CLK='1') THEN
CASE Q IS
WHEN"0000"=>Q<="0001";
WHEN"0001"=>Q<="0010";
WHEN"0010"=>Q<="0100";
WHEN"0011"=>Q<="0110";
WHEN"0100"=>Q<="1000";
WHEN"0101"=>Q<="1010";
WHEN"0110"=>Q<="1100";
WHEN"0111"=>Q<="1110";
WHEN"1000"=>Q<="0001";
WHEN"1001"=>Q<="0010";
WHEN"1010"=>Q<="0100";
WHEN"1011"=>Q<="0110";
WHEN"1100"=>Q<="1000";
WHEN"1101"=>Q<="1010";
WHEN"1110"=>Q<="1100";
WHEN"1111"=>Q<="1110";
WHEN OTHERS =>Q<="0000";
END CASE;
END IF;
END PROCESS;
COUNTOUT<=Q;
END BEHAVE;
4MHZ到1HZ的分频器
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY COUNT IS
PORT( CLK: IN STD_LOGIC;
Q: OUT STD_LOGIC);
END COUNT;
ARCHITECTURE RTL OF COUNT IS
SIGNAL TMP: STD_LOGIC_VECTOR(21 DOWNTO 0); BEGIN
PROCESS(CLK)
BEGIN
IF CLK'EVENT AND C LK='1‘ THEN
TMP<=TMP+1;
END IF;
END PROCESS;
Q<=TMP(21);
END RTL;
集成计数器74161 P1
通用双向数据缓冲器P1
十进制计数器 P2
10进制异步复位计数器 P1910进制异步复位可调占空比P20任意整数进制的计数器 P6 8421码计数器 P12
4位L环形计数器 P22
N位全减器 P21
一位全减器 P3
1位全减器 P17
一位全减器 P10
四位的全减器 P11
N位减法器 P11
十进制——BCD码编码器 P5 8—3优先编码器 P13
8-3优先编码器 P15
序列信号发生器 P7JK触发器 P7
单稳态触发器 P13
双4选一的数据选择器P8
四选一多路选择器 P16
8选一数据选择器P9
3—8译码器 P9
占空比为50%的1000分频器 P10 4MHZ到1HZ的分频器 P23
7人表决电路 P16
要求设计一个序列检测器,检测序列为1110010
程序代码
--SEQUENCE DETECTOR
--CHECK THE SEQUENCE 1110010
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CHECK_STATE1 IS
PORT(CLK,CLR:IN STD_LOGIC;
DIN:IN STD_LOGIC;
Z:OUT STD_LOGIC);
END ENTITY;
ARCHITECTURE BEHAVIOR OF CHECK_STATE1 IS
TYPE STATE_TYPE IS (S1,S2,S3,S4,S5,S6,S7,S8);
SIGNAL STATE:STATE_TYPE:=S1;
BEGIN
PROCESS(CLK,CLR,STATE,DIN)
BEGIN
IF CLR='1' THEN
Z<='0';
STATE<=S1;
ELSIF CLK'EVENT AND CLK='1' THEN CASE STATE IS
WHEN S1 => Z<='0';
IF DIN='1' THEN STATE<=S2;
END IF;
WHEN S2 => Z<='0';
IF DIN='1' THEN STATE<=S3;
ELSE
STATE<=S1;
END IF;
WHEN S3 => Z<='0';
IF DIN='1' THEN STATE<=S4;
ELSE
STATE<=S1;
END IF;
WHEN S4 => Z<='0';
IF DIN='0' THEN STATE<=S5;
ELSE
STATE<=S4;
END IF;
WHEN S5 => Z<='0';
IF DIN='0' THEN STATE<=S6;
ELSE
STATE<=S2;
END IF;
WHEN S6 => Z<='0';
IF DIN='1' THEN STATE<=S7;
ELSE
STATE<=S1;
END IF;
WHEN S7 => Z<='0';
IF DIN='0' THEN STATE<=S8;
ELSE
STATE<=S3;
END IF;
WHEN S8 => Z<='1';
IF DIN='0' THEN STATE<=S1; ELSE
STATE<=S2; END IF;
END CASE;
END IF;
END PROCESS;
END;。