EDA课后答案(适用于《EDA技术及应用》)

1.1、设计集成计数器74161，设计要求如下：4-BIT BINARY UP COUNTER WITH SYNCHRONOUS LOAD AND ASYNCHRONOUS CLEAR NOTEINPUTS： CLK LDN CLRN D C B AOUTPUTS：QD QC QB QA RCO*RCO = QD & QC & QB & QALIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CNT4 ISPORT(CLK,LDN,CLRN : IN STD_LOGIC;D,C,B,A : IN STD_LOGIC;CARRY : OUT STD_LOGIC;QD,QC,QB,QA : OUT STD_LOGIC);END;ARCHITECTURE A OF CNT4 ISSIGNAL DATA_IN: STD_LOGIC_VECTOR(3 DOWNTO 0);BEGINDATA_IN<=D&C&B&A;PROCESS(DATA_IN,CLK,LDN,CLRN)VARIABLE CNT:STD_LOGIC_VECTOR(3 DOWNTO 0);BEGINIF CLRN='0' THENCNT:=(OTHERS=>'0');ELSIF CLK'EVENT AND CLK='1' THENIF LDN='0' THENCNT:=DATA_IN;ELSECNT:=CNT+1;END IF;END IF;CASE CNT ISWHEN "1111"=> CARRY<='1';WHEN OTHERS=> CARRY<='0';END CASE;QA<=CNT(0);QB<=CNT(1);QC<=CNT(2);QD<=CNT(3);END PROCESS;END A;1.2、设计一个通用双向数据缓冲器，要求缓冲器的输入和输出端口的位数可以由参数决定。

设计要求：N BIT数据输入端口A，B。

工作使能端口EN=0时双向总线缓冲器选通，DIR=1，则A=B；反之B=A。

LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY BIDIR ISGENERIC(N:INTEGER:=8);PORT( A,B : INOUT STD_LOGIC_VECTOR(N-1 DOWNTO 0);EN,DIR : IN STD_LOGIC);END;ARCHITECTURE A OF BIDIR ISBEGINPROCESS(EN,DIR)BEGINIF EN='0' THENA<=(OTHERS=>'Z');B<=(OTHERS=>'Z');ELSEIF DIR='1' THENB<=A;ELSEA<=B;END IF;END IF;END PROCESS;END A;2.1、用VHDL语言编程实现十进制计数器，要求该计数器具有异步复位、同步预置功能。

LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY CNT_10_2 ISPORT(CLK,CLR : IN STD_LOGIC;COUNT : OUT STD_LOGIC);END;ARCHITECTURE A OF CNT_10_2 ISSIGNAL CNT_10 : INTEGER RANGE 0 TO 10;BEGINPROCESS(CLK,CLR)BEGINIF CLR='1' THENCNT_10<=0;ELSIF CLK'EVENT AND CLK='1' THENCNT_10<=CNT_10+1;IF CNT_10=9 THENCNT_10<=0;COUNT<='1';ELSECOUNT<='0';END IF;END IF;END PROCESS;END A;2.2、设计实现一位全减器。

行为描述: F_SUB4LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY F_SUB4 ISPORT(A,B,CIN : IN STD_LOGIC;DIFF,COUT : OUT STD_LOGIC);END;ARCHITECTURE A OF F_SUB4 ISBEGINDIFF<=A XOR B XOR CIN;COUT<=(NOT A AND B) OR (NOT A AND CIN) OR (B AND CIN); END A;数据流描述F_SUB1LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY F_SUB1 ISPORT(A,B :IN STD_LOGIC;CIN :IN STD_LOGIC;DIFF,COUT : OUT STD_LOGIC);END;ARCHITECTURE A OF F_SUB1 ISSIGNAL S :STD_LOGIC_VECTOR(2 DOWNTO 0); BEGINS<=CIN&A&B;PROCESS(A,B,CIN)BEGINCASE S ISWHEN "000" => DIFF<='0';COUT<='0'; WHEN "001" => DIFF<='1';COUT<='1'; WHEN "010" => DIFF<='1';COUT<='0'; WHEN "011" => DIFF<='0';COUT<='0'; WHEN "100" => DIFF<='1';COUT<='1'; WHEN "101" => DIFF<='0';COUT<='1'; WHEN "110" => DIFF<='0';COUT<='0'; WHEN "111" => DIFF<='1';COUT<='1'; WHEN OTHERS=> DIFF<='X';COUT<='X'; END CASE;END PROCESS;END A;数据流描述F_SUB2LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY F_SUB2 ISPORT(A,B,CIN : IN STD_LOGIC;DIFF,COUT : OUT STD_LOGIC);END;ARCHITECTURE A OF F_SUB2 ISSIGNAL S :STD_LOGIC_VECTOR(2 DOWNTO 0); SIGNAL C :STD_LOGIC_VECTOR(1 DOWNTO 0); BEGINS<=CIN&A&B;DIFF<=C(1);COUT<=C(0);C<="00" WHEN S="000" ELSE"11" WHEN S="001" ELSE"10" WHEN S="010" ELSE"00" WHEN S="011" ELSE"11" WHEN S="100" ELSE"01" WHEN S="101" ELSE"00" WHEN S="110" ELSE"11" ;END A;数据流描述F_SUB3LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY F_SUB3 ISPORT(A,B,CIN : IN STD_LOGIC;DIFF,COUT : OUT STD_LOGIC);END;ARCHITECTURE A OF F_SUB3 ISSIGNAL S :STD_LOGIC_VECTOR(2 DOWNTO 0);SIGNAL C :STD_LOGIC_VECTOR(1 DOWNTO 0);BEGINS<=CIN&A&B;DIFF<=C(1);COUT<=C(0);WITH S SELECTC<="00" WHEN "000","11" WHEN "001","10" WHEN "010","00" WHEN "011","11" WHEN "100","01" WHEN "101","00" WHEN "110","11" WHEN OTHERS;END A;3.1、阅读教材P181页，例[5-55]并回答下列问题：（1）、该程序的功能是什么？（2）、请写出该程序所有端口的功能描述。