使用fpga设计的电路原理图路
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P0U201A01
1 P0U20001 nc
C232 100n
14
8 VCCO
1
P0U201A02
2
CLK_BRD
RESET GND GND
C
7
GND
P0U20007
14 P0U201A014 VDD P0U201A07 7 GND
GND
VCCO
VCCO
P0C20002 P0C20001 P0C20102 P0C20101 P0C20202 P0C20201 P0C20302 P0C20301 P0C20402 P0C20401 P0C20502 P0C20501
3V3 Decoupling
P0C20602 P0C20601 P0C20702 P0C20701 P0C22802 P0C22801
VCCO
P0C21602 P0C21601 P0C21702 P0C21701 P0C21802 P0C21801 P0C21902 P0C21901
1V8 Decoupling
PORTIO PORTIO1D.SchDoc OUT[16..0] IN[16..0] PORTIO PORTIO1D.SchDoc OUTB[16..0] INB[16..0]
N0OUTB16 N0OUTB15 N0OUTB14 N0OUTB13 N0OUTB12 N0OUTB11 N0OUTB10 N0OUTB9 N0OUTB8 N0OUTB7 N0OUTB6 N0OUTB5 N0OUTB4 N0OUTB3 N0OUTB2 N0OUTB1 N0OUTB0 OUTB[16..0] N0INB16 N0INB15 N0INB14 N0INB13 N0INB12 N0INB11 N0INB10 N0INB9 N0INB8 N0INB7 N0INB6 N0INB5 N0INB4 N0INB3 N0INB2 N0INB1 N0INB0 INB[16..0]
C213 100n
C214 100n
C215 100n
GND C229 10uF
P0C23101P0C23102
U201D
U201C
U201B
U201E
U201F
C222 100n
C223 100n
C224 100n
C225 100n
C226 100n
C227 100n
GND C231 10uF
GND
P0JTAG0NEXUS0TMS
INB[16..0] OUTB[16..0] INC[16..0] OUTC[16..0]
INB[16..0] OUTB[16..0] INC[16..0] OUTC[16..0]
VCCO
P0R20002
M0 M1 M2 GND
B
P0R20001
R200 4K7 TEST_BUTTON 5V
A
P0TMS TMS P0TCK TCK P0TDI TDI P0TDO TDO
INA[16..0] OUTA[16..0]
INA[16..0] OUTA[16..0]
JTAG_NEXUS_TMS P0JTAG0NEXUS0TCK JTAG_NEXUS_TCK P0JTAG0NEXUS0TDI JTAG_NEXUS_TDI P0JTAG0NEXUS0TDO JTAG_NEXUS_TDO
P0C50102 P0C50101
VCCO VCCO
P0C50002 P0C50001 P0C50202 P0C50201
VCCO
8 P0RA50007 7 P0RA50006 6 P0RA50005 5
P0RA50008
VCCO
P0R50001
VCCO
8 P0RA50107 7 P0RA50106 6 P0RA50105 5
P0RA50108
A R500 330R
GND RA501 4k7 VCCO 20 18 19 U501
P0U501020
C500 100n
VCCO VCC
P0U500016
15 P0U500015 OE 1 P0U50001 S 2P0U50002 I0A 5P0U50005 I0B 11P0U500011 I0D 14P0U500014 I0C 3P0U50003 I1A 6P0U50006 I1B 10P0U500010 I1D 13P0U500013 I1C 8 GND
P0U50008
16
1 2 P0RA50102 3 P0RA50103 4 P0RA50104
P0RA50101
GND VCCJ VCCINT P0U501019 VCCO
P0U501018
P0U50101
D0
1
1 2 P0RA50002 3 P0RA50003 4 P0RA50004
P0RA50001
P0C22502P0C22501
P0C22602P0C22601
P0C22702P0C22701
P0U201F012
P0U201E010
P0U201D08
P0U201C06
P0U201B04
C233 100n
8
6
12
10
4
C208 100n
C209 100n
C210 100n
C211 100n
C212 100n
N0OUTA16 N0OUTA15 N0OUTA14 N0OUTA13 N0OUTA12 N0OUTA11 N0OUTA10 N0OUTA9 N0OUTA8 N0OUTA7 N0OUTA6 N0OUTA5 N0OUTA4 N0OUTA3 N0OUTA2 N0OUTA1 N0OUTA0 OUTA[16..0] N0INA16 N0INA15 N0INA14 N0INA13 N0INA12 N0INA11 N0INA10 N0INA9 N0INA8 N0INA7 N0INA6 N0INA5 N0INA4 N0INA3 N0INA2 N0INA1 N0INA0 INA[16..0]
OUT[16..0] IN[16..0]
B
TMS TCK TDI TDO
N0TMS TMS N0TCK TCK N0TDI TDI N0TDO TDO
TMS TCK TDI TDO OUTC[16..0] INC[16..0]
N0OUTC16 N0OUTC15 N0OUTC14 N0OUTC13 N0OUTC12 N0OUTC11 N0OUTC10 N0OUTC9 N0OUTC8 N0OUTC7 N0OUTC6 N0OUTC5 N0OUTC4 N0OUTC3 N0OUTC2 N0OUTC1 N0OUTC0 OUTC[16..0] N0INC16 N0INC15 N0INC14 N0INC13 N0INC12 N0INC11 N0INC10 N0INC9 N0INC8 N0INC7 N0INC6 N0INC5 N0INC4 N0INC3 N0INC2 N0INC1 N0INC0 INC[16..0]
JTAG_NEXUS_TMS JTAG_NEXUS_TCK JTAG_NEXUS_TDI JTAG_NEXUS_TDO
PORTIO PORTIO1D.SchDoc OUTD[16..0] IND[16..0]
N0OUTD16 N0OUTD15 N0OUTD14 N0OUTD13 N0OUTD12 N0OUTD11 N0OUTD10 N0OUTD9 N0OUTD8 N0OUTD7 N0OUTD6 N0OUTD5 N0OUTD4 N0OUTD3 N0OUTD2 N0OUTD1 N0OUTD0 OUTD[16..0] N0IND16 N0IND15 N0IND14 N0IND13 N0IND12 N0IND11 N0IND10 N0IND9 N0IND8 N0IND7 N0IND6 N0IND5 N0IND4 N0IND3 N0IND2 N0IND1 N0IND0 IND[16..0]
C203 100n
C204 100n
C205 100n
C206 100n
C207 100n
C228 10uF
C216 100n
C217 100n
C218 100n
C219 100n
C220 100n
C221 100n
P0C23302 P0C23301
P0C20802P0C20801
P0C20902P0C20901
P0C21002P0C21001
P0C21102P0C21101
P0C21202P0C21201
P0C21302P0C21301
P0C21402P0C21401
P0C21502P0C21501
P0C22901P0C22902
P0C22202P0C22201
P0C22302P0C22301
P0C22402P0C22401
OUT[16..0] IN[16..0]
C
N0RS2320TX RS232_TX N0RS2320RX RS232_RX
POWER POWER.SchDoc
RS232 RS232.SchDoc
RS232_TX RS232_RX
C
D
Title
D Number Revision
Size A4 Date: File: 1 2 3
PORTIO PORTIO1D.SchDoc OUT[16..0] IN[16..0]
B
RS232_TX RS232_RX
JTAG_NEXUS_TMS JTAG_NEXUS_TCK JTAG_NEXUS_TDI JTAG_NEXUS_TDO
N0JTAG0NEXUS0TMS JTAG_NEXUS_TMS N0JTAG0NEXUS0TCK JTAG_NEXUS_TCK N0JTAG0NEXUS0TDI JTAG_NEXUS_TDI N0JTAG0NEXUS0TDO JTAG_NEXUS_TDO
D
Title
D Number Revision
Size A4 Date: File: 1 2 3
2011/7/7 F:\project\
\FPGA.SchDoc
Sheet of Drawn By: 4
1
2
3
4
Include Configuration Memory in JTAG Chain
A HDR500 2 P0HDR50002 1 P0HDR50001 Header 2 U500 VCCO
P0R50002
C502 10uF Tant
RA500 3k3
N0CFG0DIN CFG_DIN
P0CFG0DIN CFG_DIN
C501 100n
P0U50004
VCCO GND
N0TDI0PP TDI_PP N0TMS TMS
ZA ZB ZC ZD
4 7
GND
P0U50007
4 P0U50104 TDI 5 P0U50105 TMS 6 P0U50106 TCK 2 P0U50102 DNC 9 P0U50109 DNC 12 P0U501012 DNC 14 P0U501014 DNC 15 P0U501015 DNC 16 P0U501016 DNC 11 P0U501011 GND GND
P0C22002 P0C22001 P0C22102 P0C22101 P0C23002 P0C23001
VCCINT C230 10uF
C
P0U201F013
P0U201E011
P0U201D09
P0U201C05
P0U201B03
13
11
9
5
3
C200 100n
C201 100n
C202 100n
P0SW20002
IND[16..0] OUTD[16..0]
IND[16..0] OUTD[16..0]
B
SW200
P0SW20001
5V
P0U200014
1 3
2 4
P0SW20003
B3FS
P0Cwk.baidu.com3202 P0C23201
P0SW20004
U200 32MHz OUT
P0U20008
U201A MC74LVX04D
1
2
3
4
A JTAG1D JTAG1D.SchDoc CCLK CFG_INIT DONE CFG_DIN PROGRAM
N0CCLK CCLK N0CFG0INIT CFG_INIT N0DONE DONE N0CFG0DIN CFG_DIN N0PROGRAM PROGRAM
A FPGA FPGA.SchDoc CCLK CFG_INIT DONE CFG_DIN PROGRAM OUTA[16..0] INA[16..0]
2011/7/7 F:\project\
\top.SchDoc
Sheet of Drawn By: 4
1
2
3
4
FPGA FPGA .SchDoc
P0CCLK CCLK P0DONE DONE P0PROGRAM PROGRAM P0CFG0DIN CFG_DIN P0CFG0INIT CFG_INIT
A
CCLK DONE PROGRAM CFG_DIN CFG_INIT TMS TCK TDI TDO JTAG_NEXUS_TMS JTAG_NEXUS_TCK JTAG_NEXUS_TDI JTAG_NEXUS_TDO
RS232_TX RS232_RX
P0RS2320TX RS232_TX P0RS2320RX RS232_RX
1 P0U20001 nc
C232 100n
14
8 VCCO
1
P0U201A02
2
CLK_BRD
RESET GND GND
C
7
GND
P0U20007
14 P0U201A014 VDD P0U201A07 7 GND
GND
VCCO
VCCO
P0C20002 P0C20001 P0C20102 P0C20101 P0C20202 P0C20201 P0C20302 P0C20301 P0C20402 P0C20401 P0C20502 P0C20501
3V3 Decoupling
P0C20602 P0C20601 P0C20702 P0C20701 P0C22802 P0C22801
VCCO
P0C21602 P0C21601 P0C21702 P0C21701 P0C21802 P0C21801 P0C21902 P0C21901
1V8 Decoupling
PORTIO PORTIO1D.SchDoc OUT[16..0] IN[16..0] PORTIO PORTIO1D.SchDoc OUTB[16..0] INB[16..0]
N0OUTB16 N0OUTB15 N0OUTB14 N0OUTB13 N0OUTB12 N0OUTB11 N0OUTB10 N0OUTB9 N0OUTB8 N0OUTB7 N0OUTB6 N0OUTB5 N0OUTB4 N0OUTB3 N0OUTB2 N0OUTB1 N0OUTB0 OUTB[16..0] N0INB16 N0INB15 N0INB14 N0INB13 N0INB12 N0INB11 N0INB10 N0INB9 N0INB8 N0INB7 N0INB6 N0INB5 N0INB4 N0INB3 N0INB2 N0INB1 N0INB0 INB[16..0]
C213 100n
C214 100n
C215 100n
GND C229 10uF
P0C23101P0C23102
U201D
U201C
U201B
U201E
U201F
C222 100n
C223 100n
C224 100n
C225 100n
C226 100n
C227 100n
GND C231 10uF
GND
P0JTAG0NEXUS0TMS
INB[16..0] OUTB[16..0] INC[16..0] OUTC[16..0]
INB[16..0] OUTB[16..0] INC[16..0] OUTC[16..0]
VCCO
P0R20002
M0 M1 M2 GND
B
P0R20001
R200 4K7 TEST_BUTTON 5V
A
P0TMS TMS P0TCK TCK P0TDI TDI P0TDO TDO
INA[16..0] OUTA[16..0]
INA[16..0] OUTA[16..0]
JTAG_NEXUS_TMS P0JTAG0NEXUS0TCK JTAG_NEXUS_TCK P0JTAG0NEXUS0TDI JTAG_NEXUS_TDI P0JTAG0NEXUS0TDO JTAG_NEXUS_TDO
P0C50102 P0C50101
VCCO VCCO
P0C50002 P0C50001 P0C50202 P0C50201
VCCO
8 P0RA50007 7 P0RA50006 6 P0RA50005 5
P0RA50008
VCCO
P0R50001
VCCO
8 P0RA50107 7 P0RA50106 6 P0RA50105 5
P0RA50108
A R500 330R
GND RA501 4k7 VCCO 20 18 19 U501
P0U501020
C500 100n
VCCO VCC
P0U500016
15 P0U500015 OE 1 P0U50001 S 2P0U50002 I0A 5P0U50005 I0B 11P0U500011 I0D 14P0U500014 I0C 3P0U50003 I1A 6P0U50006 I1B 10P0U500010 I1D 13P0U500013 I1C 8 GND
P0U50008
16
1 2 P0RA50102 3 P0RA50103 4 P0RA50104
P0RA50101
GND VCCJ VCCINT P0U501019 VCCO
P0U501018
P0U50101
D0
1
1 2 P0RA50002 3 P0RA50003 4 P0RA50004
P0RA50001
P0C22502P0C22501
P0C22602P0C22601
P0C22702P0C22701
P0U201F012
P0U201E010
P0U201D08
P0U201C06
P0U201B04
C233 100n
8
6
12
10
4
C208 100n
C209 100n
C210 100n
C211 100n
C212 100n
N0OUTA16 N0OUTA15 N0OUTA14 N0OUTA13 N0OUTA12 N0OUTA11 N0OUTA10 N0OUTA9 N0OUTA8 N0OUTA7 N0OUTA6 N0OUTA5 N0OUTA4 N0OUTA3 N0OUTA2 N0OUTA1 N0OUTA0 OUTA[16..0] N0INA16 N0INA15 N0INA14 N0INA13 N0INA12 N0INA11 N0INA10 N0INA9 N0INA8 N0INA7 N0INA6 N0INA5 N0INA4 N0INA3 N0INA2 N0INA1 N0INA0 INA[16..0]
OUT[16..0] IN[16..0]
B
TMS TCK TDI TDO
N0TMS TMS N0TCK TCK N0TDI TDI N0TDO TDO
TMS TCK TDI TDO OUTC[16..0] INC[16..0]
N0OUTC16 N0OUTC15 N0OUTC14 N0OUTC13 N0OUTC12 N0OUTC11 N0OUTC10 N0OUTC9 N0OUTC8 N0OUTC7 N0OUTC6 N0OUTC5 N0OUTC4 N0OUTC3 N0OUTC2 N0OUTC1 N0OUTC0 OUTC[16..0] N0INC16 N0INC15 N0INC14 N0INC13 N0INC12 N0INC11 N0INC10 N0INC9 N0INC8 N0INC7 N0INC6 N0INC5 N0INC4 N0INC3 N0INC2 N0INC1 N0INC0 INC[16..0]
JTAG_NEXUS_TMS JTAG_NEXUS_TCK JTAG_NEXUS_TDI JTAG_NEXUS_TDO
PORTIO PORTIO1D.SchDoc OUTD[16..0] IND[16..0]
N0OUTD16 N0OUTD15 N0OUTD14 N0OUTD13 N0OUTD12 N0OUTD11 N0OUTD10 N0OUTD9 N0OUTD8 N0OUTD7 N0OUTD6 N0OUTD5 N0OUTD4 N0OUTD3 N0OUTD2 N0OUTD1 N0OUTD0 OUTD[16..0] N0IND16 N0IND15 N0IND14 N0IND13 N0IND12 N0IND11 N0IND10 N0IND9 N0IND8 N0IND7 N0IND6 N0IND5 N0IND4 N0IND3 N0IND2 N0IND1 N0IND0 IND[16..0]
C203 100n
C204 100n
C205 100n
C206 100n
C207 100n
C228 10uF
C216 100n
C217 100n
C218 100n
C219 100n
C220 100n
C221 100n
P0C23302 P0C23301
P0C20802P0C20801
P0C20902P0C20901
P0C21002P0C21001
P0C21102P0C21101
P0C21202P0C21201
P0C21302P0C21301
P0C21402P0C21401
P0C21502P0C21501
P0C22901P0C22902
P0C22202P0C22201
P0C22302P0C22301
P0C22402P0C22401
OUT[16..0] IN[16..0]
C
N0RS2320TX RS232_TX N0RS2320RX RS232_RX
POWER POWER.SchDoc
RS232 RS232.SchDoc
RS232_TX RS232_RX
C
D
Title
D Number Revision
Size A4 Date: File: 1 2 3
PORTIO PORTIO1D.SchDoc OUT[16..0] IN[16..0]
B
RS232_TX RS232_RX
JTAG_NEXUS_TMS JTAG_NEXUS_TCK JTAG_NEXUS_TDI JTAG_NEXUS_TDO
N0JTAG0NEXUS0TMS JTAG_NEXUS_TMS N0JTAG0NEXUS0TCK JTAG_NEXUS_TCK N0JTAG0NEXUS0TDI JTAG_NEXUS_TDI N0JTAG0NEXUS0TDO JTAG_NEXUS_TDO
D
Title
D Number Revision
Size A4 Date: File: 1 2 3
2011/7/7 F:\project\
\FPGA.SchDoc
Sheet of Drawn By: 4
1
2
3
4
Include Configuration Memory in JTAG Chain
A HDR500 2 P0HDR50002 1 P0HDR50001 Header 2 U500 VCCO
P0R50002
C502 10uF Tant
RA500 3k3
N0CFG0DIN CFG_DIN
P0CFG0DIN CFG_DIN
C501 100n
P0U50004
VCCO GND
N0TDI0PP TDI_PP N0TMS TMS
ZA ZB ZC ZD
4 7
GND
P0U50007
4 P0U50104 TDI 5 P0U50105 TMS 6 P0U50106 TCK 2 P0U50102 DNC 9 P0U50109 DNC 12 P0U501012 DNC 14 P0U501014 DNC 15 P0U501015 DNC 16 P0U501016 DNC 11 P0U501011 GND GND
P0C22002 P0C22001 P0C22102 P0C22101 P0C23002 P0C23001
VCCINT C230 10uF
C
P0U201F013
P0U201E011
P0U201D09
P0U201C05
P0U201B03
13
11
9
5
3
C200 100n
C201 100n
C202 100n
P0SW20002
IND[16..0] OUTD[16..0]
IND[16..0] OUTD[16..0]
B
SW200
P0SW20001
5V
P0U200014
1 3
2 4
P0SW20003
B3FS
P0Cwk.baidu.com3202 P0C23201
P0SW20004
U200 32MHz OUT
P0U20008
U201A MC74LVX04D
1
2
3
4
A JTAG1D JTAG1D.SchDoc CCLK CFG_INIT DONE CFG_DIN PROGRAM
N0CCLK CCLK N0CFG0INIT CFG_INIT N0DONE DONE N0CFG0DIN CFG_DIN N0PROGRAM PROGRAM
A FPGA FPGA.SchDoc CCLK CFG_INIT DONE CFG_DIN PROGRAM OUTA[16..0] INA[16..0]
2011/7/7 F:\project\
\top.SchDoc
Sheet of Drawn By: 4
1
2
3
4
FPGA FPGA .SchDoc
P0CCLK CCLK P0DONE DONE P0PROGRAM PROGRAM P0CFG0DIN CFG_DIN P0CFG0INIT CFG_INIT
A
CCLK DONE PROGRAM CFG_DIN CFG_INIT TMS TCK TDI TDO JTAG_NEXUS_TMS JTAG_NEXUS_TCK JTAG_NEXUS_TDI JTAG_NEXUS_TDO
RS232_TX RS232_RX
P0RS2320TX RS232_TX P0RS2320RX RS232_RX