数字秒表设计
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2012-2013 学年 1 学期
山东科技大学电工电子实验教学中心
创新性实验研究报告
实验项目名称＿秒表设计＿＿＿
组长姓名学号
联系电话E-mail
成员姓名学号
成员姓名学号
专业电气工程及其自动化班级
指导教师及职称
2013年1 月14 日
四、实验内容
五、实验结果与分析
六、实验结论
七、指导老师评语及得分：
附件：
图1、实验电路结构框图
1、秒表计时模块程序段：
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY count60 IS
port( EN,RESET,CLK1,CLK2,PRESET: IN STD_LOGIC;
QA,QB,QC,QD: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); VOICE: OUT STD_LOGIC);
end entity;
ARCHITECTURE one OF count60 IS
signal pre1: INTEGER RANGE 0 TO 9;
signal pre2: INTEGER RANGE 0 TO 9;
signal pre3: INTEGER RANGE 0 TO 9;
signal pre4: INTEGER RANGE 0 TO 9;
signal CNT4: INTEGER RANGE 0 TO 3 := 0;
signal sco,mco,put1,put2:STD_LOGIC;
signal oma,omb,omc,omd,shishu:STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
pre1<=3;pre2<=0;pre3<=1;pre4<=0;
P1:process(clk1)
variable tma: STD_LOGIC_VECTOR(3 DOWNTO 0);
variable tmb: STD_LOGIC_VECTOR(3 DOWNTO 0);
begin
put1<='1';
If Reset ='0' or put1='0' then tma:="0000"; tmb:="0000";
elsif Put2='0'and tma=(pre1+1) and tmb=pre2 then tma:=tma; tmb:=tmb;put1<='0';
elsif clk1'event and clk1='1' then
if en='1' then
sco<=tmb(2)and tmb(0)and tma(3)and tma(0);
if tma="1001" then tma:="0000";
if tmb="0101" then tmb:="0000";
else tmb:=tmb+1;
end if;
else tma:=tma+1;
end if;
end if;
end if;
oma<=tma;omb<=tmb;qa<=tma;qb<=tmb;
end process P1;
P2:process(sco)
variable tmc: STD_LOGIC_VECTOR(3 DOWNTO 0);
variable tmd: STD_LOGIC_VECTOR(3 DOWNTO 0);
begin
pre3<=1; pre4<=0;
put2<='1';
if Reset ='0' or put1='0' then tmc:="0000"; tmd:="0000";
elsif Preset='0'and tmc=pre3 and tmd=pre4 then tmc:=tmc; tmd:=tmd;put2<='0';
elsif sco'event and sco='1' then
if en='1' then
mco<=tmd(2)and tmd(0)and tmc(3)and tmc(0);
if tmc="1001" then tmc:="0000";
if tmd="0101" then tmd:="0000";
else tmd:=tmd+1;
end if;
else tmc:=tmc+1;
end if;
end if;
end if;
omc<=tmc;omd<=tmd;qc<=tmc;qd<=tmd;
end process P2;
P3:process(clk2)
begin
if (preset='1' and oma=9 and omb=5 and omc=9 and omd=5) or(preset='0'and oma=pre1 and omb=pre2 and omc=pre3 and omd=pre4) then V oice<=clk2;
else V oice<='0';
end if;
end process P3;
生成元件符号：
图2、秒表计时模块元件符号
2、LED数码管显示模块程序段如下所示：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY SCAN_LED IS
PORT( CLK: IN STD_LOGIC;
S1, S2, S3, S4: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
BT: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
SG: OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END ENTITY;
ARCHITECTURE behave OF SCAN_LED IS
SIGNAL CNT4 : INTEGER RANGE 0 TO 3 := 0;
SIGNAL SHISHU: STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
P1:PROCESS(CLK)
BEGIN
IF CLK'EVENT AND CLK = '1' THEN
CNT4 <= CNT4 + 1;
CASE CNT4 IS
WHEN 0 => BT <= "1000"; SHISHU <= S1;
WHEN 1 => BT <= "0100"; SHISHU <= S2;
WHEN 2 => BT <= "0010"; SHISHU <= S3;
WHEN 3 => BT <= "0001"; SHISHU <= S4;CNT4<=0;
WHEN OTHERS => NULL;
END CASE;
END IF;
END PROCESS;
P2: PROCESS(SHISHU)
BEGIN
IF CNT4=3 THEN
CASE SHISHU IS
WHEN "0000" => SG<= "11111110" ;
WHEN "0001" => SG<= "10110000" ;
WHEN "0010" => SG<= "11101101" ;
WHEN "0011" => SG<= "11111001" ;
WHEN "0100" => SG<= "10110011" ;
WHEN "0101" => SG<= "11011011" ;
WHEN "0110" => SG<= "11011111" ;
WHEN "0111" => SG<= "11110000" ;
WHEN "1000" => SG<= "11111111" ;
WHEN "1001" => SG<= "11111011" ;
WHEN others=> NULL;
END CASE;
ELSE