数字集成电路复习习题库
数字电路复习题
数字电路复习题（选择、填空、判断）第一章数制与码制选择题1.与十进制数（53）10等值的数为（A ）A.(100111)2B.(110101)2C.(25 )16D.(33)162.十进制数25用8421BCD码表示为（B ）A.10101B.00100101C.11001D.101010003.在下列一组数中，最大数是（C ）A.(258)10B.(100000010)2C.(103)16D.(001001011000)8421BCD4.十----二进制转换：（25.7）10＝（C ）2A.11011.1011B.11001.1001C.11001.1011D.11011.10015.将十进制数35表示为8421BCD码是（C ）A.100011B.100011C.110101D.11010006.将二进制数11001.01转换为十进制数是（B ）A.20.25B.25.25C.25.2D.25.17.十——二进制转换：（117）10＝（A ）2A.1110101B.1110110C.1100101D.110101判断题1.数字信号是离散信号，模拟信号是连续信号。
（√）2.格雷码具有任何相邻码只有一位码元不同的特性。
（√）3.8421码又称BCD码，是十进制代码中最常用的一种。
8421码属于恒权码。
（√）4.直接对模拟量进行处理的电子线路称为数字电路。
（X ）填空题1.自然界物理量按其变化规律的特点可分为两类，为模拟量和数字量。
2. 数字信号的特点是在时间上和数量上都是离散变化的。
3.(167)10=（10100111）2 =（000101100111）8421BCD。
4.(193)10=（C1 ）16 =（000110010011 ）8421BCD。
5.二进制数01011001对应的十六进制数（59 ）16 ，表示十进制数是89 。
6.BCD余3码100001011001对应的十进制数526 ，表示成BCD8421码是010********* 。
数字集成电路测试题
A 衬底 B 扩散区 C 有源区 D 接触孔和通孔
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Inverter
单选题 1分 最符合阈值电压定义的说法是 。
A 漏端电流为1μA时的栅源电压
B 漏端电流10倍于泄露电流时的栅源电压
衬底载流子浓度和有源区载流子浓度相 C 等时的栅源电压
芯片中的金属线和PCB中的金属线一样， A 可以是多层的。
B
CMOS集成电路是在一块正方形的硅片 上制造的。
光刻机的作用是通过激光在硅片上刻画 C 集成电路版图。
光刻胶的作用是将集成电路所需的不同 D 材料层胶合在一起。
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Inverter
D MOgrated Circuits2nd
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Inverter
单选题 1分 电路互连线上的延时td 与长度L的关系是 。
A
td L
B
td L2
C
td L3/2
D
td L3
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数字集成电路 ch1-ch4习题集
Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic
© Digital Integrated Circuits2nd
Inverter
单选题 1分
在集成电路0.25μm工艺中，晶体管的最小沟 道长度由 决定。
A 光刻精度 B 消费者和代工厂 C 电路工程师 D 电源电压
C 无穷大的“断开”电阻和有限的“导通”电阻。
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数字集成电路习题
带入延迟公式可得，反相器链的延迟
t p N t p 0 (1
N
F
) 5 70 ps (1
5
2000 ) 1960 ps 2ns 1
c． 方法 a 的延迟时间
t p t p 0 (1
j 1
N
C g , j 1
C g , j
) t p 0 (1
解：VGS=VDS=2.5V，管子工作在饱和区。 栅沟电容 CGC=W*L*Cox=0.36um*0.24um*6fF/um2=0.52fF 栅与源漏区的交叠电容 Cov=CGSO=CGDO=W*Co=0.36um*0.31fF/um=0.11fF 栅电容 CG=CGC+2Cov=0.52 fF +2*0.11 fF=0.74fF 栅源电容 CGS=2CGC/3+Cov=2*0.52fF/3+0.11=0.46fF 栅漏电容 CGD=Cov=0.11fF 管子的源区和衬底都接地，所以源衬底扩散结处于零偏状态。有 Cs,bottom=W*LD*Cj0=0.36um*0.625um*2fF/um2=0.45fF Cs,sw=(W+2LD)*Cjsw0=(0.36um+2*0.625um)*0.28um/fF=0.45fF CSB= Cs,bottom + Cs,sw =0.45fF+0.45fF=0.9fF 管子的漏区接 2.5V，衬底接地，所以漏衬底扩散结处于反偏状态。有 CD,bottom=W*LD*Cj0/(1-VD/φ b)mj =0.36um*0.625um*2(fF/um2)/[1-(-2.5V)/0.9V]0.5 =0.23fF CD,sw=(W+2LD)*Cjsw0/(1-VD/φ bsw)mjsw =(0.36um+2*0.625um)*0.28(um/fF)/[1-(-2.5V)/0.9]0.44 =0.25fF CDB= CD,bottom + CD,sw =0.23fF+0.25fF=0.48fF
数字集成电路习题(第三章)
0. Explain qualitatively
4
Chapter 3 Problem Set a. Write down the equations (and only those) which are needed to determine the voltage at node X. Do NOT plug in any values yet. Neglect short channel effects and assume that λp = 0. b. Draw the (approximative) load lines for both MOS transistor and resistor. Mark some of the significant points. c. Determine the required width of the transistor (for L = 0.25µm) such that X equals 1.5 V. d. We have, so far, assumed that M1 is a long-channel device. Redraw the load lines assuming that M1 is velocity-saturated. Will the voltage at X rise or fall?
Table 0.2 Measurements taken from the MOS device, at different terminal voltages.
Measurement number 1 2 3 4 5 6 7 8.
VGS (V) -2.5 1 -0.7 -2.0 -2.5 -2.5 -2.5
R1 = 2kΩ + 2.5 V – ID R2 = 2kΩ
数字集成电路--电路、系统与设计（第二版）课后练习题第六.
数字集成电路--电路、系统与设计（第⼆版）课后练习题第六.Digital Integrated Circuits - 2nd Ed 11 DESIGN PROJECT Design, lay out, and simulate a CMOS four-input XOR gate in the standard 0.25 micron CMOS process. You can choose any logic circuit style, and you are free to choose how many stages of logic to use: you could use one large logic gate or a combination of smaller logic gates. The supply voltage is set at 2.5 V! Your circuit must drive an external 20 fF load in addition to whatever internal parasitics are present in your circuit. The primary design objective is to minimize the propagation delay of the worst-case transition for your circuit. The secondary objective is to minimize the area of the layout. At the very worst, your design must have a propagation delay of no more than 0.5 ns and occupy an area of no more than 500 square microns, but the faster and smaller your circuit, the better. Be aware that, when using dynamic logic, the precharge time should be made part of the delay. The design will be graded on themagnitude of A × tp2, the product of the area of your design and the square of the delay for the worst-case transition.。
数字集成电路--电路、系统与设计(第二版)课后练习题 第六章 CMOS组合逻辑门的设计
Chapter 6 Problem Set
Chapter 6 PROBLEMS
1. [E, None, 4.2] Implement the equation X = ((A + B) (C + D + E) + F) G using complementary CMOS. Size the devices so that the output resistance is the same as that of an inverter with an NMOS W/L = 2 and PMOS W/L = 6. Which input pattern(s) would give the worst and best equivalent pull-up or pull-down resistance? Implement the following expression in a full static CMOS logic fashion using no more than 10 transistors: Y = (A ⋅ B) + (A ⋅ C ⋅ E) + (D ⋅ E) + (D ⋅ C ⋅ B) 3. Consider the circuit of Figure 6.1.
2
VDD E 6 A A 6 B 6 C 6 D 6 E F A B C D 4 4 4 4 E 1 A B C D 4 4 4 4 E 1 6 F 6 B 6 C 6 D
Chapter 6 Problem Set
VDD 6
Circuit A
Circuit B
Figure 6.2 Two static CMOS gates.
【精品】数字集成电路电路、系统与设计第二版课后练习题第六章CMOS组合逻辑门的设计
【精品】数字集成电路--电路、系统与设计(第二版)课后练习题第六章CMOS组合逻辑门的设计第六章 CMOS组合逻辑门的设计1.为什么CMOS电路逻辑门的输入端和输出端都要连接到电源电压？CMOS电路采用了MOSFET（金属氧化物半导体场效应管）作为开关元件，其中N沟道MOSFET（NMOS）和P沟道MOSFET（PMOS）分别用于实现逻辑门的输入和输出。
NMOS和PMOS都需要连接到电源电压，以使其能够正常工作。
输入端连接到电源电压可以确保信号在逻辑门中正常传递，输出端连接到电源电压可以确保输出信号的正确性和稳定性。
2.为什么在CMOS逻辑门中要使用两个互补的MOSFET？CMOS逻辑门中使用两个互补的MOSFET是为了实现高度抗干扰的逻辑功能。
其中，NMOS和PMOS分别用于实现逻辑门的输入和输出。
NMOS和PMOS的工作原理互补，即当NMOS导通时，PMOS截止，当PMOS导通时，NMOS截止。
这样的设计可以在逻辑门的输出上提供高电平和低电平的稳定性，从而提高逻辑门的抗干扰能力。
3.CMOS逻辑门的输入电压范围是多少？CMOS逻辑门的输入电压范围通常是在0V至电源电压之间，即在低电平和高电平之间。
在CMOS逻辑门中，低电平通常定义为输入电压小于0.3Vdd（电源电压的30%），而高电平通常定义为输入电压大于0.7Vdd（电源电压的70%）。
4.如何设计一个基本的CMOS逻辑门？一个基本的CMOS逻辑门可以由一个NMOS和一个PMOS组成。
其中，NMOS的源极连接到地，栅极连接到逻辑门的输入，漏极连接到PMOS的漏极；PMOS的源极连接到电源电压，栅极连接到逻辑门的输入，漏极连接到输出。
这样的设计可以实现逻辑门的基本功能。
5.如何提高CMOS逻辑门的速度？可以采取以下方法来提高CMOS逻辑门的速度：•减小晶体管的尺寸：缩小晶体管的尺寸可以减小晶体管的电容和电阻，从而提高逻辑门的响应速度。
•优化电源电压：增加电源电压可以提高晶体管的驱动能力，从而加快逻辑门的开关速度。
复习题(数电答案)
1．下列四种类型的逻辑门中，可以用（ D ）实现与、或、非三种基本运算。
A. 与门 B. 或门 C. 非门 D. 与非门 2. 根据反演规则，CD C B A F ++=)(的反函数为（A ）。
A. ))((''''''D C C B A F ++= B. ))((''''''D C C B A F ++= C. ))((''''''D C C B A F += D. ))(('''''D C C B A F ++= 3.逻辑函数F=)(B A A ⊕⊕ =（ A ）。
A. BB. AC. B A ⊕D. B A ⊕4. 最小项ABCD 的逻辑相邻最小项是（ A ）。
A. ABCDB. ABCDC. ABCDD. ABCD 5. 对CMOS 与非门电路，其多余输入端正确的处理方法是（D ）。
A. 通过大电阻接地（>1.5K Ω）B. 悬空C. 通过小电阻接地（<1K Ω）D. 通过电阻接+VCC 6. 下列说法不正确的是（ C ）。
A ．当高电平表示逻辑0、低电平表示逻辑1时称为正逻辑。
B ．三态门输出端有可能出现三种状态（高阻态、高电平、低电平）。
C ．OC 门输出端直接连接可以实现正逻辑的线与运算。
D ．集电极开路的门称为OC 门。
7．已知74LS138译码器的输入三个使能端（E 1=1， E 2A = E 2B =0）时，地址码A 2A 1A 0=011，则输出 Y 7 ～Y 0是( C ) 。
A. 11111101B. 10111111C. 11110111D. 111111118. 若用JK 触发器来实现特性方程为1+n QQ AB Q +=A ，则JK 端的方程为（ A ）。
A.J=AB ，K=AB.J=AB ，K=AC. J =A ，K =ABD.J=B A ，K=AB 9．要将方波脉冲的周期扩展10倍，可采用（ C ）。
数字集成电路--电路、系统与设计(第二版)课后练习题 第五章 CMOS反相器
C H A P T E R5T H E C M O S I N V E R T E R Quantification of integrity,performance,and energy metrics of an inverterOptimization of an inverter design5.1Exercises and Design Problems5.2The Static CMOS Inverter—An IntuitivePerspective5.3Evaluating the Robustness of the CMOSInverter:The Static Behavior5.3.1Switching Threshold5.3.2Noise Margins5.3.3Robustness Revisited5.4Performance of CMOS Inverter:The DynamicBehavior5.4.1Computing the Capacitances5.4.2Propagation Delay:First-OrderAnalysis5.4.3Propagation Delay from a DesignPerspective5.5Power,Energy,and Energy-Delay5.5.1Dynamic Power Consumption5.5.2Static Consumption5.5.3Putting It All Together5.5.4Analyzing Power Consumption UsingSPICE5.6Perspective:Technology Scaling and itsImpact on the Inverter Metrics180Section 5.1Exercises and Design Problems 1815.1Exercises and Design Problems1.[M,SPICE,3.3.2]The layout of a static CMOS inverter is given in Figure 5.1.(λ=0.125µm).a.Determine the sizes of the NMOS and PMOS transistors.b.Plot the VTC (using HSPICE)and derive its parameters (V OH ,V OL ,V M ,V IH ,and V IL ).c.Is the VTC affected when the output of the gates is connected to the inputs of 4similargates?.d.Resize the inverter to achieve a switching threshold of approximately 0.75V .Do not lay-out the new inverter,use HSPICE for your simulations.How are the noise margins affected by this modification?2.Figure 5.2shows a piecewise linear approximation for the VTC.The transition region isapproximated by a straight line with a slope equal to the inverter gain at V M .The intersectionof this line with the V OH and the V OL lines defines V IH and V IL .a.The noise margins of a CMOS inverter are highly dependent on the sizing ratio,r =k p /k n ,of the NMOS and PMOS e HSPICE with V Tn =|V Tp |to determine the valueof r that results in equal noise margins?Give a qualitative explanation.b.Section 5.3.2of the text uses this piecewise linear approximation to derive simplifiedexpressions for NM H and NM L in terms of the inverter gain.The derivation of the gain isbased on the assumption that both the NMOS and the PMOS devices are velocity saturatedat V M .For what range of r is this assumption valid?What is the resulting range of V M ?c.Derive expressions for the inverter gain at V M for the cases when the sizing ratio is justabove and just below the limits of the range where both devices are velocity saturated.What are the operating regions of the NMOS and the PMOS for each case?Consider theeffect of channel-length modulation by using the following expression for the small-signalresistance in the saturation region:r o,sat =1/(λI D ).Figure 5.1CMOS inverter layout.InOutGND V DD =2.5V.Poly Metal1NMOSPMOSPolyMetal12λ182THE CMOS INVERTER Chapter 53.[M,SPICE,3.3.2]Figure 5.3shows an NMOS inverter with resistive load.a.Qualitatively discuss why this circuit behaves as an inverter.b.Find V OH and V OL calculate V IH and V IL .c.Find NM L and NM H ,and plot the VTC using HSPICE.d.Compute the average power dissipation for:(i)V in =0V and (ii)V in =2.5Ve HSPICE to sketch the VTCs for R L =37k,75k,and 150k on a single graph.ment on the relationship between the critical VTC voltages (i.e.,V OL ,V OH ,V IL ,V IH )and the load resistance,R L .g.Do high or low impedance loads seem to produce more ideal inverter characteristics?4.[E,None,3.3.3]For the inverter of Figure 5.3and an output load of 3pF:a.Calculate t plh ,t phl ,and t p .b.Are the rising and falling delays equal?Why or why not?pute the static and dynamic power dissipation assuming the gate is clocked as fast as possible.5.The next figure shows two implementations of MOS inverters.The first inverter uses onlyNMOS transistors.V OH V OL inV outFigure 5.2A different approach to derive V IL and V IH .V outV in M 1W/L =1.5/0.5+2.5VFigure 5.3Resistive-load inverterR L =75k ΩSection 5.1Exercises and Design Problems183a.Calculate V OH ,V OL ,V M for each case.e HSPICE to obtain the two VTCs.You must assume certain values for the source/drain areas and perimeters since there is no layout.For our scalable CMOS process,λ =0.125μm,and the source/drain extensions are 5λfor the PMOS;for the NMOS the source/drain contact regions are 5λx5λ.c.Find V IH ,V IL ,NM L and NM H for each inverter and comment on the results.How can you increase the noise margins and reduce the undefined region?ment on the differences in the VTCs,robustness and regeneration of each inverter.6.Consider the following NMOS inverter.Assume that the bulk terminals of all NMOS deviceare connected to GND.Assume that the input IN has a 0V to 2.5V swing.a.Set up the equation(s)to compute the voltage on node x .Assume γ=0.5.b.What are the modes of operation of device M2?Assume γ=0.c.What is the value on the output node OUT for the case when IN =0V?Assume γ=0.d.Assuming γ=0,derive an expression for the switching threshold (V M )of the inverter.Recall that the switching threshold is the point where V IN =V OUT .Assume that the devicesizes for M1,M2and M3are (W/L)1,(W/L)2,and (W/L)3respectively.What are the limitson the switching threshold?For this,consider two cases:i)(W/L)1>>(W/L)2V DD =2.5V V IN V OUTV DD =2.5V V IN V OUT M 2M 1M 4M 3W/L=0.375/0.25W/L=0.75/0.25W/L=0.375/0.25W/L=0.75/0.25Figure 5.4Inverter ImplementationsV DD =2.5V OUTM1IN M2M3V DD =2.5Vx184THE CMOS INVERTER Chapter 5ii)(W/L)2>>(W/L)17.Consider the circuit in Figure 5.5.Device M1is a standard NMOS device.Device M2has allthe same properties as M1,except that its device threshold voltage is negative and has a valueof -0.4V.Assume that all the current equations and inequality equations (to determine themode of operation)for the depletion device M2are the same as a regular NMOS.Assume thatthe input IN has a 0V to 2.5V swing.a.Device M2has its gate terminal connected to its source terminal.If V IN =0V ,what is the output voltage?In steady state,what is the mode of operation of device M2for this input?pute the output voltage for V IN =2.5V .You may assume that V OUT is small to simplify your calculation.In steady state,what is the mode of operation of device M2for this input?c.Assuming Pr (IN =0)=0.3,what is the static power dissipation of this circuit?8.[M,None,3.3.3]An NMOS transistor is used to charge a large capacitor,as shown in Figure5.6.a.Determine the t pLH of this circuit,assuming an ideal step from 0to 2.5V at the input node.b.Assume that a resistor R S of 5k Ωis used to discharge the capacitance to ground.Deter-mine t pHL .c.Determine how much energy is taken from the supply during the charging of the capacitor.How much of this is dissipated in M1.How much is dissipated in the pull-down resistanceduring discharge?How does this change when R S is reduced to 1k Ω.d.The NMOS transistor is replaced by a PMOS device,sized so that k p is equal to the k n ofthe original NMOS.Will the resulting structure be faster?Explain why or why not.9.The circuit in Figure 5.7is known as the source follower configuration.It achieves a DC levelshift between the input and the output.The value of this shift is determined by the current I 0.Assume x d =0,γ=0.4,2|φf |=0.6V ,V T 0=0.43V ,k n ’=115μA/V 2and λ=0.V DD =2.5VOUTM1(4μm/1μm)IN M2(2μm/1μm),V Tn =-0.4VFigure 5.5A depletion load NMOSinverterV DD =2.5VOutFigure 5.6Circuit diagram with annotated W/L ratios=5pFSection 5.1Exercises and Design Problems 185a.Suppose we want the nominal level shift between V i and V o to be 0.6V in the circuit in Figure 5.7(a).Neglecting the backgate effect,calculate the width of M2to provide this level shift (Hint:first relate V i to V o in terms of I o ).b.Now assume that an ideal current source replaces M2(Figure 5.7(b)).The NMOS transis-tor M1experiences a shift in V T due to the backgate effect.Find V T as a function of V o for V o ranging from 0to 2.5V with 0.5V intervals.Plot V T vs.V oc.Plot V o vs.V i as V o varies from 0to 2.5V with 0.5V intervals.Plot two curves:one neglecting the body effect and one accounting for it.How does the body effect influence the operation of the level converter?d.At V o (with body effect)=2.5V,find V o (ideal)and thus determine the maximum error introduced by the body effect.10.For this problem assume:V DD =2.5V ,W P /L =1.25/0.25,W N /L =0.375/0.25,L =L eff =0.25μm (i.e.x d =0μm),C L =C inv-gate ,k n ’=115μA/V 2,k p ’=-30μA/V 2,V tn0=|V tp0|=0.4V,λ =0V -1, γ=0.4,2|φf |=0.6V ,and t ox =e the HSPICE model parameters for parasitic capacitance given below (i.e.C gd0,C j ,C jsw ),and assume that V SB =0V for all problems except part (e).Figure 5.7NMOS source follower configuration V DD =2.5V V iV oV DD =2.5VV i V oV bias =(a)(b)I o1um/0.25um M1186THE CMOS INVERTER Chapter 5##Parasitic Capacitance Parameters (F/m)##NMOS:CGDO=3.11x10-10,CGSO=3.11x10-10,CJ=2.02x10-3,CJSW=2.75x10-10PMOS:CGDO=2.68x10-10,CGSO=2.68x10-10,CJ=1.93x10-3,CJSW=2.23x10-10a.What is the V m for this inverter?b.What is the effective load capacitance C Leff of this inverter?(include parasitic capacitance,refer to the text for K eq and m .)Hint:You must assume certain values for the source/drain areas and perimeters since there is no layout.For our scalable CMOS process,λ =0.125μm,and the source/drain extensions are 5λfor the PMOS;for the NMOS the source/drain contact regions are 5λx5λ.c.Calculate t PHL ,t PLH assuming the result of (b)is ‘C Leff =6.5fF’.(Assume an ideal step input,i.e.t rise =t fall =0.Do this part by computing the average current used to charge/dis-charge C Leff .)d.Find (W p /W n )such that t PHL =t PLH .e.Suppose we increase the width of the transistors to reduce the t PHL ,t PLH .Do we get a pro-portional decrease in the delay times?Justify your answer.f.Suppose V SB =1V,what is the value of V tn ,V tp ,V m ?How does this qualitatively affect C Leff ?ing Hspice answer the following questions.a.Simulate the circuit in Problem 10and measure t P and the average power for input V in :pulse(0V DD 5n 0.1n 0.1n 9n 20n),as V DD varies from 1V -2.5V with a 0.25V interval.[t P =(t PHL +t PLH )/2].Using this data,plot ‘t P vs.V DD ’,and ‘Power vs.V DD ’.Specify AS,AD,PS,PD in your spice deck,and manually add C L =6.5fF.Set V SB =0Vfor this problem.b.For Vdd equal to 2.5V determine the maximum fan-out of identical inverters this gate candrive before its delay becomes larger than 2ns.c.Simulate the same circuit for a set of ‘pulse’inputs with rise and fall times of t in_rise,fall =1ns,2ns,5ns,10ns,20ns.For each input,measure (1)the rise and fall times t out_rise andV DD =2.5VV IN V OUTC L =C inv-gateL =L P =L N =0.25μmV SB-+(W p /W n =1.25/0.375)Figure 5.8CMOS inverter with capacitiveSection 5.1Exercises and Design Problems 187t out_fall of the inverter output,(2)the total energy lost E total ,and (3)the energy lost due to short circuit current E short .Using this data,prepare a plot of (1)(t out_rise +t out_fall )/2vs.t in_rise,fall ,(2)E total vs.t in_rise,fall ,(3)E short vs.t in_rise,fall and (4)E short /E total vs.t in_rise,fall.d.Provide simple explanations for:(i)Why the slope for (1)is less than 1?(ii)Why E short increases with t in_rise,fall ?(iii)Why E total increases with t in_rise,fall ?12.Consider the low swing driver of Figure 5.9:a.What is the voltage swing on the output node (V out )?Assume γ=0.b.Estimate (i)the energy drawn from the supply and (ii)energy dissipated for a 0V to 2.5V transition at the input.Assume that the rise and fall times at the input are 0.Repeat the analysis for a 2.5V to 0V transition at the input.pute t pLH (i.e.the time to transition from V OL to (V OH +V OL )/2).Assume the input rise time to be 0.V OL is the output voltage with the input at 0V and V OH is the output volt-age with the input at 2.5V .pute V OH taking into account body effect.Assume γ =0.5V 1/2for both NMOS and PMOS.13.Consider the following low swing driver consisting of NMOS devices M1and M2.Assumean NWELL implementation.Assume that the inputs IN and IN have a 0V to 2.5V swing andthat V IN =0V when V IN =2.5V and vice-versa.Also assume that there is no skew between INand IN (i.e.,the inverter delay to derive IN from IN is zero).a.What voltage is the bulk terminal of M2connected to?V in V out V DD =2.5V W L 3μm 0.25μm =p 2.5V0V C L =100fFW L 1.5μm 0.25μm=n Figure 5.9Low Swing DriverV LOW =0.5VOutM1ININ M225μm/0.25μm 25μm/0.25μmC L =1pFFigure 5.10Low Swing Driver188THE CMOS INVERTER Chapter 5b.What is the voltage swing on the output node as the inputs swing from 0V to 2.5V .Showthe low value and the high value.c.Assume that the inputs IN and IN have zero rise and fall times.Assume a zero skewbetween IN and IN.Determine the low to high propagation delay for charging the outputnode measured from the the 50%point of the input to the 50%point of the output.Assumethat the total load capacitance is 1pF,including the transistor parasitics.d.Assume that,instead of the 1pF load,the low swing driver drives a non-linear capacitor,whose capacitance vs.voltage is plotted pute the energy drawn from the lowsupply for charging up the load capacitor.Ignore the parasitic capacitance of the driver cir-cuit itself.14.The inverter below operates with V DD =0.4V and is composed of |V t |=0.5V devices.Thedevices have identical I 0and n.a.Calculate the switching threshold (V M )of this inverter.b.Calculate V IL and V IH of the inverter.15.Sizing a chain of inverters.a.In order to drive a large capacitance (C L =20pF)from a minimum size gate (with inputcapacitance C i =10fF),you decide to introduce a two-staged buffer as shown in Figure5.12.Assume that the propagation delay of a minimum size inverter is 70ps.Also assumeV DD =0.4VV IN V OUTFigure 5.11Inverter in Weak Inversion RegimeSection 5.1Exercises and Design Problems 189that the input capacitance of a gate is proportional to its size.Determine the sizing of thetwo additional buffer stages that will minimize the propagation delay.b.If you could add any number of stages to achieve the minimum delay,how many stages would you insert?What is the propagation delay in this case?c.Describe the advantages and disadvantages of the methods shown in (a)and (b).d.Determine a closed form expression for the power consumption in the circuit.Consider only gate capacitances in your analysis.What is the power consumption for a supply volt-age of 2.5V and an activity factor of 1?16.[M,None,3.3.5]Consider scaling a CMOS technology by S >1.In order to maintain compat-ibility with existing system components,you decide to use constant voltage scaling.a.In traditional constant voltage scaling,transistor widths scale inversely with S,W ∝1/S.To avoid the power increases associated with constant voltage scaling,however,youdecide to change the scaling factor for W .What should this new scaling factor be to main-tain approximately constant power.Assume long-channel devices (i.e.,neglect velocitysaturation).b.How does delay scale under this new methodology?c.Assuming short-channel devices (i.e.,velocity saturation),how would transistor widthshave to scale to maintain the constant power requirement?1InAdded Buffer StageOUTC L =20pF C i =10fF‘1’is the minimum size inverter.??Figure 5.12Buffer insertion for driving large loads.190THE CMOS INVERTER Chapter5DESIGN PROBLEMUsing the0.25μm CMOS introduced in Chapter2,design a static CMOSinverter that meets the following requirements:1.Matched pull-up and pull-down times(i.e.,t pHL=t pLH).2.t p=5nsec(±0.1nsec).The load capacitance connected to the output is equal to4pF.Notice that thiscapacitance is substantially larger than the internal capacitances of the gate.Determine the W and L of the transistors.To reduce the parasitics,useminimal lengths(L=0.25μm)for all transistors.Verify and optimize the designusing SPICE after proposing a first design using manual -pute also the energy consumed per transition.If you have a layout editor(suchas MAGIC)available,perform the physical design,extract the real circuitparameters,and compare the simulated results with the ones obtained earlier.。
(完整word版)数字电路习题
数字电路习题一、判断题1、当TTL与非门的输入端悬空时相当于输入为逻辑1.2、普通的逻辑门电路的输出端不可以并联在一起,否则可能会损坏器件。
3、三态门的三种状态分别为：高电平、低电平、不高不低的电压。
4、TTL OC门（集电极开路门）的输出端可以直接相连，实现线与.5、CMOS 电路和 TTL 电路在使用时，不用的管脚可悬空。
6、CMOS 电路比 TTL 电路功耗大。
7、在 TTL 电路中通常规定高电平额定值为 5V .二、选择题1、三态门输出高阻状态时，是正确的说法。
A。
用电压表测量指针不动 B.相当于悬空 C。
电压不高不低 D.测量电阻指针不动2、对于T T L与非门闲置输入端的处理,可以.A.接电源B。
通过电阻3kΩ接电源 C.接地D。
与有用输入端并联3、C M O S数字集成电路与T T L数字集成电路相比突出的优点是。
A.微功耗B。
高速度C。
高抗干扰能力 D.电源范围宽4、以下电路中常用于总线应用的有。
A。
T S L门（三态门） B.O C门 C.C M O S传输门 D.C M O S与非门5、下面几种逻辑门中，可以用作双向开关的是.A．C M O S传输门B．或非门Ｃ．异或门三、练习题1、如图所示各门电路均为 74 系列 TTL 电路，分别指出电路的输出状态（高电平、低电平或高阻态）2、如图所示各门电路均为 CC4000 系列的 CMOS 电路，分别指出电路的输出状态是高电平还是低电平。
3、半导体二极管的开关条件是什么?导通和截止时各有什么特点？4、半导体三极管的开关条件是什么？饱和导通和截止时个有什么特点？5、为实现图中输出端表达式的逻辑关系，请合理地将多余端C 进行处理.图（ a ）～（ c ）为 CMOS 电路，图（ d )为 TTL 电路.在 CMOS 电路中，要求至少采用两种方法。
6、 利用2输入与非门组成非门、与门、或门、或非门和异或门，要求列出表达式并画出最简逻辑图。
1+X集成电路理论知识复习题库含答案
1+X集成电路理论知识复习题库含答案1、组装电子产品有很高的技术要求，包括严格的安装顺序如（）。
A、先低后高B、先易后难C、先重后轻D、先一般元器件后特殊元器件答案：ABD2、电镀工序中在进行清洗后会进行干燥处理，一般采用（）或（）的方式。
A、悬挂晾干B、气泵吹干C、挤压速干D、高速甩干答案：BD略3、在集成电路制造工艺中，测量二氧化硅膜厚度的方法有（）。
A、比色法B、光干涉法C、椭圆偏振法D、四探针法答案：ABC4、运放组件的整体布局的一般按照以下顺序（）。
A、按照具体电路的对称性要求以及电路结构，将电路中的具体晶体管按照电路中的相对位置对称排布B、按照具体电路设计的文件，确定每个支路通过的最大工作电流C、按照每个支路的最大工作电流对应的导线宽度增加一定的裕量，确保电路的性能D、根据具体电路的要求，确定电路中的输入输出引线，确定其与电源和地在整体布局中的位置答案：ABCD5、切割机显示区可以进行（）、（）等操作。
A、给其他操作人员发送消息B、设置参数C、切割道对位D、操作过程中做笔记答案：BC略6、电镀的主要目的是增强暴露在塑封体外面的引线的（）和（）。
A、防水性B、抗氧化性C、抗腐蚀性D、耐高温能力E、美观性答案：BC略7、属于湿法刻蚀的优点的是（）。
A、各向同性B、各向异性C、提高刻蚀的选择比D、不产生衬底损伤答案：CD湿法刻蚀可以控制刻蚀液的化学成分，使得刻蚀液对特定薄膜材料的刻蚀速率远大于其他材料的刻蚀速率，从而提高刻蚀的选择比，同时也不产生衬底损伤。
湿法刻蚀的效果是各向同性的，这导致刻蚀后的线宽难以控制，是湿法刻蚀的缺点。
8、防静电铝箔袋的作用是（）。
A、防静电B、防电磁干扰C、防潮D、防水答案：ABCD防静电铝箔袋具有防静电、防电磁干扰、防潮三大功能，具有良好的防水、阻氧、避光等特点，可以最大程度地保护静电敏感元器件免受潜在静电危害。
9、在进入集成电路制造车间前注意着装规范，其目的是为了防止人体、衣物等产生（）和（）对芯片造成损害。
数字集成电路设计第四章习题
1. 如下图所示时钟数, 根据下表中提供的电容电阻数据, 计算从节点A到节点B的Elmore 延时。
图计算延时的RC树
表Values of the components in the RC tree
Resistor Value( ) Capacitor Value(fF)
R1 0.25 C1 250
R2 0.25 C2 750
R3 0.50 C3 250
R4 100 C4 250
R5 0.25 C5 1000
R6 1.00 C6 250
R7 0.75 C7 500
R8 1000 C8 250
3等分并插入2个传播延时为100ps的反相器，计算在这种情况下各层上整个导线的传播延时。
3．设计一个时钟分布网络，在各个时钟之间的最小偏差是很关键的问题，从一个时钟网络中抽象出如下图所示的RC网络，最初CLK3比CLK1和CLK2的路径更短，为了补偿这一不平衡，在CLK3的路径中插入一个传输门。
1)写出节点CLK3、CLK1和CLK2的时间常数，假设传输门用R3模拟；
2)如果R1=R2=R4=R5=R，C1=C2=C3=C4=C5=C，R3为多大时可以平衡；
3)当R=750Ω，C=200fF，传输门有多大的W/L比可以消除偏差；。
数字电路总复习题
09级4班数字电路总复习题没有DAC 、ADC 部分一、填空题1．在逻辑电路中,任意时刻的输出状态仅取决于该时刻输入信号的状态,而与信号作用前电路的状态无关,这种电路称为 ;因此在电路结构上,一般由 组合而成;2．3510= 2, 101012= 103． 电路能产生周期的脉冲波形； 电路可将正弦波变成矩形波;4．三态门具有 、 、 三种状态,因此常用于 结构中;5．右图所示的波形是一个 进制 加、减法计数器的波形;若由触发器组成该计数器,触发器的个数应为 ,它有 个无效状态,分别为 和 ;6．组合逻辑电路的设计步骤为：① ； ② ； ③简化和变换逻辑表达式,从而画出逻辑图;7．欲将一个频率为10kH Z 的矩形波变换成频率为1kH Z的矩形波,应选用 电路;8．逻辑表达式C AB Y +A CD+A BD 的最小项之和的形式是：;9．分析组合逻辑电路的步骤为：① ；② ；③ ；④ 根据真值表和逻辑表达对逻辑电路进行分析,最后确定其功能;10．为实现图逻辑表达式的功能,请将多余输入端C 进行处理只需一种处理方法其中图Y 1、Y 2为TTL 电路,图Y 3、Y 4为CMOS 电路;Y 1的C 端应 ,Y 2的C 端应 ,Y 3的C 端应 ,Y 4的C 端应 ;11．在任何时刻,输出状态只决定于同一时刻各输入状态的组合,而与先前状态无关的逻 辑电路称为 ,而若逻辑电路的输出状态不仅与输出变量的状态有关,而且还与系统原先的状态有关,则称其为 ;12．双极性三极管饱和工作状态的条件是 ;13．正与门与 门等效;CP 0Q 1Q 2Q14．“逻辑相邻”是指两个最小项________因子不同,而其余因子________;15．数字比较器是用于对两数 ,以判断其 的逻辑电路; 16．数2转化为八进制数是 ,十六进制数是 ;17．在同步计数器中,各触发器的CP 输入端应接 时钟脉冲;18．有一两端输入的TTL 与非门带同类负载门的个数为N,已知门电路的|I IS |=,|I IH |=10μA,|I OL |=15mA |I OH |=400μA 试问电路带负载门个数N= ;19．四位双向移位寄存器T4194的功能表如表所示;由功能表可知,要实现保持功能,应使 ,当1 D R ,S 1=1,S 0=0时,电路实现 功能;20．图中所示电路中,当电路其他参数不变：仅R b 减小时,三极管的饱和程度 ；仅R C 减小时,三极管的饱和程度 ,它的饱和压降U CES ;21．TTL 反相器电气特性如图所示,该门电路输入短路电流I IS = ,高电平输入电流I IH = 若带同类门,其带负载能力N ≤ ;22．由555定时器构成的施密特触发器,已知电源电压U CC =9V 其正向阈值电压U+= ；负向阈值电压U-= ,回差电压△U T = ;23．某计数器的状态转换图如图所示,试问该计数器是一个 进制法计数器,它有 个有效状态, 个无效状态,该电路 自启动;若用JK 触发器组成,至少要 个;24．单稳态触发器的特点是电路有一个 和一个 ;25．TTL 或非门多余输入端的处理是 ;7．电路中的二极管均为理想二极管,判断各二极管的状态和输出电压V o的大小;D 1 ； D 2 ；D 3 ； V O ;26．555定时器构成的单稳态触发器,该电路是触发脉冲的 触发,有两种状态： 和 ；电路要求输入信号负脉冲的宽度必须 输出脉冲宽度;27．三个JK 触发器组成的计数器,最多有效状态是 个,它是 进制计数器；若要构成五进制计数器,最少需 个触发器,它的无效状态有 个;28．在下图所示的组合电路框图中 ,若A 1 , A 2 …A m 为输入逻辑变量 ,Y 1 ,Y 2…Yn 为输出逻辑函数,其输入和输出间的函数关系可表示为Y 1 = f 1 由此可见,组合电路的输出只决定于 而与 无关;29．十六进制数64H转换为十进制数则为;30．将二进制数11010102转换成十进制数是,八进制数是,十六进制数是;31．右图为555定时器构成的输入与输出的波形,该电路t w≈电路正常工作时,要求T W t w;32．已知如图a所示各电路输出电压波形如图b所示,填写电路名称;电路1为,电路2为,电路3 ;33．施密特触发器和单稳态触发器是一种脉冲电路,多谐振荡器是一种脉冲电路;34．若在时钟脉冲高电平期间RS端信号不发生变化,则同步RS触发器的状态变化是在时钟脉冲发生的,主从RS触发器的状态转变是在时钟脉冲发生的;35．TTL与非门电路中,为了提高工作速度采到了以下措施：1 ,2 ,3 ;二、选择题1．用555定时器组成的三种应用电路如下图所示,其中图a对应电路名称是,图b对应电路名称是,图c对应电路名称是;⑴施密特触发器；⑵单稳态触发器；⑶多谐振荡器;2．以下单元电路中,具有“记忆”功能的单元电路是：A、运算放大器；B、触发器；C、TTL门电路；D、译码器；3．以下各电路中属于组合逻辑电路有;A、编码器B、译码器C、寄存器D、计数器4．在数字电路中,晶体管的工作状态为：A、饱和；B、放大；C、饱和或放大；D、饱和或截止；5．图a 由555定时器组成的何种电路 ,已知图a 输入,输出脉冲波形如图b 所示,则输出脉冲的宽度Tw=A 单稳态触发器B 施密特触发器C 多谐振荡器⑴T W =⑵T W =⑶T W =2RC6．电路如图所示,指出能实现1n n Q AQ +=的电路是 ,实现1n n Q A Q +=的电路是 ,实现1n n Q A Q +=+的电路是 ;7．下图所示波形是一个 进制加法计数器的波形图;试问它有 个无效状态;A 二；B 四 ；C 六；D 八8．半加器的逻辑关系是A 、与非B 、或非C 、 与或非D 、异或9．有四个触发器的二进制计数器,它们有 种计数状态;A 、8B 、16；C 、 256D 、64;10．下列函数中等于A 的是 ;A 、A+1B 、A+A D 、AA+B11．图中所示电路中图 的逻辑表达式AB F =12．摩根定律反演律的正确表达式是：A 、;B A B A ⋅=+ B 、;B A B A +=+C 、;B A B A +=+D 、;B A B A ⋅=+13．在555定时器组成的三种电路中,能自动产生周期为T=R 1+2R 2C 的脉冲信号的电路是 ; ⑴施密特触发器 ；⑵单稳态触发器 ；⑶多谐振荡器;14．指出四变量A 、B 、C 、D 的最小项应为A 、)(D C AB + B 、DC B A +++C 、D C B A +++ D 、CD B A15．右图CT54H 系列的TTL 门电路的输出状态A 、高电平B 、低电平C 、高阻态D 、无法确定；16．指出下列各种类型的触发器中能组成移位寄存器的应该是A 、基本RS 触发器B 、同步RS 触发器C 、主从结构触发器D 、维持阻塞触发器；17．下列说法正确的是：A 、单稳态触发器是振荡器的一种B 、单稳态触发器有两个稳定状态C 、JK 触发器是双稳态触发器D 、振荡器有两个稳定状态18．图示为一简单的编码器,其中E 、F 、G 是一般信号,A 、B 是输出二位二进制代码变量,今令 AB = 10 ,则输入的信号是 ;A 、EB 、FC 、G19．设所有触发器的初始状态皆为0,找出下图各触发器在时钟信号作用下输出电压波形不为0的是： 图 ;20．组合逻辑电路任何时刻的输出信号与该时刻的输入信号 ,与电路原来所处的状态A 、关,无关B 、无关,有关C 、有关,无关D 、有关,有关21．在函数K=AB+CD 的真值表中,F=1的状态有多少个A 、2B 、4C 、6D 、7；E 、1622．电路如图所示,这是由定时器构成的：A 多谐振荡器B 单稳态触发器C 施密特触发器D 双稳态触发器23．如图所示TTL 电路中逻辑表达式为Y=A+B 的是 ;24．欲将一正弦波信号转换为与之频率相同的矩形脉冲信号,应采用：A 、单稳态触发器B 、施密特触发器C 、 A/D 转换器 D 、移位寄存器25． 74LS138是３线—８线译码器,译码为输入低电平有效,若输入为A 2A 1A 0=100时,输出01234567Y Y Y Y Y Y Y Y 为A 、00010000B 、11101111C 、D 、0000010026．下列数中最小数是 ;A 、 2610B 、10008421BCDC 、100102D 、37827．下列触发器中只有计数功能的是 ;A 、RS 触发器B 、JK 触发器C 、D 触发器 D 、T 触发器28．逻辑电路如图所示,其逻辑函数式为： A 、;B A B A + B 、;AB B A +C 、;B A B A +D 、;A AB +29．在图中,选择能实现给定逻辑功能A Y =的电路 ;30．TTL 与非门中多余的输入端应接电平是：A 、低B 、高C 、地D 、悬空31．特性征方程中含有约束条件的触发器是：A 、主从RS 触发器B 、主从JK 触发器C 、JK 边沿触发器D 、D 边沿触发器32．CMOS 传输门相当于一个：A 、与门B 、非门C 、或门D 、开关33．不能用来描述组合逻辑电路的是：A 、真值表B 、卡诺图C 、逻辑图D 、驱动方程34．下列电路中,不属于组合电路的是：A 、数字比较器B 、寄存器C 、译码器D 、全加器35．下列逻辑代数运算错误的是：A 、A+A=AB 、A 0=⋅AC 、A ·A = 1D 、A+1=A36．NMOS 管的开启电压U GSth =2V 外加漏源电压U DD =10V ,为使管子截止,则要求U GSth1 >2V 2=2V 3<2V37．二进制数B 转换为十进制数则为：A 、B 、11.75C 、D 、38．JK 触发器的特征方程为：A 、1n n n J K Q Q Q +=+B 、 Q Q n n K J +=+1C 、 Q Q n n K J +=+1D 、 Q Q nn K J +=+139．二进制加法计数器从0 计到十进制数12时,需要个 触发器构成,它有 个无效状态;A 、4B 、3C 、8D 、1640．下列逻辑代数运算错误的是：A 、A 00=⋅B 、A+1=AC 、A A =⋅1D 、A+0=A41．如图所示CMOS 电路中逻辑表达式Y=A 的是 ;42．逻辑函数LA 、B 、C 、D=()()15.14.13.12.11.109,6,5,2,1d m +∑ 化简结果为：A 、D C A D CB DC A ++ B 、D C A D C B CD A ++C 、D C D C + D 、CD D C +43．当Cr=0时,移位寄存器处于状态：A 、保持B 、左移C 、右移D 、清除三、判断题1．编码器,译码器,数据选择器都属于组合逻辑电路;2．请将下列触发器的特性方程与其对应触发器用线连接起来特性方程中,触发器的输入端用字符A 、B ……．表示;1 T 触发器 a 1n n n Q AQ BQ +=+2 RS 触发器 b 1n Q A +=3 JK 触发器 c 1 0n n Q A BQ AB +=+=4 D 触发器 d 1n n n Q AQ A Q +=+3．化简逻辑函数,就是把逻辑代数式写成最小项和的形式;4．对于TTL 数字集成电路来说,在使用中应注意：电源电压极性不得接反,其额定值为5V;5．主从RS 触发器能够克服空翻,但不能消除不定态;6．二进制加法计数器从0计数到十进制24时,需要5个触发器构成,有7个无效状态;7．在所示的反向器电路中,为了加深三极管的饱和深度,可以采用下列方法中的哪一种 在可以采用的方法后面画√,在不可以采用的方法后面画×;1三极管的β 2减小R C3减小R 2 4减小E Q5 加大R 38．“同或”逻辑关系是,输入变量到值相同输出为1；取值不同,输出为零;9．有8个触发器数目的二进制计数器,它具有256个计数状态;10．单稳态触发器中,欲加大输出脉冲宽度,可增加输入脉冲宽度;11．某一时刻编码器只能对一个输入信号进行编码;12．要实现图中各TTL 门电路输出端所示的逻辑关系,各电路的解法是否正确a b c d13．常用逻辑门电路的真值表如下表所示,试判断它们分别属于哪种类型门电路．即F 1、F 2、F 3、F 4和F 5分别属于何种常用逻辑门;F 1 ；F 2 ；F 3 ； F 4 ；F 5 ;14．用二进制代码表示某一信息称为编码;反之把二进制代码所表示的信息翻译出来称为译码;15．数字钟计时是否准确主要取决于计数器的精度;16．N 进制计数器可以实现N 分频；17．利用卡诺图化简逻辑表达式时,只要是相邻项即可画在包围圈中;18．下图是用D 触发器组成的寄存器电路;当在u i 端随CP 脉冲依次输入1011时,经过四个CP 脉冲后,串行输出端的状态是1011;Q 1Q 2Q 3Q 4的初始状态是0000;19．TTL 与非门输出端不能并联使用；20．为了确保逻辑输出的确定性,JK 触发器的J 和K 输入端不能同时为逻辑高电平1 ;21．译码器、计数器、全加器、寄存器都是组合逻辑电路;22．判断图中所示各CMOS 电路的逻辑表达式是否正确;对者√ 错的打×;23．C B A Y ⋅=的对偶式是C B A Y ++='24．连续异或85个“1”的结果是0 ;25．全加器的输出不仅取决于输入,同时还取决于相邻低位的进位,因此说全加器属于时序逻辑电路;26．当TTL 门电路的输入端接地时,才称之为该输入端所接为逻辑低电平;27．四位移位寄存器经过4个CP 脉冲后,四位数码恰好全部移入寄存器,因此可以得到四位串行输出;28．对于TTL 数字集成电路来说,在使用中应注意：不使用的输入端接1;29．数据选择器能从多个输入信号中选择2个信号送到输出器;A B F 1 F 2 F 3 F 4 F 5 0 0 0 1 0 0 1 0 1 1 1 0 1 0 1 0 1 1 0 1 0 1 1 0 0 1 1 030．两个不同最小项乘积恒为零;31．如果在时钟脉冲CP=1的期间,由于干扰的原因使触发器的数据输入信号经常有变化,此时不能选用TTL 主从型结构的触发器,而应选用边沿型和维持阻塞型的触发器;32．对于低电平输入有效的基本RS 触发器,其RS 端的输入信号不得同时为低电平;33．对于高电平输入有效的基本RS 触发器,其RS 端的输入信号不得同时为高电平;34．判断下图所示各触发器中哪些触发器的状态1n n Q Q += ;35．要实现图中各TTL 电路输出端所示的逻辑关系,各电路的接法是否正确;36．图中均为TTL 电路,试问哪些电路能实现CD AB +的逻辑关系37．C B A Y ⋅=的对偶式是C B A Y ++=' ;38．TTL 与非门输入端可以接意值电阻;39．对于TTL 数字集成电路来说,在使用中应注意;输入端可以串有电阻器,但其数值不应大于关门电阻;四、计算题本题分,共题1．利用卡诺图化简:Y+ABCABD++=++CADCDCABDCA2．试分析下图时序电路的逻辑功能,写出驱动方程状态方程和输出方程;3．分别写出如图所示的各触发器次态的逻辑函数表达式;4．写出如图所示电路逻辑表达式,并将其化简后用最简单的组合电路实现此组合电路; 5．如图a所示逻辑电路,已知CP为连续脉冲,如图b所示,试画出Q1,Q2的波形;6．用5G555设计一个多谐振荡器,要求输出脉冲的振荡频率为f 0 = 20KHz 占空比D = 25% ;7．图a 是555定时器构成的单稳态电路,已知u i 和u c 的波形见图b;1对应画出u o 的波形;2估算脉宽t w 的数值;8．十进制计数器T4160构成的计数器电路如图所示,试分析该电路是几进制计数器,画出状态转换图;T4160的功能表见下表;9．用代数法将下列函数化简为最简与或表达式; 1;)(AC BC AB C B A ABC Y ++⋅+++= 2G BC E C B D C B C D AC B A Y +++++=10．在图中所示的时序电路中,X 为控制信号,Q 1、Q 2为输出信号,CP 为一连续脉冲;1画出其状态转换图;2说明电路的功能;11．设计一多数表决电路;要求A 、B 、C 三人中只要有半数以上同意,则决议就能通过;但A 还具有否决;计算振荡器振荡12．用555定时器组成的多谐振荡器电路如下图所示,已知：V cc=15V,R1=R2=5K,C=F周期T;13．设计一个组合电路,其输入是十进制数的8421编码,输出为3循环码,见真值表;14．某产品有A、B、C、D四项质量指标;规定：A必须满足要求,其它三项中只要有任意两项满足要求,产品算合格,试列出真值表,通过卡诺图求出产品合格的最简与或表达式,并画出用与非门实现的逻辑图;15．电路如图所示,已知：CMOS与非门U OL=0V、U OH=5V、I OH=、三极管β=40、U BE=、U CES=;为实现F=AB的逻辑功能,求R b的取值范围;16．如图所示电路图中,试问在哪些输入情况输出Z=117．已知OC 门I OL ≤25mA 、I OH ≤100,用OC 门驱动三极管电路;已知三极管β=20、U BES =、U CES =;求电路中R b 的到值;18．1证明等式：C AB C B C A AB +=++2化简函数：Y 1=∑mn 0,1,3,5,8,9+∑d 10,11,12,13,14,1519．试分析如图所示电路,写出驱动方程,状态方程,画出状态图,说明计数器类型;20．触发器电路如图所示,试根据CP,A,B 的波形,对应画出输出端Q 的波形,设触发器的初试状态为0;21．下图是555定时器构成的施密特触发器,已知电源电压V CC =12V ,求：1电路的U T+,U T-和△U T 各为多少2如果输入电压波形如图,试画出输出u O 的波形;3若控制端接至+6V ,则电路的U T+,U T-和△U T 各为多少22．将下图所示电路化简成最简与或表达式;23．试判断如图所示电路中硅三极管工作在什么状态 并求集电极电位;五、综合题1．分析下图时序电路的逻辑功能,写出电路驱动方程状态方程,画出状态转换图;2．分析图中所示的时序电路;写出电路的驱动方程和状态方程；画出完整的状态转换图,画出时序图至少有六个CP;假设触发器的初态均为0;3．由理想二极管组成的幅度选择电路如图所示,试求电路的输出电压U O 值,电流I 值;4．试用图中所示的或非门实现下列函数：1;1A F = 2;2AB F = 3;3B A F += 4;4B A F ⊕=5．在各种功能的触发器中,若输入端用A,B 单端输入用A,双端输入A,B 表示,请根据表对应写出JK 触发器,D 触发器和T 触发器的现状;6．写出图中所示电路的最简与或表达式;7．下图所示是一什么电路,其特点是什么8．化简图所示的电路,要求化简后的电路逻辑功能不变;9．用卡诺图化简下列函数,并用与非门画出逻辑电路图;FA 、B 、C 、D=Σ0、2、6、7、8、9、10、13、14、1510．画出如图所示各触发器在时钟脉冲作用下输出端的电压波形;设所有触发器的初始状态皆为Q = 0;11．1或非门能否作反相器使用若可以其输入端如何连接2写出下图CMOS 门电路输出函数式：12．画出如图时序电路的状态转换图和时序图;13．已知逻辑函数A C C B B A F ++=,试用真值表,卡诺图及逻辑图表示;14．有一个“与非”门组成的基本S-R 锁存器2当输入脉冲如图b波形时重复上述练习;15．根据要求完成下列各题;利用二输入端与非门组成非门、与门、或门、或非门和异或门,要求列出表达式并画出最简逻辑图;16．分析如图所示逻辑电路的逻辑功能,设各触发器的初始状态均为“0”,试列出它的表达式,画出Q0、Q1、Q2的工作波形图;17．电路如图所示,写出状态方程,列状态转换表,画出状态转换图,并说明该电路的逻辑功能;1写出电路的驱动方程和状态方程；2画出状态转换图,判断能否启动；3说明该电路的逻辑功能;。
(参考资料)数字集成电路课后习题1-4章作业解析
QB0 =−3×10−7 C / cm××1100−−76
=−0.188 V
= QOX COX
6= ×1011.16××11.60−×610−19
0.06 V
VT0 =−0.99 − (−0.88) − (−0.188) − 0.060 =+0.018 V
计算 PMOS 器件的阈值电压：
VGS −VT + EC L
(1.2 − 0.4)(6)(0.2) 1.2 − = 0.4 + (6)(0.2)
0.48V
VDS = 0.2V
∴ VDS < VDSAT
d. 饱和
VGS>VT，VD > VG 肯定工作在饱和区。对于长沟道器件，如果满足这个关系 就工作在饱和区。而发生速度饱和的短沟道器件的 VDSAT 比长沟道器件的要 小，如果电压偏置能使长沟道器件饱和，那么肯定能使速度饱和的短沟道器件 饱和。
VGS = VG −VS = 1.2 −1.1 = 0.1V V=T V= T 0 0.4V ∴ VGS < VT
c. 线性
VGS = VG −VS = 1.2 − 0 = 1.2V V=T V= T 0 0.4V ∴ VGS > VT
不在饱和区的判断依据：
= VDSAT
(= VGS −VT ) EC L
(N 型)
对于(b)中的 PMOS 器件：
NI
= − QI q
= − (1.6
×10−6 )(1.24 1.6 ×10−19
−
0.4)
= 8.4 ×1012 ions / cm2
(P 型)
d) 从上面的计算可以看到，NMOS 用 N 型多晶硅栅和 PMOS 用 P 型多晶硅栅算得的阈值 电压比较小，在沟道区使用与衬底相同的离子掺杂即可调整到期望值(NMOS：P 型注 入；PMOS：N 型注入)。如果我们在 MOS 管的栅极中采用跟衬底相同类型的离子注 入，得到的阈值电压很大，偏离期望值很多，调整起来比较困难。另外，源极和漏极 的制作过程采用自对准工艺，如果栅极的注入类型和源漏一致，一步即可完成离子注 入，简化了器件制作的工艺流程。
数字集成电路部分课后习题chapter11_ex
1Chapter 11 Problem SetChapter 11PROBLEMS1.[E, None, 11.6] For this problem you are given a cell library consisting of full adders and two-input Boolean logic gates (i.e. AND, OR, INVERT, etc.).a.Design an N-bit two's complement subtracter using a minimal number of Boolean logicgates. The result of this process should be a diagram in the spirit of Figure 11.5 . Specifythe value of any required additional signals (e.g., C in ).b.Express the delay of your design as a function of N , tcarry , t sum , and the Boolean gate delays(t and , t or , t inv , etc.).2.[M, None, 11.6] A magnitude comparator for unsigned numbers can be constructed using fulladders and Boolean logic gates as building blocks. For this problem you are given a celllibrary consisting of full adders and arbitrary fan-in logic gates (i.e., AND, OR, INVERTER,etc.).a.Design an N -bit magnitude comparator with outputs and A = B using a minimalnumber of Boolean logic gates. The result of this process should be a diagram in the spiritof Figure 11.5. Specify the value of any required control signals (e.g., C in ).b.Express the delay of your design in computing the two outputs as a function of N , tcarry ,t sum , and the Boolean gate delays (t and , t or , t inv , etc.).3.3.[E, None, 11.6] Show how the arithmetic module in Figure 0.1 can be used as a comparator.Derive an expression for its propagation delay as a function of the number of bits.4.[E, None, 11.6] The circuit of Figure 11.2 implements a 1-bit datapath function in dynamic(precharge/evaluate) logic.a.Write down the Boolean expressions for outputs F and G . On which clock phases are out-puts F and G valid?b.To what datapath function could this unit be most directly applied (e.g., addition, subtrac-tion, comparison, shifting)?5.[M, None, 11.3] Consider the dynamic logic circuit of Figure 0.2 .a.What is the purpose of transistor M1? Is there another way to achieve the same effect, butwith reducing capacitive loading on the clock Φ?A B ≥Figure 0.1Arithmetic module.a i a ib j b jc jd jc j +1j+1c 0c 1d 0d 1c 1c 2d 1d 2c 2c 3d 2d 3c 3c 4d 3d 4a 0b 0a 1b 1a 2b 2a 3b 32Chapter 11 Problem Setb.How can the evaluation phase of F be sped up by rearranging transistors? No transistorsshould be added, deleted, or resized.c.Can the evaluation of G be sped up in the same manner? Why or why not?6.[M, SPICE, 11.3] The adder circuit of Figure 0.3 makes extensive use of the transmissiongate XOR. V DD = 2.5 V.a.Explain how this gate operates. Derive the logic expression for the various circuit nodes.Why is this a good adder circuit?b.Derive a first-order approximation of the capacitance on the C o -node in equivalent gate-capacitances. Assume that gate and diffusion capacitances are approximately identical.Compare your result with the circuit of Figure 11-6 .c.Assume that all transistors with the exception of those on the carry path are minimum-size. Use 4/0.25 NMOS and 8/0.25 PMOS devices on the carry-path. Using SPICE simu-lation, derive a value for all important delays (input-to-carry, carry-to-carry, carry-to-sum).A C inB B A ΦΦA B C in ABC inF GFigure 0.2Datapath module bit-slice.M 1Figure 0.3Quasi-clocked adder circuit.A A iV C oC i Signal setup Carry generationSum generationDigital Integrated Circuits - 2nd Ed 37.[M, None, 11.3] The dynamic implementation of the 4-bit carry-lookahead circuitry from Fig.11-21 can significantly reduce the required transistor count.a.Design a domino-logic implementation of Eq. 11.17 . Compare the transistor counts of thetwo implementations.b.What is the worst-case propagation delay path through this new circuit?c.Are there any charge-sharing problems associated with your design? If so, modify yourdesign to alleviate these effects.8.[C, None, 11.3] Figure 0.4 shows a popular adder structure called the conditional-sum adder.Figure 0.4.a shows a four-bit instance of the adder, while 0.4.b gives the schematics of thebasic adder cell. Notice that only pass-transistors are used in this implementation.a.Derive Boolean descriptions for the four outputs of the one-bit conditional adder cell.b.Based on the results of describe how the schematic of 0.4.a results in an addition.c.Derive an expression for the propagation delay of the adder as a function of the number ofbits N . You may assume that a switch has a constant resistance R on when active and thateach switch is identical in size.9.[M, None, 11.3] Consider replacing all of the NMOS evaluate transistors in a dynamicManchester carry chain with a single common pull-down as shown in Fgure 0.5.a. Assumethat each NMOS transistor has (W /L )N = 0.5/0.25 and each PMOS has (W /L )P = 0.75/0.25.Further assume that parasitic capacitances can be modeled by a 10 fF capacitor on each of theFigure 0.4Conditional-sum adder.A A B B A A B S 0A A B B AA B S 1AB A A AC 0ABA AAC 1(b) Conditional adder cell (a) Four-bit conditional-sum adderS 0S 1S 2S 3C out Conditional Cell Conditional Cell Conditional Cell ConditionalCellC 1C 0S 1S 0C 1C 0S 1S 0C 1C 0S 1S 0C 1C 0S 1S 0B 3A 3B 2A 2B 1A 1B 0A 04Chapter 11 Problem Setinternal nodes: A , B , C , D , E , and F . Assume all transistors can be modeled as linear resistorswith an on-resistance, R on = 5 k Ω.a.Does this variation perform the same function as the original Manchester carry chain?Explain why or why not.b.Assuming that all inputs are allowed only a single zero-to-one transition during evalua-tion, will this design involve charge-sharing difficulties? Justify your answer.plete the waveforms in Figure 0.5b for P 0 = P 1 = P 2 = P 3 = 2.5 V and G 0 = G 1 = G 2 =G 3 = 0 V. Compute and indicate t pHL values for nodes A , E , and F . Compute and indicate10.[M, None, 11.3] Consider the two implementations of Manchester carry gates in Figure 11-8.pare the delay per segment of the two implementationsb.Compare the layout complexities of the two gates using stick diagrams.c.In the precharged Manchester carry chain using the gate from b. find the probability thatthe carry signal is propagated from the 15th to the 16thbit of a 32-bit adder, assuming ran-dom inputs.11.[C, None, 11.3] Consider the Radix-4 and Radix-2 Kogge-Stone adders from Figures 11-22and 11-27 extended to 64-bits. All gates are implemented in domino and all gates in a stagehave the same size. The adders have an overall fanout (electrical effort) of 6.ing logical effort, identify the critical path.b.Size the gates for minimum delay (hint: don't forget to factor in branching). Which adderis faster?c.Let's now consider sparse versions of each of the above trees. In a tree with a sparseness of2, only every other carry is computed and it is used to select 2 sums. Similarly, a tree witha sparseness of 4 computes every fourth carry - and that carry signal is used to select 4sums. Repeat a. and b. for Radix-2 and Radix-4 trees with sparseness of 2 and 4 and com-pare their speed. Which adder is fastest?pare the switching power of all adders analyzed in this problem.12.[C, None, 11.3] In this problem we will analyze a carry-lookahead adder proposed by H. Lingmore than 20 years ago, but still among the fastest adders available. In a conventional adder,in order to add two numbersA = a n −12n −1 + a n −22n −2 + .... + a 020B = b n −12n −1 + b n −22n −2 + .... + b 020we first compute the local carry generate and propagate terms:P 0C in P 1G 0P 2G 1P 3G 2G 3φφV DD Figure 0.5Alternative dynamic Manchester carry-chain adder.A B C D E F (a) Circuit schematic (b) Partial waveformsφAEFCDigital Integrated Circuits - 2nd Ed 5g i = a i b i pi = a i + b ithen, with a ripple or a tree circuit we form the global carry-out terms resulting from the recurrence relation:G i = g i + p i G i −1Finally, we form the sum of A and B using local expressions:In the conventional adder, the terms G i have, as described, a physical significance. However,an arbitrary function could be propagated, as long as sum terms could be derived. Ling'sapproach is to replace G i with:H i = G i + Gi −1i.e. H i is true if "something happens at bit i " - there is a carry out or a carry in. H i is so-called"Ling's pseudo-carry".a.Show that:H i = g i + ti −1H i −1where p i = a i + b i (it was Ling’s idea to change the notation).b.Find a formula for computing the sum out of the operands and Ling's pseudo-carry.c.Unroll the recursions for G i and H i for i = 3. You should get the expressions fpr G 3 and H 3as a function of the bits of input operands. Simplify the expressions as much as possible.d.Implement the two functions using n-type dynamic gates. Draw the two gates and size thetransistors. Which one helps us build a faster adder? Explain your answer.13.[M, None, 11.4] An array multiplier consists of rows of adders, each producing partial sumsthat are subsequently fed to the next adder row. In this problem, we consider the effects ofpipelining such a multiplier by inserting registers between the adder rows.a.Redraw Figure 11-31 by inserting word-level pipeline registers as required to achievemaximal benefit to throughput for the 4x 4 multiplier. Hint: you must use additional regis-ters to keep the input bits synchronized to the appropriate partial sums.b.Repeat for a carry-save, as opposed to ripple-carry, architecture.c.For each of the two multiplier architectures, compare the critical path, throughput, andlatency of the pipelined and nonpipelined versions.d.Which architecture is better suited to pipelining, and how does the choice of a vector-merging adder affect this decision?14.[M, None, 11.4] Estimate the delay of a 16x16 Wallace tree multiplier with the final adderimplemented using a Radix-4 tree. One FA has a delay of t p , a HA 2/3*t p and a CLA stage½*t p .15.[E, None, 11.5] The layout of shifters is dominated by the number of wires running through acell. For both the barrel shifter and the logarithmic shifter, estimate the width of a shifter cellas a function of the maximum shift-width M and the metal pitch p .16.[E, None, 11.7] Consider the circuit from Figure 0.7 . Modules A and B have a delay of 10 nsand 32 ns at 2.5V, and switch 15 pF and 56 pF respectively. The register has a delay of 2 nsand switches 0.1 pF. Adding a pipeline register allows for reduction of the supply voltagewhile maintaining throughput. How much power can be saved this way? Delay with respectto V DD can be approximated from Figure 11-57.17.[E, None, 11.7] Repeat Problem 16, using parallelism instead of pipelining. Assume that a 2-to-1 multiplexer has a delay of 4 ns at 2.5 V and switches 0.3 pF. Try parallelism levels of 2and by 4. Which one is preferred?S i p i G i 1–⊕=6Chapter 11 Problem Set DESIGN PROBLEMUsing the 0.25 µm CMOS technology, design a static 32-bit adder, with the fol-lowing constraints:1.input capacitance on each bit is limited to not more than 50fF.2.each bit is loaded with 100fF.Use a carry lookahead tree of your choice for implementation. The goal is toachieve the shortest propagation delay.Determine the logic design of the adder and W and L of all transistors.Initially size the design using the method of logical effort. Estimate the capaci-tance of carry signal wires based on the floorplan. Verify and optimize thedesign using SPICE. Compute also the energy consumed per transition. If youhave a layout editor available, perform the physical design, extract the real cir-cuit parameters, and compare the simulated results with the ones obtained ear-lier. For implementation use the 144λ.bit-slice pitch, that corresponds to 36metal-1 tracks. Use metal 1 for cell-level power distrbution and intra-cell rout-ing, metal-2 for short interconnect and metal-3 and metal-4 for long carries.R e g is t er Re gis t e r Figure 0.6Pipelined datapath.A B In Out。
数字集成电路--电路、系统与设计(第二版)课后练习题 第六章 CMOS组合逻辑门的设计-Chapter 6 Designing
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Chapter 6 Problem Set
VDD F G
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Figure 6.6 Two-input complex logic gate.
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Design and simulate a circuit that generates an optimal differential signal as shown in Figure 6.7. Make sure the rise and fall times are equal.
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VDD E 6 A A 6 B 6 C 6 D 6 F A B C D 4 4 4 4 E 1 A B C D E 4 4 4 4 E 1 6 F 6 B 6 C 6 D
Chapter 6 Problem SetVDD 6Circ来自it ACircuit B
Figure 6.2 Two static CMOS gates.
Digital Integrated Circuits - 2nd Ed
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M2 W/L = 0.5μm/0.25μm Vout Vin M1 W/L = 4μm/0.25μm NMOS Figure 6.4 Pseudo-NMOS inverter.
a. What is the output voltage if only one input is high? If all four inputs are high? b. What is the average static power consumption if, at any time, each input turns on with an (independent) probability of 0.5? 0.1? c. Compare your analytically obtained results to a SPICE simulation.
数字集成电路5章[1]习题1
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说明：[难度等级（E容易M中等C难），需要的设计工具，与之相关的章节]第5章CMOS反相器4. [E, None, 3.3.3]对于图5.3中的输出负载为3pF的反相器：a. 计算t plh，t phl和t pb. 上升延时和下降延时是否相等？为什么？c. 计算静态和动态功耗，假设门的时钟频率尽可能的快。
图5.3 电阻负载反相器7. 考虑图5.5中的电路。
器件M1是一个标准的NMOS器件。
器件M2除了阈值电压为负并且其值为-0.4V之外，和M1有共同的特性。
假设耗尽型器件M2的所有电流公式和不等式（来决定工作模式）与规范的NMOS器件相同。
并假设输入IN有0V到2.5V的摆幅。
图5.5 一个耗尽型负载的NMOS反相器a.器件M2的栅极和源极相连。
如果V IN =0V，那么输出电压是多少？在稳态，对于这个输入，器件M2的工作模式是什么？b.计算V IN =2.5V时的输出电压。
为简化计算，你可以假设V OUT很小。
在稳态，对于这个输入，器件M2的工作模式是什么？c.假设Pr(LN=0)=0.3，这个电路的静态功耗是多少？8. [M, None, 3.3.3]一个NMOS晶体管用来向一个大电容充电，如图5.6所示：a. 确定这个电路的t pLH，假设输入节点有一个0到2.5V的理想阶跃信号。
b. 假设一个5kΩ的电阻R S用来对电容放电至地，确定t pHL的值。
c. 确定在对电容充电期间从电源得到多少能量。
其中多少能量在M1中被消耗？在放电期间，多少能量在下拉电阻上消耗？当R S减小至1kΩ时又是多少？d. NMOS晶体管用一个PMOS器件代替，k p和原先NMOS的k n相等。
替换后的结构是否比以前快？解释为什么。
图5.6 注明W/L比的电路图12. 考虑图5.9的低摆幅驱动：a. 输出节点（V out）的电压摆幅是多少？假设γ =0。
b. 输入端有一个从0V 到2.5V的翻转，估算（i）来自于电源的能量和（ii）能量损耗。