74HC165D

APPLICATIONS
• Parallel-to-serial data conversion
QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
SYMBOL
PARAMETER
tPHL/ tPLH
fmax CI CPD
propagation delay CP to Q7, Q7 PL to Q7, Q7 D7 to Q7, Q7
When PL is HIGH, data enters the register serially at the Ds input and shifts one place to the right (Q0 → Q1 → Q2, etc.) with each positive-going clock transition. This feature allows parallel-to-serial converter expansion by tying the Q7 output to the DS input of the succeeding stage.
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications • The IC06 74HC/HCT/HCU/HCMOS Logic Package Information • The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
UNIT
ns ns ns MHz pF pF
ORDERING INFORMATION See “74HC/HCT/HCU/HCMOS Logic Package Information”.
December 1990
2
Philips Semiconductors
8-bit parallel-in/serial-out shift register
OUTPUTS
Q7
L H
q6 q6 q7
Q7
H L
q6 q6 q7
December 1990
Fig.5 Logic diagram. 4
Philips Semiconductors
8-bit parallel-in/serial-out shift register
Product specification
AC CHARACTERISTICS FOR HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
SYMBOL PARAMETER
+25 min. typ. max.
74HC −40 to +85 min. max.
−40 to +125 min. max.
The 74HC/HCT165 are 8-bit parallel-load or serial-in shift registers with complementary serial outputs (Q7 and Q7) available from the last stage. When the parallel load (PL) input is LOW, parallel data from the D0 to D7 inputs are loaded into the register asynchronously.
19
tW
clock pulse width 80 17
HIGH or LOW
16 6
14 5
100
120
ns
20
24
17
20
tW
parallel load pulse 80 14
width; LOW
16 5
14 4
100
120
ns
20
24
17
20
trem
removal time
100 22
PL to CP, CE
X X ↑ ↑ X
DS
X X l h X
D0-D7
L H X X X
Q0
L H L H q0
Q1-Q6
L-L H-H
q0-q5 q0-q5 q1-q6
Note
1. H = HIGH voltage level h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition L = LOW voltage level I = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition q = lower case letters indicate the state of the referenced output one set-up time prior to the LOW-to-HIGH clock transition X = don’t care ↑ = LOW-to-HIGH clock transition
maximum clock frequency
input capacitance
power dissipation capacitance per package
CONDITIONS
TYPICAL
HC
HCT
CL = 15 pF; VCC = 5 V
16
14
15
17
11
11
56
48
3.5
3.5
notes 1 and 2
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
3
Philips Semiconductors
8-bit parallel-in/serial-out shift register
Product specification
20 8
17 6
125
150
ns
25
30
21
26
tsu
set-up time
80 11
Ds to CP, CE
16 4
14 3
1ห้องสมุดไป่ตู้0
120
ns
20
24
17
20
tsu
set-up time
CE to CP;
CP to CE
80 17 16 6 14 5
100
120
ns
20
24
17
20
tsu
set-up time
GENERAL DESCRIPTION
The 74HC/HCT165 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.
18 33
41
50
14 28
35
43
tPHL/ tPLH propagation delay
36 120
150
180 ns
D7 to Q7, Q7
13 24
30
36
10 20
26
31
tTHL/ tTLH output transition
19 75
95
110 ns
time
7 15
19
22
6 13
16
The clock input is a gated-OR structure which allows one input to be used as an active LOW clock enable (CE) input. The pin assignment for the CP and CE inputs is arbitrary and can be reversed for layout convenience. The LOW-to-HIGH transition of input CE should only take place while CP HIGH for predictable operation. Either the CP or the CE should be HIGH before the LOW-to-HIGH transition of PL to prevent shifting the data when PL is activated.
74HC/HCT165
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard ICC category: MSI
Dn to PL
80 22 16 8 14 6
UNIT
VCC WAVEFORMS (V)
tPHL/ tPLH propagation delay
52 165
205
250 ns
CE, CP to Q7, Q7
19 33
41
50
15 28
35
43
tPHL/ tPLH propagation delay
50 165
205
250 ns
PL to Q7, Q7
74HC/HCT165 8-bit parallel-in/serial-out shift register
Product specification File under Integrated Circuits, IC06
December 1990
Philips Semiconductors
8-bit parallel-in/serial-out shift register
35
35
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz fo = output frequency in MHz ∑ (CL × VCC2 × fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC − 1.5 V
Product specification
74HC/HCT165
PIN DESCRIPTION
PIN NO. 1 7 9 2 8 10 11, 12, 13, 14, 3, 4, 5, 6 15 16
SYMBOL
PL Q7 Q7 CP GND Ds D0 to D7 CE VCC
NAME AND FUNCTION asynchronous parallel load input (active LOW) complementary output from the last stage serial output from the last stage clock input (LOW-to-HIGH edge-triggered) ground (0 V) serial data input parallel data inputs clock enable input (active LOW) positive supply voltage
Product specification
74HC/HCT165
FEATURES
• Asynchronous 8-bit parallel load • Synchronous serial input • Output capability: standard • ICC category: MSI
74HC/HCT165
Fig.4 Functional diagram.
FUNCTION TABLE
OPERATING MODES
INPUTS
Qn REGISTERS
parallel load
serial shift hold “do nothing”
PL
L L H H H
CE
X X L L H
CP