基于vhdl时钟的设计与制作(附完整代码)

三、实验程序及部分仿真波形图
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity colock is
port(clk1,clk2,key1,key2: in std_logic;
abc:out std_logic_vector(2 downto 0);
led7s:out std_logic_vector(6 downto 0) );
end entity;
architecture one of colock is
signal ctrl:std_logic_vector(3 downto 0);
signal clk02,cs02,cm02,cs1,cs2,cm1,cm2,ch1,cp,k2,ck1,ck2:std_logic;
signal s1,s2,m1,m2,h1,h2,s01,s02,m01,m02,h01,h02,s001,s002,m001,m002,h001, h002,p1,p2,disp:std_logic_vector(3 downto 0);
signal ctrl0:std_logic_vector(8 downto 0);
signal tmp1,tmp2:std_logic_vector(9 downto 0);
signal k1:std_logic_vector(1 downto 0);
begin
--当处于按键调时状态时,根据K1的值来确定所调整的位,被调整的位送按键2产生的脉冲(CK2),其余进位脉冲赋0屏蔽掉
process(k1,clk2,clk02,cs2,cm2,ck2)
begin
case k1 is
when "00" => clk02<=clk2;cs02<=cs2;cm02<=cm2;
when "01" => clk02<=ck2;cs02<='0';cm02<='0';
when "10" => clk02<='0';cs02<=ck2;cm02<='0';
when "11" => clk02<='0';cs02<='0';cm02<=ck2;
when others => clk02<=clk2;cs02<=cs2;cm02<=cm2;
end case ;
end process;
--500进制计数器,每500ms对CP进行取反一次,用于闪烁控制
process(clk1)
begin
if rising_edge(clk1) then
if ctrl0<499 then ctrl0<=ctrl0+1;
else ctrl0<="000000000";cp<=not cp;
end if;
end process;
--数码管动态扫描,接138的输入端
process(clk1)
begin
if rising_edge(clk1) then
if ctrl<9 then ctrl<=ctrl+1;
else ctrl<="0000";
end if ;
end if ;
end process;
abc<=ctrl(2 downto 0);
--秒个位的计数
process(clk02)
begin
if rising_edge(clk02) then
if s01<"1001" then s01<=s01+1;cs1<='0';
else s01<="0000";cs1<='1';
end if;
end if;
end process;
--秒十位的计数
process(cs1)
begin
if rising_edge(cs1) then
if s02<"0101" then s02<=s02+1;cs2<='0';
else s02<="0000";cs2<='1';
end if;
end if;
end process;
--分个位的计数
process(cs02)
begin
if rising_edge(cs02) then
if m01<"1001" then m01<=m01+1;cm1<='0';
else m01<="0000";cm1<='1';
end if;
end if;
--分十位的计数
process(cm1)
begin
if rising_edge(cm1) then
if m02<"0101" then m02<=m02+1;cm2<='0';
else m02<="0000";cm2<='1';
end if;
end if;
end process;
--小时个位的计数
process(cm02)
begin
if rising_edge(cm02) then
if h02<"0010" then
if h01<"1001" then h01<=h01+1;ch1<='0';
else h01<="0000";ch1<='1';
end if ;
else
if h01<"0011"then h01<=h01+1;ch1<='0';
else h01<="0000";ch1<='1';
end if;
end if;
end if;
end process;
--小时十位的计数
process(ch1)
begin
if rising_edge(ch1) then
if h02<"0010" then h02<=h2+1;
else h02<="0000";
end if;
end if;
end process;
--按键一去抖动
process(clk1)
begin
if rising_edge(clk1) then
tmp1(0)<=key1;tmp1(9 downto 1)<=tmp1(8 downto 0);
1.第五章心得体会
通过此次课程设计使我更加深刻的认识EDA电子电路设计的各个模块。

时钟程序的编写按键调整时间同时让处于调整的位闪烁体会到各个进程之间通过控制信号建立起来的紧密联系，以及通过移位来达到按键的去抖动。

进行硬件调试时了解到芯片跟外围设备之间的连接程序功能由简单到复杂，通过课堂提问一步步完善时钟的各个模块，将本学期所学到的内容串到一起，最终完成课程设计。