FPGA门电路
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非门
module test(in,out);
input in;
output out;
assign out=~in;
endmodule
测试
`timescale 1ns/1ns
module test_tb();
reg in;
wire out;
test U(in,out);
initial
begin
#1 in=1;
wire out;
test U(in1,in2,out);
initial
begin
#0.5 in1=1;
in2=1;
#0.5 in1=1;
in2=0;
#0.5 in1=0;
in2=1;
#0.5 in1=0;
in2=0;
#5 $stop;
end
endmodule
或门
module test(in1,in2,out);
#1 in=0;
$stop;
end
endmodule
与门
module test(in1,in2,out);
input in1,in2;
output out;
assign out=in1&in2;
endmodule
测试
`timescale 1ns/1ns
module test_tb();
reg in1,in2;
in2=0;
in3=0;
#5 $stop;
end
endmodule
异或门
module test(in1,in2,out);
input in1,in2;
output out;
assign out= in1^in2;
endmodule
测试
`timescale 100ns/100ns
module test_tb();
module test_tb();
reg in1,in2,in3;
wire out;
test U(in1,in2,in3,out);
initial
begin
#0.5 in1=1;
in2=0;
in3=1;
#0.5 in1=1;
in2=1;
in3=1;
#0.5 in1=0;
in2=1;
in3=0;
#0.5 in1=0;
#0.5 in1=0;
in2=0;
#5 $stop;
end
endmodule
与或非门
module test(in1,in2,in3,out);
input in1,in2,in3;
output out;
assign out= ~((in1&in2)|in3);
endmodule
测试
`timescale 1ns/1ns
endmodule
测试
`timescale 1ns/1ns
module test_tb();
reg in1,in2;
wire out;
test U(in1,in2,out);
initial
begin
#0.5 in1=1;
in2=1;
#0.5 in1=1;
in2=0;
#0.5 in1=0;
in2=1;
reg in1,in2;
wire out;
test U(in1,in2,out);
initial
begin
#0.5 in1=1;
in2=0;
#0.5 in1=1;
in2=1;
百度文库#0.5 in1=0;
in2=1;
#0.5 in1=0;
in2=0;
#5 $stop;
end
endmodule
in2=1;
#0.5 in1=1;
in2=0;
#0.5 in1=0;
in2=1;
#0.5 in1=0;
in2=0;
#5 $stop;
end
endmodule
与非门
module test(in1,in2,out);
input in1,in2;
output out;
assign out= ~(in1&in2);
input in1,in2;
output out;
assign out=in1|in2;
endmodule
测试
`timescale 1ns/1ns
module test_tb();
reg in1,in2;
wire out;
test U(in1,in2,out);
initial
begin
#0.5 in1=1;
module test(in,out);
input in;
output out;
assign out=~in;
endmodule
测试
`timescale 1ns/1ns
module test_tb();
reg in;
wire out;
test U(in,out);
initial
begin
#1 in=1;
wire out;
test U(in1,in2,out);
initial
begin
#0.5 in1=1;
in2=1;
#0.5 in1=1;
in2=0;
#0.5 in1=0;
in2=1;
#0.5 in1=0;
in2=0;
#5 $stop;
end
endmodule
或门
module test(in1,in2,out);
#1 in=0;
$stop;
end
endmodule
与门
module test(in1,in2,out);
input in1,in2;
output out;
assign out=in1&in2;
endmodule
测试
`timescale 1ns/1ns
module test_tb();
reg in1,in2;
in2=0;
in3=0;
#5 $stop;
end
endmodule
异或门
module test(in1,in2,out);
input in1,in2;
output out;
assign out= in1^in2;
endmodule
测试
`timescale 100ns/100ns
module test_tb();
module test_tb();
reg in1,in2,in3;
wire out;
test U(in1,in2,in3,out);
initial
begin
#0.5 in1=1;
in2=0;
in3=1;
#0.5 in1=1;
in2=1;
in3=1;
#0.5 in1=0;
in2=1;
in3=0;
#0.5 in1=0;
#0.5 in1=0;
in2=0;
#5 $stop;
end
endmodule
与或非门
module test(in1,in2,in3,out);
input in1,in2,in3;
output out;
assign out= ~((in1&in2)|in3);
endmodule
测试
`timescale 1ns/1ns
endmodule
测试
`timescale 1ns/1ns
module test_tb();
reg in1,in2;
wire out;
test U(in1,in2,out);
initial
begin
#0.5 in1=1;
in2=1;
#0.5 in1=1;
in2=0;
#0.5 in1=0;
in2=1;
reg in1,in2;
wire out;
test U(in1,in2,out);
initial
begin
#0.5 in1=1;
in2=0;
#0.5 in1=1;
in2=1;
百度文库#0.5 in1=0;
in2=1;
#0.5 in1=0;
in2=0;
#5 $stop;
end
endmodule
in2=1;
#0.5 in1=1;
in2=0;
#0.5 in1=0;
in2=1;
#0.5 in1=0;
in2=0;
#5 $stop;
end
endmodule
与非门
module test(in1,in2,out);
input in1,in2;
output out;
assign out= ~(in1&in2);
input in1,in2;
output out;
assign out=in1|in2;
endmodule
测试
`timescale 1ns/1ns
module test_tb();
reg in1,in2;
wire out;
test U(in1,in2,out);
initial
begin
#0.5 in1=1;