函数信号发生器等vhdl程序
- 1、下载文档前请自行甄别文档内容的完整性，平台不提供额外的编辑、内容补充、找答案等附加服务。
- 2、"仅部分预览"的文档,不可在线预览部分如存在完整性等问题,可反馈申请退款(可完整预览的文档不适用该条件!)。
- 3、如文档侵犯您的权益，请联系客服反馈,我们会尽快为您处理(人工客服工作时间：9:00-18:30)。
分频器：
-- Copyright (C) 1991-2008 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- PROGRAM "Quartus II"
-- VERSION "Version 8.1 Build 163 10/28/2008 SJ Full Version" -- CREATED ON "Fri Sep 23 22:47:56 2011"
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY work;
ENTITY fenpin IS
PORT
(
clk1 : IN STD_LOGIC;
clk : OUT STD_LOGIC
);
END fenpin;
ARCHITECTURE bdf_type OF fenpin IS
ATTRIBUTE black_box : BOOLEAN;
nATTRIBUTE noopt : BOOLEAN;
COMPONENT \74163_0\
PORT(ENT : IN STD_LOGIC;
CLRN : IN STD_LOGIC;
CLK : IN STD_LOGIC;
ENP : IN STD_LOGIC;
LDN : IN STD_LOGIC;
RCO : OUT STD_LOGIC);
ATTRIBUTE black_box OF \74163_0\: COMPONENT IS true; ATTRIBUTE noopt OF \74163_0\: COMPONENT IS true;
COMPONENT \74163_1\
PORT(ENT : IN STD_LOGIC;
CLRN : IN STD_LOGIC;
CLK : IN STD_LOGIC;
ENP : IN STD_LOGIC;
LDN : IN STD_LOGIC;
RCO : OUT STD_LOGIC);
END COMPONENT;
ATTRIBUTE black_box OF \74163_1\: COMPONENT IS true; ATTRIBUTE noopt OF \74163_1\: COMPONENT IS true;
COMPONENT \74163_2\
PORT(ENT : IN STD_LOGIC;
CLRN : IN STD_LOGIC;
CLK : IN STD_LOGIC;
ENP : IN STD_LOGIC;
LDN : IN STD_LOGIC;
RCO : OUT STD_LOGIC);
END COMPONENT;
ATTRIBUTE black_box OF \74163_2\: COMPONENT IS true; ATTRIBUTE noopt OF \74163_2\: COMPONENT IS true;
COMPONENT \74163_3\
PORT(ENT : IN STD_LOGIC;
CLRN : IN STD_LOGIC;
CLK : IN STD_LOGIC;
ENP : IN STD_LOGIC;
LDN : IN STD_LOGIC;
RCO : OUT STD_LOGIC);
END COMPONENT;
ATTRIBUTE black_box OF \74163_3\: COMPONENT IS true; ATTRIBUTE noopt OF \74163_3\: COMPONENT IS true;
COMPONENT \74163_4\
PORT(ENT : IN STD_LOGIC;
CLRN : IN STD_LOGIC;
CLK : IN STD_LOGIC;
ENP : IN STD_LOGIC;
LDN : IN STD_LOGIC;
RCO : OUT STD_LOGIC);