函数信号发生器等vhdl程序

分频器：-- Copyright (C) 1991-2008 Altera Corporation-- Your use of Altera Corporation's design tools, logic functions-- and other software and tools, and its AMPP partner logic-- functions, and any output files from any of the foregoing-- (including device programming or simulation files), and any-- associated documentation or information are expressly subject-- to the terms and conditions of the Altera Program License-- Subscription Agreement, Altera MegaCore Function License-- Agreement, or other applicable license agreement, including,-- without limitation, that your use is for the sole purpose of-- programming logic devices manufactured by Altera and sold by-- Altera or its authorized distributors. Please refer to the-- applicable agreement for further details.-- PROGRAM "Quartus II"-- VERSION "Version 8.1 Build 163 10/28/2008 SJ Full Version" -- CREATED ON "Fri Sep 23 22:47:56 2011"LIBRARY ieee;USE ieee.std_logic_1164.all;LIBRARY work;ENTITY fenpin ISPORT(clk1 : IN STD_LOGIC;clk : OUT STD_LOGIC);END fenpin;ARCHITECTURE bdf_type OF fenpin ISATTRIBUTE black_box : BOOLEAN;nATTRIBUTE noopt : BOOLEAN;COMPONENT \74163_0\PORT(ENT : IN STD_LOGIC;CLRN : IN STD_LOGIC;CLK : IN STD_LOGIC;ENP : IN STD_LOGIC;LDN : IN STD_LOGIC;RCO : OUT STD_LOGIC);ATTRIBUTE black_box OF \74163_0\: COMPONENT IS true; ATTRIBUTE noopt OF \74163_0\: COMPONENT IS true;COMPONENT \74163_1\PORT(ENT : IN STD_LOGIC;CLRN : IN STD_LOGIC;CLK : IN STD_LOGIC;ENP : IN STD_LOGIC;LDN : IN STD_LOGIC;RCO : OUT STD_LOGIC);END COMPONENT;ATTRIBUTE black_box OF \74163_1\: COMPONENT IS true; ATTRIBUTE noopt OF \74163_1\: COMPONENT IS true;COMPONENT \74163_2\PORT(ENT : IN STD_LOGIC;CLRN : IN STD_LOGIC;CLK : IN STD_LOGIC;ENP : IN STD_LOGIC;LDN : IN STD_LOGIC;RCO : OUT STD_LOGIC);END COMPONENT;ATTRIBUTE black_box OF \74163_2\: COMPONENT IS true; ATTRIBUTE noopt OF \74163_2\: COMPONENT IS true;COMPONENT \74163_3\PORT(ENT : IN STD_LOGIC;CLRN : IN STD_LOGIC;CLK : IN STD_LOGIC;ENP : IN STD_LOGIC;LDN : IN STD_LOGIC;RCO : OUT STD_LOGIC);END COMPONENT;ATTRIBUTE black_box OF \74163_3\: COMPONENT IS true; ATTRIBUTE noopt OF \74163_3\: COMPONENT IS true;COMPONENT \74163_4\PORT(ENT : IN STD_LOGIC;CLRN : IN STD_LOGIC;CLK : IN STD_LOGIC;ENP : IN STD_LOGIC;LDN : IN STD_LOGIC;RCO : OUT STD_LOGIC);ATTRIBUTE black_box OF \74163_4\: COMPONENT IS true; ATTRIBUTE noopt OF \74163_4\: COMPONENT IS true;SIGNAL SYNTHESIZED_WIRE_24 : STD_LOGIC; SIGNAL SYNTHESIZED_WIRE_6 : STD_LOGIC; SIGNAL SYNTHESIZED_WIRE_11 : STD_LOGIC; SIGNAL SYNTHESIZED_WIRE_16 : STD_LOGIC; SIGNAL SYNTHESIZED_WIRE_21 : STD_LOGIC;BEGINSYNTHESIZED_WIRE_24 <= '1';b2v_inst : 74163_0PORT MAP(ENT => SYNTHESIZED_WIRE_24,CLRN => SYNTHESIZED_WIRE_24,CLK => clk1,ENP => SYNTHESIZED_WIRE_24,LDN => SYNTHESIZED_WIRE_24,RCO => SYNTHESIZED_WIRE_6);b2v_inst1 : 74163_1PORT MAP(ENT => SYNTHESIZED_WIRE_24,CLRN => SYNTHESIZED_WIRE_24,CLK => SYNTHESIZED_WIRE_6,ENP => SYNTHESIZED_WIRE_24,LDN => SYNTHESIZED_WIRE_24,RCO => SYNTHESIZED_WIRE_11);b2v_inst2 : 74163_2PORT MAP(ENT => SYNTHESIZED_WIRE_24,CLRN => SYNTHESIZED_WIRE_24,CLK => SYNTHESIZED_WIRE_11,ENP => SYNTHESIZED_WIRE_24,LDN => SYNTHESIZED_WIRE_24,RCO => SYNTHESIZED_WIRE_16);b2v_inst3 : 74163_3PORT MAP(ENT => SYNTHESIZED_WIRE_24,CLRN => SYNTHESIZED_WIRE_24,CLK => SYNTHESIZED_WIRE_16,ENP => SYNTHESIZED_WIRE_24,LDN => SYNTHESIZED_WIRE_24,RCO => SYNTHESIZED_WIRE_21);b2v_inst5 : 74163_4PORT MAP(ENT => SYNTHESIZED_WIRE_24,CLRN => SYNTHESIZED_WIRE_24,CLK => SYNTHESIZED_WIRE_21,ENP => SYNTHESIZED_WIRE_24,LDN => SYNTHESIZED_WIRE_24,RCO => clk);END bdf_type;序列信号发生器-LIBRARY ieee;USE ieee.std_logic_1164.all;LIBRARY work;ENTITY fashengqi ISPORT(pin_name : IN STD_LOGIC;xulie : OUT STD_LOGIC);END fashengqi;ARCHITECTURE bdf_type OF fashengqi ISATTRIBUTE black_box : BOOLEAN; nATTRIBUTE noopt : BOOLEAN;COMPONENT \74175_0\PORT(D1 : IN STD_LOGIC;D2 : IN STD_LOGIC;D3 : IN STD_LOGIC;D4 : IN STD_LOGIC;Q1 : OUT STD_LOGIC;QN1 : OUT STD_LOGIC;Q2 : OUT STD_LOGIC;QN2 : OUT STD_LOGIC;Q3 : OUT STD_LOGIC;QN3 : OUT STD_LOGIC;Q4 : OUT STD_LOGIC;QN4 : OUT STD_LOGIC);END COMPONENT;ATTRIBUTE black_box OF \74175_0\: COMPONENT IS true;ATTRIBUTE noopt OF \74175_0\: COMPONENT IS true;SIGNAL SYNTHESIZED_WIRE_15 : STD_LOGIC;SIGNAL SYNTHESIZED_WIRE_16 : STD_LOGIC;SIGNAL SYNTHESIZED_WIRE_2 : STD_LOGIC;SIGNAL SYNTHESIZED_WIRE_3 : STD_LOGIC;SIGNAL SYNTHESIZED_WIRE_4 : STD_LOGIC;SIGNAL SYNTHESIZED_WIRE_5 : STD_LOGIC;SIGNAL SYNTHESIZED_WIRE_7 : STD_LOGIC;SIGNAL SYNTHESIZED_WIRE_8 : STD_LOGIC;SIGNAL SYNTHESIZED_WIRE_9 : STD_LOGIC;SIGNAL SYNTHESIZED_WIRE_10 : STD_LOGIC;SIGNAL SYNTHESIZED_WIRE_11 : STD_LOGIC;SIGNAL SYNTHESIZED_WIRE_12 : STD_LOGIC;SIGNAL SYNTHESIZED_WIRE_13 : STD_LOGIC;BEGINxulie <= SYNTHESIZED_WIRE_3;SYNTHESIZED_WIRE_7 <= SYNTHESIZED_WIRE_15 AND SYNTHESIZED_WIRE_16; SYNTHESIZED_WIRE_9 <= SYNTHESIZED_WIRE_2 AND SYNTHESIZED_WIRE_3;SYNTHESIZED_WIRE_8 <= SYNTHESIZED_WIRE_4 AND SYNTHESIZED_WIRE_5 AND SYNTHESIZED_WIRE_16;SYNTHESIZED_WIRE_10 <= SYNTHESIZED_WIRE_7 OR SYNTHESIZED_WIRE_8;SYNTHESIZED_WIRE_11 <= SYNTHESIZED_WIRE_9 OR SYNTHESIZED_WIRE_10;b2v_inst8 : 74175_0PORT MAP(D1 => SYNTHESIZED_WIRE_11,D2 => SYNTHESIZED_WIRE_12,D3 => SYNTHESIZED_WIRE_13,D4 => SYNTHESIZED_WIRE_15,Q1 => SYNTHESIZED_WIRE_12,QN1 => SYNTHESIZED_WIRE_4,Q2 => SYNTHESIZED_WIRE_13,QN2 => SYNTHESIZED_WIRE_5,Q3 => SYNTHESIZED_WIRE_15,QN3 => SYNTHESIZED_WIRE_2,Q4 => SYNTHESIZED_WIRE_3,QN4 => SYNTHESIZED_WIRE_16);END bdf_type;串并转换：LIBRARY ieee;USE ieee.std_logic_1164.all;LIBRARY work;ENTITY chuanbingzhuanhuan ISPORT(pin_name2 : IN STD_LOGIC;a : OUT STD_LOGIC;b : OUT STD_LOGIC;c : OUT STD_LOGIC;d : OUT STD_LOGIC;e : OUT STD_LOGIC;f : OUT STD_LOGIC;g : OUT STD_LOGIC);END chuanbingzhuanhuan;ARCHITECTURE bdf_type OF chuanbingzhuanhuan ISATTRIBUTE black_box : BOOLEAN;nATTRIBUTE noopt : BOOLEAN;COMPONENT \74194_0\PORT(SRSI : IN STD_LOGIC;CLK : IN STD_LOGIC;CLRN : IN STD_LOGIC;S1 : IN STD_LOGIC;S0 : IN STD_LOGIC;QA : OUT STD_LOGIC;QB : OUT STD_LOGIC;QC : OUT STD_LOGIC;QD : OUT STD_LOGIC);END COMPONENT;ATTRIBUTE black_box OF \74194_0\: COMPONENT IS true; ATTRIBUTE noopt OF \74194_0\: COMPONENT IS true;COMPONENT \74194_1\PORT(SRSI : IN STD_LOGIC;CLK : IN STD_LOGIC;CLRN : IN STD_LOGIC;S1 : IN STD_LOGIC;S0 : IN STD_LOGIC;QA : OUT STD_LOGIC;QB : OUT STD_LOGIC;QC : OUT STD_LOGIC);END COMPONENT;ATTRIBUTE black_box OF \74194_1\: COMPONENT IS true; ATTRIBUTE noopt OF \74194_1\: COMPONENT IS true;COMPONENT fashengqiPORT(pin_name : IN STD_LOGIC;xulie : OUT STD_LOGIC);END COMPONENT;SIGNAL SYNTHESIZED_WIRE_0 : STD_LOGIC; SIGNAL SYNTHESIZED_WIRE_8 : STD_LOGIC; SIGNAL SYNTHESIZED_WIRE_9 : STD_LOGIC; SIGNAL SYNTHESIZED_WIRE_4 : STD_LOGIC;BEGINd <= SYNTHESIZED_WIRE_4; SYNTHESIZED_WIRE_8 <= '1'; SYNTHESIZED_WIRE_9 <= '0';b2v_inst : 74194_0PORT MAP(SRSI => SYNTHESIZED_WIRE_0,CLK => pin_name2,CLRN => SYNTHESIZED_WIRE_8,S1 => SYNTHESIZED_WIRE_9,S0 => SYNTHESIZED_WIRE_8,QA => g,QB => f,QC => e,QD => SYNTHESIZED_WIRE_4);b2v_inst1 : 74194_1PORT MAP(SRSI => SYNTHESIZED_WIRE_4,CLK => pin_name2,CLRN => SYNTHESIZED_WIRE_8,S1 => SYNTHESIZED_WIRE_9,S0 => SYNTHESIZED_WIRE_8,QA => c,QB => b,QC => a);b2v_inst2 : fashengqiPORT MAP(pin_name => pin_name2,xulie => SYNTHESIZED_WIRE_0); END bdf_type;串行检测：LIBRARY ieee;USE ieee.std_logic_1164.all;LIBRARY work;ENTITY chuanxingjiance ISPORT(b : IN STD_LOGIC;c : IN STD_LOGIC;a : OUT STD_LOGIC);END chuanxingjiance;ARCHITECTURE bdf_type OF chuanxingjiance IS BEGINa <=b OR c;END bdf_type;并行检测：LIBRARY ieee;USE ieee.std_logic_1164.all;LIBRARY work;ENTITY bingxingjiance ISPORT(pin_name : IN STD_LOGIC;tongbu : OUT STD_LOGIC);END bingxingjiance;ARCHITECTURE bdf_type OF bingxingjiance ISATTRIBUTE black_box : BOOLEAN; nATTRIBUTE noopt : BOOLEAN;COMPONENT \7485_0\PORT(A3 : IN STD_LOGIC;B2 : IN STD_LOGIC;A2 : IN STD_LOGIC;AEBI : IN STD_LOGIC;AGBI : IN STD_LOGIC;ALBI : IN STD_LOGIC;A0 : IN STD_LOGIC;B0 : IN STD_LOGIC;B3 : IN STD_LOGIC;A1 : IN STD_LOGIC;B1 : IN STD_LOGIC;AEBO : OUT STD_LOGIC);END COMPONENT;ATTRIBUTE black_box OF \7485_0\: COMPONENT IS true; ATTRIBUTE noopt OF \7485_0\: COMPONENT IS true;COMPONENT \7485_1\PORT(A3 : IN STD_LOGIC;B2 : IN STD_LOGIC;A2 : IN STD_LOGIC;AEBI : IN STD_LOGIC;AGBI : IN STD_LOGIC;ALBI : IN STD_LOGIC;A0 : IN STD_LOGIC;B0 : IN STD_LOGIC;B3 : IN STD_LOGIC;A1 : IN STD_LOGIC;B1 : IN STD_LOGIC;ALBO : OUT STD_LOGIC;AGBO : OUT STD_LOGIC;AEBO : OUT STD_LOGIC);END COMPONENT;ATTRIBUTE black_box OF \7485_1\: COMPONENT IS true; ATTRIBUTE noopt OF \7485_1\: COMPONENT IS true;COMPONENT chuanbingzhuanhuanPORT(pin_name2 : IN STD_LOGIC;g : OUT STD_LOGIC;f : OUT STD_LOGIC;e : OUT STD_LOGIC;d : OUT STD_LOGIC;c : OUT STD_LOGIC;b : OUT STD_LOGIC;a : OUT STD_LOGIC);END COMPONENT;SIGNAL SYNTHESIZED_WIRE_0 : STD_LOGIC; SIGNAL SYNTHESIZED_WIRE_22 : STD_LOGIC; SIGNAL SYNTHESIZED_WIRE_2 : STD_LOGIC; SIGNAL SYNTHESIZED_WIRE_3 : STD_LOGIC; SIGNAL SYNTHESIZED_WIRE_4 : STD_LOGIC; SIGNAL SYNTHESIZED_WIRE_5 : STD_LOGIC; SIGNAL SYNTHESIZED_WIRE_6 : STD_LOGIC; SIGNAL SYNTHESIZED_WIRE_23 : STD_LOGIC; SIGNAL SYNTHESIZED_WIRE_9 : STD_LOGIC; SIGNAL SYNTHESIZED_WIRE_13 : STD_LOGIC; SIGNAL SYNTHESIZED_WIRE_17 : STD_LOGIC; SIGNAL SYNTHESIZED_WIRE_20 : STD_LOGIC;BEGINSYNTHESIZED_WIRE_22 <= '0'; SYNTHESIZED_WIRE_23 <= '1';b2v_inst : 7485_0PORT MAP(A3 => SYNTHESIZED_WIRE_0,B2 => SYNTHESIZED_WIRE_22,A2 => SYNTHESIZED_WIRE_2,AEBI => SYNTHESIZED_WIRE_3,AGBI => SYNTHESIZED_WIRE_4,ALBI => SYNTHESIZED_WIRE_5,A0 => SYNTHESIZED_WIRE_6,B0 => SYNTHESIZED_WIRE_22,B3 => SYNTHESIZED_WIRE_23,A1 => SYNTHESIZED_WIRE_9,B1 => SYNTHESIZED_WIRE_22,AEBO => tongbu);b2v_inst1 : 7485_1PORT MAP(A3 => SYNTHESIZED_WIRE_22,B2 => SYNTHESIZED_WIRE_23,A2 => SYNTHESIZED_WIRE_13,AEBI => SYNTHESIZED_WIRE_23,AGBI => SYNTHESIZED_WIRE_22,ALBI => SYNTHESIZED_WIRE_22,A0 => SYNTHESIZED_WIRE_17,B0 => SYNTHESIZED_WIRE_23,B3 => SYNTHESIZED_WIRE_22,A1 => SYNTHESIZED_WIRE_20,B1 => SYNTHESIZED_WIRE_23,ALBO => SYNTHESIZED_WIRE_5,AGBO => SYNTHESIZED_WIRE_4,AEBO => SYNTHESIZED_WIRE_3);b2v_inst3 : chuanbingzhuanhuanPORT MAP(pin_name2 => pin_name,g => SYNTHESIZED_WIRE_6,f => SYNTHESIZED_WIRE_9,e => SYNTHESIZED_WIRE_2,d => SYNTHESIZED_WIRE_0,c => SYNTHESIZED_WIRE_17,b => SYNTHESIZED_WIRE_20,a => SYNTHESIZED_WIRE_13);END bdf_type;控制电路：LIBRARY ieee;USE ieee.std_logic_1164.all;LIBRARY work;ENTITY kongzhi ISPORT(PRN1 : IN STD_LOGIC;D1 : IN STD_LOGIC;CLK1 : IN STD_LOGIC;CLRN1 : IN STD_LOGIC;PRN2 : IN STD_LOGIC;D2 : IN STD_LOGIC;CLK2 : IN STD_LOGIC;CLRN2 : IN STD_LOGIC;Q2 : OUT STD_LOGIC;QN2 : OUT STD_LOGIC;Q1 : OUT STD_LOGIC;QN1 : OUT STD_LOGIC);END kongzhi;ARCHITECTURE bdf_type OF kongzhi ISSIGNAL DFF_10 : STD_LOGIC; SIGNAL DFF_9 : STD_LOGIC;BEGINQ2 <= DFF_10;Q1 <= DFF_9;PROCESS(CLK2,CLRN2,PRN2)BEGINIF (CLRN2 <= '0') THENDFF_10 <= '0';ELSIF (PRN2 = '0') THENDFF_10 <= '1';ELSIF (RISING_EDGE(CLK2)) THENDFF_10 <= D2;END IF;END PROCESS;QN2 <= NOT(DFF_10);QN1 <= NOT(DFF_9);PROCESS(CLK1,CLRN1,PRN1)BEGINIF (CLRN1 <= '0') THENDFF_9 <= '0';ELSIF (PRN1 = '0') THENDFF_9 <= '1';ELSIF (RISING_EDGE(CLK1)) THENDFF_9 <= D1;END IF;END PROCESS;END bdf_type;锁存器：LIBRARY ieee;USE ieee.std_logic_1164.all; LIBRARY work;ENTITY suocun ISPORT(clk : IN STD_LOGIC;d : OUT STD_LOGIC;a : OUT STD_LOGIC;b : OUT STD_LOGIC;c : OUT STD_LOGIC;e : OUT STD_LOGIC;f : OUT STD_LOGIC;g : OUT STD_LOGIC);END suocun;ARCHITECTURE bdf_type OF suocun ISATTRIBUTE black_box : BOOLEAN; nATTRIBUTE noopt : BOOLEAN;COMPONENT \74273_0\PORT(D2 : IN STD_LOGIC;D3 : IN STD_LOGIC;D1 : IN STD_LOGIC;D4 : IN STD_LOGIC;D7 : IN STD_LOGIC;D6 : IN STD_LOGIC;D5 : IN STD_LOGIC;CLK : IN STD_LOGIC;CLRN : IN STD_LOGIC;Q4 : OUT STD_LOGIC;Q1 : OUT STD_LOGIC;Q2 : OUT STD_LOGIC;Q3 : OUT STD_LOGIC;Q6 : OUT STD_LOGIC;Q5 : OUT STD_LOGIC;Q7 : OUT STD_LOGIC);END COMPONENT;ATTRIBUTE black_box OF \74273_0\: COMPONENT IS true; ATTRIBUTE noopt OF \74273_0\: COMPONENT IS true;COMPONENT chuanbingzhuanhuanPORT(pin_name2 : IN STD_LOGIC;g : OUT STD_LOGIC;f : OUT STD_LOGIC;e : OUT STD_LOGIC;d : OUT STD_LOGIC;c : OUT STD_LOGIC;b : OUT STD_LOGIC;a : OUT STD_LOGIC);END COMPONENT;COMPONENT kongzhiPORT(clk : IN STD_LOGIC;kongzhi : OUT STD_LOGIC);END COMPONENT;SIGNAL SYNTHESIZED_WIRE_0 : STD_LOGIC; SIGNAL SYNTHESIZED_WIRE_1 : STD_LOGIC; SIGNAL SYNTHESIZED_WIRE_2 : STD_LOGIC; SIGNAL SYNTHESIZED_WIRE_3 : STD_LOGIC; SIGNAL SYNTHESIZED_WIRE_4 : STD_LOGIC; SIGNAL SYNTHESIZED_WIRE_5 : STD_LOGIC; SIGNAL SYNTHESIZED_WIRE_6 : STD_LOGIC; SIGNAL SYNTHESIZED_WIRE_7 : STD_LOGIC; SIGNAL SYNTHESIZED_WIRE_8 : STD_LOGIC;BEGINSYNTHESIZED_WIRE_8 <= '1';b2v_inst : 74273_0PORT MAP(D2 => SYNTHESIZED_WIRE_0,D3 => SYNTHESIZED_WIRE_1,D1 => SYNTHESIZED_WIRE_2,D4 => SYNTHESIZED_WIRE_3,D7 => SYNTHESIZED_WIRE_4,D6 => SYNTHESIZED_WIRE_5,D5 => SYNTHESIZED_WIRE_6,CLK => SYNTHESIZED_WIRE_7,CLRN => SYNTHESIZED_WIRE_8,Q4 => d,Q1 => g,Q2 => f,Q3 => e,Q6 => b,Q5 => c,Q7 => a);b2v_inst1 : chuanbingzhuanhuanPORT MAP(pin_name2 => clk,g => SYNTHESIZED_WIRE_2,f => SYNTHESIZED_WIRE_0,e => SYNTHESIZED_WIRE_1,d => SYNTHESIZED_WIRE_3,c => SYNTHESIZED_WIRE_6,b => SYNTHESIZED_WIRE_5,a => SYNTHESIZED_WIRE_4);b2v_inst2 : kongzhiPORT MAP(clk => clk,kongzhi => SYNTHESIZED_WIRE_7); END bdf_type;。