mips汇编

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XVECENT宏中的分支延迟槽执行数据加载，但是由于数据加载延迟，不能在f（romExcHandle）的第一条指令中访问k0参数，或者在li后添加一条nop指令。
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1.5.2 编址及内存访问
跳转指令(j)：有限的32位指令长度对于大型程序的分支跳转支持确实是个难题。MIPS指令中最小的操作码域占6位，剩下的26位用于跳转目标的编址。由于所有指令在内存中都是4字节对齐的，因此最低的2个地址位是无需存储的，这样可供寻址范围为2^28=256MB。分支跳转地址被当做一个256MB的段内绝对地址，而非PC相对寻址。这对于地址范围超过256MB的跳转程序而言是无能为力的，所幸目前很少遇到这么大的远程跳转需求。
1.5.4 Programmer-Visible Pipeline Effects
Delayed branches: The pipeline structure of the MIPS CPU (Figure 1.3) means that when a jump/branch instruction reaches the execute phase and a new program counter is generated,the instruction after the jump will already have been started. Rather than discard this potentially useful work, the architecture dictates that the instruction after a branch must always be executed before the instruction at the target of the branch. The instruction position following any branch is called the branch delay slot.
1.5.4 程序员可见的流水线效果
延迟分支：MIPS CPU的流水线结构（见图1-3）意味着，当跳转/分支指令到达执行阶段并且新的程序计数器已经产生时，紧随其后的下一条指令已经开始执行了。MIPS体系架构并没有抛弃这部分潜在的有用工作，而是规定分支之后的指令总是在分支目标指令之前执行。紧随分支指令之后的位置称为分支延迟槽。
对条件分支来说需要很小心，分支延迟指令必须对（至少）两条路径都不会产生不良影响。在没有任何可用操作时，延迟槽将填充空指令（nop）。
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数据加载延迟（加载延迟槽）：流水线的另一后果是数据加载指令的数据在下一条指令的ALU阶段启动之后才能从缓存或内存系统中取得，于是下一条指令便不能使用该数据。图1-4显示了此工作原理。
(2) A subroutine call is “jump and link” or“branch and link” and the mne-monics end . . .al.
8.7.8 Jumps, Subroutine Calls, and Branches
The MIPS architecture follows Motorola nomenclature for these instructions, as follows:
(1) PC-relative instructions are called“branch” and absolute-addressed instructions “jump”; the operation mnemonics begin with b orj.
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It is the responsibility of the compiler system or the assembly programming wizard to allowfor and even to exploit the branchdelay; it turns out that it is usually possible toarrange that the instruction in the branch delay slot does useful work. Quite often,the instruction that would otherwise have beenplaced before the branch can be moved into the delay slot.
Onmodern MIPS CPUs the load result is interlocked:If you try to use the result too early, the CPU stops until the data arrives. But on early MIPS CPUs, there were no interlocks, and the attempt to use data in the load delay slot led to unpredictable results.
紧跟在加载指令后的指令位置叫做加载延迟槽，优化的编译器可以用延迟槽来做一些有用的工作。这一特性对程序员是透明的，很多时候汇编器向该延迟槽填入一个空操作指令（nop）。
在现代MIPS CPU中加载结果会导致互锁：如果你想过早使用该数据，CPU就会停下来直到该数据到达。但早期的MIPSCPU中没有互锁硬件，任何企图提前使用加载延迟槽中的数据的操作都将导致无法预料的结果。
.5cesses
Jump instructions: The limited 32-bit instruction length is a particular problem for branches in anarchitecture that wants to support very large programs. The smallest opcode field in a MIPS instruction is 6 bits, leaving 26 bits to define the target of a jump. Since all instructions are four-byte aligned in memory,the two least significant address bits need not be stored,allowing an address range of 2^28= 256 MB. Rather than make this branch PC relative, this is interpreted as an absolute address within a 256MB segment. That’s inconvenient for single programs larger than this, although it hasn't been much of a problem yet!
This can be a bit tricky on a conditional branch, where the branch delay instructionmust be (at least)harmless on bothpaths. Where nothing useful can be done, the delay slot isfilled with a nopinstruction.
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Late Data from load(load delay slot): Another consequence of the pipeline is that a load instruction’s data arrives from the cache/memory system after the next instruction’s ALU phase starts—so it is not possible to use the data from a load in the following instruction. (See Figure 1.4 for how this works.)
例如《VxWorks BSP for AMD's AU1500(MIPS)》的V100R001CPE\romMipsInit.s中定义ROM异常入口点时，XVECENT宏中利用分支延迟槽传参。
#define XVECENT(f,bev) b f; li k0,bev
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编译器或汇编程序可以考虑充分利用分支延迟，比如在延迟槽中填充有用的指令，把原来放在分支指令之前的指令移动到延迟槽中。
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Theinstruction position immediately after the load is called the load Delay Slot, and an optimizingcompiler will try to do something useful with it. The assembler will hide this from you but may end upputting in a nop.