DXP规则报错,PCB制板元件管脚电气特性介绍

Dxp规则报错及解决方法

1.[Short-Circuit Constraint Violation]

详细：Advanced PCB stm32.PcbDoc Short-Circuit Constraint: Between Via (73.3044mm,64.9224mm) Top Layer to Bottom Layer And Track (73.3044mm,64.9224mm)(73.32061mm,64.90619mm) Top Layer 16:41:48 2013/4/16 497 原因：过孔没有标明网络

解决：上下两层短路，注意一下过孔有无错误

2.[Silkscreen Over Component Pads Constraint Violation]

详细：Advanced PCB stm32.PcbDoc Silkscreen Over Component Pads Constraint: Between Track (84.85998mm,42.58mm)(84.85998mm,43.78mm) Top Overlay And Pad C23-1(85.36mm,43.18mm) Top Layer [Top Overlay] to [Top Solder] clearance [0.02503mm]

原因：丝印层与焊盘的距离问题

解决：在网上查资料后，发现，将规则（Rules...）里面的Manufacturing某个参数改一下就可以避免这种绿色警告，分享如下。首先，design-->rules...-->左边若干选项中有一个Manufacturing，子选项Silkscreen over Component Pads

3.[Minimum Solder Mask Sliver Constraint Violation]

详细：Advanced PCB stm32.PcbDoc Minimum Solder Mask Sliver Constraint: Between Pad *1-16(76.68859mm,74.71903mm) Multi-Layer And Pad U1-48(75.89561mm,73.37141mm) Top Layer [Top Solder] Mask Sliver [0.24442mm] 17:20:01 2013/4/16 100

原因：焊盘间的最小间距问题

解决：首先，design-->rules...-->左边若干选项中有一个Manufacturing，子选项minimum solder mask sliver，原来的constraints选框内显示的clearance将间距改为0之后绿色警告消失。

4.[Un-Routed Net Constraint Violation]

详细：Advanced PCB stm32.PcbDoc Un-Routed Net Constraint: Between Track (73.3472mm,83.812mm)(76.89332mm,83.812mm) Top Layer And Pad *1-6(73.6886mm,89.719mm) Bottom Layer 17:23:03 2013/4/16 359

原因：存在没有连或没有连好的线

解决：根据提示找到该线补连

5.[Clearance Constraint Violation]

详细：stm32.PcbDoc Advanced PCB Clearance Constraint: Between Via (73.32061mm,64.90619mm) Top Layer to Bottom Layer And Polygon Arc (73.3044mm,64.9224mm) Top Layer 18:53:43 2013/4/17 1

原因：不同网络的最小间隔问题

解决：首先，design-->rules...-->左边若干选项中有一个Electrical，子选项clearance，原来的Different Nets Only最小清除改为0.1之后警告消失。

6.[Clearance Constraint Violation]

详细：stm32.PcbDoc Advanced PCB Clearance Constraint: Between Pad

KEY1-1(59.2582mm,26.4668mm) Multi-Layer And Track

(28.067mm,25.4mm)(100.0252mm,25.4mm) Keep-Out Layer

原因：multi-layer超出了keep-out layer层的范围了

解决：调整multi-layer和keep-out layer层之间的位置关系

7.[Room Definition Violation]

详细：PCB1.PcbDoc Advanced PCB Between Component R2(5380mil,4260mil) Top Laye r and Room Sheet1 (Bounding Region = (7005mil, 3095mil, 8871.423mil, 3552.874mil) (I nComponentClass('Sheet1')) 10:46:48 AM 2008-5-24 97

原因：room定义错误

解决：把原来原理图带过的图纸边框删掉

元件引脚电气类型作用

为了对原理图设计进行可靠的电气法则检查，在创建元件的时候应该注意其各个引脚的电气特性

引脚可供设置的电气特性有以下八种：

INPUT 输入型。作为输入引脚使用

IO 双向型。既可作为输入，又可作为输出引脚。

OUTPUT 输出型。作为输出引脚使用

OPENCOLLECTOR 集电极开路的引脚

PASSIVE 无源型。该引脚为无源引脚