MIPIDSIEssentialMIPI协议详细介绍演示幻灯片

500Mbps/Lane, differential signaling 10Mbps, single ended signaling, lane 0 only
? Lane-Scalable, up to 4 data lanes
? Packet Based Data Transmission
– DSI Protocol has ECC, CRC capability -
TX: Distribute data to 1, 2, 3 or 4 lanes RX: Assembly data from 1, 2, 3 or 4 to one
byte stream
Physical Transmission / Reception Serializer / Deserializer
Display Refresh
Bus Interface
Display Driver
LCD Display
6
Command Mode Display
Host Processor
Image Update
Data
Bus Interface
Commands & Image Update
Data
Display Panel
containing DSI Transmitter
DSI Transmitter DataN+ DataN-
Bi-directional High Speed Data Links
Data0+ Data0-
N Data Lanes where N may be
1, 2, 3, or 4
Peripheral, e.g. a Display containing the DSI receiver
DSI Receiver DataN+ DataN-
Data0+ Data0-
Clock+ Clock-
Clock+ Clock-
4
MIPI DSI Functional Layers
Transmitter SFra bibliotekdeApplication
Pixel
Control
Pixel
Control
Pixel to Byte Packing Formats
? Serial Interface
– Low Pin Count – Reduced Power Consumption
? 2 Types of Data Signaling
– High Speed Data Transmission – Low Power Data Transmission -
Bus Interface
Color Frame Buffer
Display Controller
LCD Display
Receiver Side
Application
Control
Pixel
Control
Pixel
Byte to Pixel Unpacking Formats
Control
Data
8-bits
Control
Data
Low Level Protocol
Control
Data
8-bits
Lane Management Layer
16-, 18- or 24-bit Pixels
Pack / Unpack Pixels or Commands from / to Byte Stream
Add (TX) / Extract (RX) low level protocol, synchronization, ECC, CRC packet headers and footers.
MIPI DSI Essential
Table of Contents
? MIPI DSI Overview
? PHY Layer
– D-PHY Architecture – Global Operation
? Lane Management Layer
? DSI Protocol Layer
2
MIPI DSI Overview
Byte Clock Generation / Recovery (DDR) per MIPI D-PHY Spec
High Speed Unidirectional Clock Lane 0 -High Speed bidirectional Data Lane 1 -High Speed Unidirectional Data Lane 2 -High Speed Unidirectional Data Lane 3 -High Speed Unidirectional Data
N * 8-bits
Control Data0 Data1 Data3 Data3
PHY Layer
5
Video Mode Display
Host Processor
Timing Control
Bus Interface
Update Frame Buffer
Color Frame Buffer
Display Panel
robust data transmission
– Protocol Support Multiple displays (up to 4)
? Support All Legacy Parallel Interface
MIPI DSI Interface Physical Architecture
■ 1 Clock Lane, unidirectional ■ 1 to 4 Data Lanes ■ Lane0 is bidirectional for LP data output transmission of the driver IC
Host Device, e.g. an Application Processor or Baseband Processor
Data
Control
8-bits
Data
Control
Low Level Protocol
Data
Control
8-bits
Lane Management Layer
N * 8-bits
Data3 Data2 Data1 Data0 Control
PHY Layer
Encode and Interpretat Data / Commands