2010级硕士模拟集成电路分析与设计期末复习题-解答

2010级研究生《模拟集成电路分析与设计》复习自己的解答一、Questions ：1．What is the problem of simple differential circuit? How to solve this problem?Answer: If V in, CM is low output will be clipped. Solve method: use differential pair.2．Describe advantages and drawbacks of differential signals comparing with single-ended signal. Answer: Advantages: Higher immunity to environment noise(对环境噪声更具抗干扰能力); Reduce coupled noise in transmission line(减少相邻信号线传输时受的干扰); Reject supply noise; Increase output voltage swing;Simpler biasing;Higher linearityDrawbacks: occupy twice areas3. Why analog design needed in Optical Receivers?Answer: High frequency signals are not suitable for transmitting over long distance in the traditional cable due to the severe interference and considerable attenuation because of the limited bandwidth of the cable. In this case, the electrical high frequency signals are converted into the optical signals first by the laser diode, then these optic signals are transmitted by an optical fiber, which has extremely wide band and very low loss. In the other end, the optical signals are converted into electrical signals again by the photodiode.书(中)P3；（英）P4 4. Which two figures play most important role in technology nodes scaling down? Please describe in detail.Answer: Minimum channel length often represents the technology nodes. Oxide thickness often affects the threshold voltage and the power supply.5. If there is a small mismatch between M1 and M2, how do the parameters of the transistorsaffect the common mode rejection ratio (CMRR) of a differential pair?(中)P1016. Write the input pole of the circuit in Fig. 1.Answer: The input pole: ωin =1/[R S (1+A)C F ]7. When both NMOS and PMOS devices are needed to be placed on one chip, what is needed? Answer: N-Well or P-Well is needed.8. What is the problem for the circuit in Fig. 2? Any suggestions to solve it?Answer: Small-signal drain current of M1 is “wasted”. Solve method: Use differential pair with active current mirror to combine the small-signal current together.)arg ()21(242121e l too not is mismatch if R g g g g R g g g g A A CMRR SS m mmmSSm m m m DMCM DM DM +∆≈∆++==--9. Among the output noise and the input-referred noise, which one is more popular to be used inthe circuit simulation? Why?Answer: Since the output noise depends on the gain, it is hard to fairly compare the effects of noise of different circuits because of the different gain. Therefore, the input-referred noise is more popular to be used in the circuit simulation.10. Refer to Fig. 3, what benefits do we have for using cascode structure in current source? And any drawbacks?Answer: Advantages: Largely reduce the change so that V Y is more close to V X , and hence I out more closely track I REF.Drawbacks: Cost higher voltage headroom.11. Can we use the statistical value of noise amplititude ? If the answer is no, then what weusually use when considering the noise in circuit systems? Explain the reason.Answer: No. Because the statistical value of noise amplitude over time domain is zero. Fortunately the statistical value of power overall time domain is not zero. So we usually incorporate average power of a random signal in circuit analysis. 12. Explain why use diode-connected for M1 in Fig. 4 Answer: Diode-connected to ensure M1 always in saturation.13. Describe the steps for calculating the loop gain of a feedback system. And calculate LG in Fig. 5 following the steps.Answer: Step 1: Set the main input to zero; Step 2: Break the loop at some point;Step 3: Inject a test signal in the “right direction”;Step 4: Follow the signal around the loop;Fig.1Fig. 3Fig. 2)(0=⎰∞dt t xStep 5: Obtain the value that returns to the break point;Step 6: The negative of the transfer function derived is the loop gain;14. What is CMRR? Write down the definition of it. Answer: Common mode rejection ratio (共模抑制比）:Where gm denotes the mean value: gm=(gm1+gm2)/215. Write the input and output pole of the circuit in Fig. 6, ignoring the effect of C Gs and R S on C out . Answer: Low frequency gain:Using Miller’ Theorem:Therefore, the input pole is:If not consider the effect of R s and C GS on C out , Using Miller’ Theorem again:The output pole can be written as:16. Plot a diagram of a simple PLL and explain the working principle of it in short.Answer:Phase detector (PD) compares the phases of V out and Vin, generating an error signal; Low-pass filter (LPF) transfer the error wave to a dc level to the oscillator; The dc level can control the output frequency by VCO;In this way, the frequency and phase of V out can be locked to Vin.17. What is Power spectral density (PSD)? Use the expression and the plot to show it.Answer:（书）表示在每个频率上信号具有的功率大小。