计算机结构与逻辑设计

7-2 Edge-Triggered Flip-Flops
Q J Q CLK Q
S
Q
R
Q
Assuming that the Q output is High (Q=1)
if S 0, R 1
Q?
Q R Q 11 0
Q?
Q SQ 00 1
SET operation Assuming that the Q output is 0
if S 0, R 1
Q?
Q R Q 1 0 1
Q S Q 11 0
Q?
Q RQ 00 1
Q?
Q S Q 11 0
7-1 Latches
S
Q
R
Q
Assuming that the Q output is High (Q=1)
if S 0, R 0
Q?
Q RQ 011
Q?
Invalid condition
Assuming that the Q output is 0
The edge-triggered D flip-flop
Given the waveforms
Q
7-2 Edge-Triggered Flip-Flops
Delay of D Flip-Flops
The rising-edge of CLK has passed for Q2
The rising-edge of CLK has passed for Q3
Latches, Flip-Flops, and Timers
Zhou Ping School of Biological Science & Medical Engineering
7-1 Latches
The latch is a type of temporary storage device that has two stable states (bi-stable).
The gated S-R latch : an enable input, EN was applied.
S Q
EN Q
R
7-1 Latches
The gated D Latch
D latch differs from the S-R latch because it has only one input in addition to EN which is called the D (data) input.
＆ D
≥1 S
1
R
＆
C
S D, R D
Q ≥1
D EN
S D
EN
R
C 0 1 1
Q
Q
D
X
0
0
1
1
7-1 Latches
Race
hold
transparent
7-1 Latches
Master-slave
Qm
D
Q
1D
1D
C1
C1
CP
1
sample output sample output
7-2 Edge-Triggered Flip-Flops
7-2 Edge-Triggered Flip-Flops
7-2 Edge-Triggered Flip-Flops
A method of edge-triggered
A F
The edge-triggered D flip-flop
F A A
7-2 Edge-Triggered Flip-Flops
Q?
Q S Q 011
7-1 Latches
S
Q
R
Q
Assuming that the Q output is High (Q=1)
if S 1, R 0
Q?
Q RQ 011
Q?
RESET operation
Assuming that the Q output is 0
if S 1, R 0
7-2 Edge-Triggered Flip-Flops
The edge-triggered J-K Flip-Flop The difference is that the J-K FF has no invalid state as does the S-R FF.
Q J Q CLK Q
The S-R (or R-S) Latch
S→ Set (Q=1)
R → Reset (Q=0)
S
Q
S
Q
R
Q
Active-High input S-R latch
R
Q
Active-Low input S R latch
7-1 Latches
S
Q
R
Q
Assuming that the Q output is High (Q=1)
if S 1, R 1
Q?
Q R Q 11 0
Q?
No-change condition Assuming that the Q output is 0
if S 1, R 1
Q S Q 1 0 1
Q?
Q R Q 1 0 1
Q?
Q S Q 11 0
7-1 Latches
Flip-flops are synchronous bistable devices.
An edge-triggered flip-flop changes state either at the positive edge (rising edge ) or at the negative edge (falling edge) of the clock pulse and is sensitive to its inputs only at this transition of the clock.
if S 0, R 0
Q S Q 011
Q?
Q RQ 00 1
Q?
Q S Q 011
7-1 Latches
Logic symbols
S
Q
R
Q
SLeabharlann Baidu
Q
R
Q
Active-High input S-R latch Active-Low input S R latch
7-1 Latches
?
7-1 Latches
Application : the latch as a contact-bounce eliminator
7-1 Latches
Application : storage and transmission of information
＆
SQ
RQ
＆
TR
SQ RQ
7-1 Latches