计算机组织与结构复习题答案

read ---> Memory
t4: (MBR) -> IR
t3: Memory ---> MBR
(PC) +1 -> PC
t4: (MBR) -> PC
(Note: SP always points an empty location as top of stack.)
5’. CALL X;
Fetch cycle
t4: (MBR) -> IR
t4: (AX)+(MBR) ->AX
(PC) +1 -> PC 4. JZ NEXT1; —If (ZF)=0,then jump to (PC)+ NEXT1.
Fetch cycle
Execute cycle
t1: (PC) -> MAR
t1: if(ZF) =0
t2: (MAR) ---> Memory
t4: (MBR) -> PC
(PC) +1 -> PC
(SP) +1 -> SP
(Note: SP always points a full location as top of stack.)
7. STORE X; —Store the content of AC to location X .
(1)Show the mapping format; (2)Where is the cache is the data from memory location FDB9753 H ?(when read from memory) (3)Where is the memory is the data from cache set number 09D H and tag value 1357 H ?(when write to memory)
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2.Consider a memory system cache size is 64K words,main memory size is 4G words,which contain 512M blocks.If to adapt 4-way set associative mapping,what is address format?Which set is mapped to the memory location ABCDEF8F H?
Execute cycle
t1: (PC) -> MAR
t1: (PC) -> MBR
t2: (MAR) ---> Memory
(SP) -1 -> SP
read ---> Memory
(SP) -1 -> MAR
t3: Memory ---> MBR
t2: (MBR) ---> Memory
t4: (MBR) -> IR
(MAR) ---> Memory
(PC) +1 -> PC
write ---> Memory
t3: Ad(IR) ---> PC
(Note: SP always points a full location as top of stack.)
6’. RETURN;
Fetch cycle
Execute cycle
Fetch cycle
Indirect cycle
Execute cycle
t1: (PC) -> MAR
t1: Ad(MBR) -> MAR
t1: (MBR) -> MAR
t2: (MAR) ---> Memory t2: (MAR) -> Memory
t2: (MAR) -> Memory
read ---> Memory
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8. PUSH AX; —Store the content of AX to the top of stack 9. POP AX; —load AX from the top of stack 注意：给出一种合理的顺序即可，微操作还会涉及优化问题，不考虑了。
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计算机组织与结构答案
题型 1 中断处理过程 Interrupt Processing CHAPTER 07
Fetch cycle
Execute cycle
t1: (PC) -> MAR
t1: (BX) -> MAR
t2: (MAR) ---> Memory
t2: (MAR) -> Memory
read ---> Memory
read ->Memory
t3: Memory ---> MBR
t3: Memory-> MBR
read ->Memory
read ->Memory
t3: Memory ---> MBR
t3: Memory-> MBR
t3: Memory-> MBR
t4: (MBR) -> IR
t4:(MBR) -> AX
(PC) +1 -> PC
3. ADD AX, [BX]; —Operand pointed by the content of Register BX is added to AX, that means (AX)+((BX))->AX —[ ] means register indire MAR
t1: (SP) ->MAR
t2: (MAR) ---> Memory
t2: (MAR) --> Memory
read ---> Memory
read ---> Memory
t3: Memory ---> MBR
t3: Memory ---> MBR
t4: (MBR) -> IR
Please write out the steps which processor do when interrupt occurs ? (Describe simply all steps of the Interruption ? ) Answer: 0.The CPU does something else. 1. I/O module issues an interrupt signal to CPU. 2. The CPU finishes execution of the current instruction before responding to the interrupt. 3. The CPU tests & makes sure of an interrupt , and sends an ACK to I/O module. 4. The CPU saves important message(PSW&PC) of current program to stack for resuming. 5. The CPU loads new PC based on interrupt. 6. The CPU saves the remainder of current program onto stack. 7. The CPU process interrupt. 8. The restore CPU remainder from stack. 9. The CPU restore old PSW and PC from stack. 10.The CPU resumes interrupted something else.
计算机组织与结构总结
题型 1 中断处理过程 Interrupt Processing CHAPTER 07
Please write out the steps which processor do when interrupt occurs ? (Describe simply all steps of the Interruption ? ) Answer:
t4: (MBR) -> IR
t4: (AX)+(MBR) ->AX
(PC) +1 -> PC
2. MOV AX, [X]; —Operand pointed by the content of location X is moved to AX, that means ((X))->AX —[ ] means indirect addressing.
Initial
snoopy
Read hit 读命中
I
S
I
S
M
E
M
The states in begin
Initial
snoopy
Iniatial Actions
E
Snoopy
The states in end
Initial
snoopy
6
Write miss 写未命中
I
S
I
S
M
E
M
The states in begin
t4: (MBR) -> IR
write ---> Memory
(PC) +1 -> PC
t3: Ad (IR) -> PC
(SP) -1 -> SP
(Note: SP always points an empty location as top of stack.)
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6. RETURN; —From top of stack return to PC.
; ; ; ; ; ; ; ; ; ; ;
1
题型 2 海明码 Hamming Code CHAPTER 05
1.For the 8-bit data 10110101 would be stored in memory.Suppose the data is just read from Main Memory and calculated(计算) check bit is 1101,please use the Hamming algorithm to answer.
1.What is old check bit? 2.What is new check bit? 3.What is the data read from memory ?
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2.Suppose the code 1001 0111 0101 is just read from memory,please use the Hamming algorithm to determine what is right data bits(the valid 8-bit data).
Fetch cycle
Execute cycle
t1: (PC) -> MAR t2: (MAR) ---> Memory
t1: (SP) +1 -> SP (SP) +1 ->MAR
（提示：把加后结果同时存）
read ---> Memory
t2: (MAR)---> Memory
t3: Memory ---> MBR
3
题型 3 高速缓冲寄存器--组关联映射 Cache--Set Associative Mapping CHAPTER 04 1.A four-way set associative cache has 64K words,main memory has 256M words and 8 words in each block.
then (PC)+(NEXT1) ->PC
read ---> Memory
t3: Memory ---> MBR
t4: (MBR) -> IR
(PC) +1 -> PC
5. CALL X; —Call x function, save return address on the top of stack.
Initial
snoopy
Iniatial Actions
E
Snoopy
The states in end
Initial
snoopy
Write hit 写命中
I
S
I
S
M
E
M
The states in begin
Initial
snoopy
Iniatial Actions
E
Snoopy
The states in end
Initial
snoopy
7
题型 5 寻址方式和指令格式 Addressing Modes and Formats micro-operations 微操作 CHAPTER 11
1. ADD AX, X; —The contents of AC adds the contents of location X, result is stored to AC.
5
题型 4 并行处理--MESI 协议 Parallel Processing--MESI CHAPTER 17 Read miss 读未命中
I
S
I
S
M
E
M
The states in begin
Initial
snoopy
Iniatial Actions
E
Snoopy
The states in end
Fetch cycle
Execute cycle
t1: (PC) -> MAR
t1: Ad(MBR) -> MAR
t2: (MAR) ---> Memory
t2: (MAR) -> Memory
read ---> Memory
read ->Memory
t3: Memory ---> MBR
t3: Memory-> MBR
Fetch cycle
Execute cycle
t1: (PC) -> MAR
t1: (PC) -> MBR
t2: (MAR) ---> Memory
(SP) -> MAR
read ---> Memory
t2: (MBR) ---> Memory
t3: Memory ---> MBR
(MAR) --> Memory