Quartus常见错误分析 Error

design.
7 Warning: VHDL Process Statement warning at divider_10.vhd(17): signal "cnt" is read inside the Process
Statement but isn't in the Process Statement's sensivitity list
cannot be read. Change object mode to buffer or inout.
------信号类型设置不对，out当作buffer来定义
4 Error: Node instance "clk_gen1" instantiates undefined entity "clk_gen"
-------引用的例化元件未定义实体－－entity "clk_gen"
5 Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s)
analyzed as buffer(s) resulting in clock skew
-------同一进程中含有两个或多个if(edge)条件，（一个进程中之能有一个时钟沿）
26 Error: Can't resolve multiple constant drivers for net "datain_reg[22]" at shift_reg.vhd(19)
27 can't infer register for signal "num[0]" because signal does not hold its outside clock edge
28Error: Can't elaborate top-level user hierarchy
29 Error: Can't resolve multiple constant drivers for net "cs_in" at led_key.vhd(32)
----------有两个以上赋值语句，不能确定“cs_in”的值，
－－－－－－－－因为前一个错误而导致的错误
24 Error: VHDL error at period_counter.vhd(38): type of identifier "alarm" does not agree with its usage
as std_logic type
11 Warning: Circuit may not operate. Detected 1 non-operational path(s) clocked by clock "sign" with
clock skew larger than data delay. See Compilation Report for details.
Info: Detected ripple clock "clk_gen:clk_gen1|clk_incr" as buffer
Info: Detected ripple clock "clk_gen:clk_gen1|clk_scan" as buffer
6 Warning: VHDL Process Statement warning at ledmux.vhd(15): signal or variable "dataout" may not be
21 Error: VHDL error at impulcomp.vhd(19): can't implement clock enable condition specified using binary
operator "or"
22 Error: VHDL Association List error at period_counter.vhd(38): actual parameter assigned to formal
Warning: No output dependent on input pin "clk"
Warning: No output dependent on input pin "sign"
------输出信号与输入信号无关，
20 Warning: Found clock high time violation at 16625.0 ns on register "|impulcomp|gate1"
GND
10 Warning: Circuit may not operate. Detected 1 non-operational path(s) clocked by clock "class[1]" with
clock skew larger than data delay. See Compilation Report for details.
30 Warning: Ignored node in vector source file. Can't find corresponding node name "over" in design.
---------------在源文件中找不到对应的节点“over”。
31 Error: Can't access JTAG chain
14 Error: VHDL Binding Indication error at freqdetect_top.vhd(19): port "class" in design entity does
not have std_logic_vector type that is specified for the same generic in the associated component
-----缺少敏感信号
8 Warning: No clock transition on "counter_bcd7:counter_counter_clk|q_sig[3]" register
9 Warning: Reduced register "counter_bcd7:counter_counter_clk|q_sig[3]" with stuck clock port to stuck
Warning: VHDL Process Statement warning at random.vhd(18): signal reset is in statement, but is not in
sensitivity list
----没把singal放到process（）中
3 Error: VHDL Interface Declaration error in clk_gen.vhd(29): interface object "clk_scan" of mode out
－－－－－－－－"alarm"的定义类型与使用的类型不一致
25 Error: VHDL error at shift_reg.vhd(24): can't synthesize logic for statement with conditions that
test for the edges of multiple clocks
1.
Warning: Found pins ing as undefined clocks and/or memory enables
Info: Assuming node CLK is an undefined clock
-=-----可能是说设计中产生的触发器没有使能端
2 ]"被优化掉了
18 Warning: Reduced register "gate~reg0" with stuck data_in port to stuck GND
19 Warning: Design contains 2 input pin(s) that do not drive logic
13 Warning: Ignored node in vector source file. Can't find corresponding node name "class_sig[2]" in
design.
------没有编写testbench文件，或者没有编辑输入变量的值 testbench里是元件申明和映射
16 Warning: Found clock high time violation at 1000.0 ns on register
"|fcounter|lpm_counter:temp_rtl_0|dffs[4]"
17 Warning: Compiler packed, optimized or synthesized away node "temp[19]". Ignored vector source file
12 Error: VHDL error at counter_clk.vhd(90): actual port "class" of mode "in" cannot be associated with