MSP430_Timer_A学习笔记

Introduction

1)16-bit timer/counter with three capture/compare registers.

2)Multiple capture/compares,PWM outputs,and interval timing.

3)Interrupt capabilities

4)Selectable and configurable clock source

Blockdiagram

Operation

1.16- bit Timer Counter

16-bit timer/counter register(TAR) increments or decrements (depending on the mode of operation)with each rising edge of the clock signal.

TAR can be written or read with software.

Timer_A can generate interrupt when TAR overflows.

TACLR: clear TAR,clock divider and count direction

1)Clock Source Select and Divider

Source:ACLK,SMCLK,or externally via TACLK or INCLK.

The clock source is selected with the TASSELx bits.

Using the IDx bits to select divider(2,4 or 8).

2.Starting the Timer

MCx>0 and clock source is active.

When the timer mode is either up or up/down,the timer may be stopped by writing 0 to TACCR0.

The timer may be restarted by writing a nonzero value to TACCR0.

(increment to zero)

3.Timer Mode Control(MCx)

1)Up mode

Attention: changing TACCR0 while the timer is running.

2)Continuous Mode

Usage:Generate independent time interval and output frequencies.

Each time an interval is completed, an interrupt is generated.

Thenext time interval is added to the TACCRx register in the interrupt

service routine(中断服务例程).

The CCIFG interrupt flag is set when the timer counts to the TACCR0value. The TAIFG interrupt flag is set when the timer counts

from TACCR0 to zero

3)Up/Down Mode

4.Capture/Compare Blocks

Capture mode: when CAP=1,capture mode is used to record time events. It can be used for speed computations or time measurements. The capture inputs CCIxA and CCIxB are connected to external signals and are selected with the CCISx bits.

CMx: select capture edge(rising, falling or both ).

If a capture occurs:

Timer value is copied into the TACCRx register.

CCIFG is set.

Setting the SCS bit will synchronize the capture with the next timer clock.

1)Capture Innitiated

Set CMx bits. then

Sets CCIS1=1 and toggles bit CCIS0to switch the capture signal

between Vcc and GND.

Initiating a capture each time CCIS0 changes state

Compare Mode:

CAP=0, compare mode is used to generate PWM output signals or interrupt at specific time intervals.

When TAR counts to the value in a TACCRx:

CCIFG is set.

EQUx=1, affects the output.

CCI is latched into SCCI.

5.TACCR0 Interrupt

1)TACCR0 Interrupt(CCIFG)

Highest Timer_A interrupt priority. Automatically reset when the TACCR0 interrupt request is serviced.

2)TAIV, Interrupt Vector Generator

TACCR1 CCIFG, TACCR2 CCIFG, and TAIFG flags are prioritized and combined to source a single interrupt vector.

3)