STM32F103VBT6
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■ DMA
– 7-channel DMA controller – Peripherals supported: timers, ADC, SPIs,
I2Cs and USARTs
LQFP48 7 x 7 mm
LQFP100 14 x 14 mm
LQFP64 10 x 10 mm
BGA100 10 x 10 mm
5.3.9 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.3.5 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.3.6 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4
Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.3.2 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 27
5.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.1 Test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
July 2007
Rev 2
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
5.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
STM32F103x6 STM32F103x8 STM32F103xB
Performance line, ARM-based 32-bit MCU with Flash, USB, CAN, seven 16-bit timers, two ADCs and nine communication interfaces
Table 1. Device summary
Reference
Root part number
STM32F103x6 STM32F103C6, STM32F103R6
STM32F103x8
STM32F103C8, STM32F103R8 STM32F103V8
STM32F103xB STM32F103RB STM32F103VB
5.3.3 Embedded reset and power control block characteristics . . . . . . . . . . . 28
5.3.4 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
– 2 x 16-bit watchdog timers (Independent and Window)
– SysTick timer: a 24-bit downcounter
■ Up to 9 communication interfaces – Up to 2 x I2C interfaces (SMBus/PMBus) – Up to 3 USARTs (ISO 7816 interface, LIN, IrDA capability, modem control) – Up to 2 SPIs (18 Mbit/s) – CAN interface (2.0B Active) – USB 2.0 full speed interface
calibration
■ Low power
– Sleep, Stop and Standby modes – VBAT supply for RTC and backup registers ■ 2 x 12-bit, 1 µs A/D converters (16-channel)
– Conversion range: 0 to 3.6 V – Dual-sample and hold capability – Synchronizable with advanced control timer – Temperature sensor
■ Debug mode
– Serial wire debug (SWD) & JTAG interfaces
■ Up to 80 fast I/O ports
– 32/49/80 5 V-tolerant I/Os – All mappable on 16 external interrupt
vectors – Atomic read/modify/write operations
5.3.7 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5.3.8 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
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1
Contents
Contents
STM32F103xx
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
5.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
maskable interrupt channels – Interrupt processing (down to 6 CPU
cycles) with tail chaining
■ Memories
– 32-to-128 Kbytes of Flash memory – 6-to-20 Kbytes of SRAM
■ Up to 7 timers
– Up to three 16-bit timers, each with up to 4 IC/OC/PWM or pulsΒιβλιοθήκη Baidu counter
– 16-bit, 6-channel advanced control timer: up to 6 channels for PWM output Dead time generation and emergency stop
2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3
Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
■ Clock, reset and supply management
– 2.0 to 3.6 V application supply and I/Os – POR, PDR, and programmable voltage
detector (PVD) – 4-to-16 MHz quartz oscillator – Internal 8 MHz factory-trimmed RC – Internal 32 kHz RC – PLL for CPU clock – Dedicated 32 kHz oscillator for RTC with
Preliminary Data
Features
■ Core: ARM 32-bit Cortex™-M3 CPU
– 72 MHz, 90 DMIPS with 1.25 DMIPS/MHz – Single-cycle multiplication and hardware
division – Nested interrupt controller with 43
– 7-channel DMA controller – Peripherals supported: timers, ADC, SPIs,
I2Cs and USARTs
LQFP48 7 x 7 mm
LQFP100 14 x 14 mm
LQFP64 10 x 10 mm
BGA100 10 x 10 mm
5.3.9 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.3.5 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.3.6 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4
Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.3.2 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 27
5.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.1 Test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
July 2007
Rev 2
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
5.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
STM32F103x6 STM32F103x8 STM32F103xB
Performance line, ARM-based 32-bit MCU with Flash, USB, CAN, seven 16-bit timers, two ADCs and nine communication interfaces
Table 1. Device summary
Reference
Root part number
STM32F103x6 STM32F103C6, STM32F103R6
STM32F103x8
STM32F103C8, STM32F103R8 STM32F103V8
STM32F103xB STM32F103RB STM32F103VB
5.3.3 Embedded reset and power control block characteristics . . . . . . . . . . . 28
5.3.4 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
– 2 x 16-bit watchdog timers (Independent and Window)
– SysTick timer: a 24-bit downcounter
■ Up to 9 communication interfaces – Up to 2 x I2C interfaces (SMBus/PMBus) – Up to 3 USARTs (ISO 7816 interface, LIN, IrDA capability, modem control) – Up to 2 SPIs (18 Mbit/s) – CAN interface (2.0B Active) – USB 2.0 full speed interface
calibration
■ Low power
– Sleep, Stop and Standby modes – VBAT supply for RTC and backup registers ■ 2 x 12-bit, 1 µs A/D converters (16-channel)
– Conversion range: 0 to 3.6 V – Dual-sample and hold capability – Synchronizable with advanced control timer – Temperature sensor
■ Debug mode
– Serial wire debug (SWD) & JTAG interfaces
■ Up to 80 fast I/O ports
– 32/49/80 5 V-tolerant I/Os – All mappable on 16 external interrupt
vectors – Atomic read/modify/write operations
5.3.7 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5.3.8 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
1/67
www.st.com
1
Contents
Contents
STM32F103xx
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
5.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
maskable interrupt channels – Interrupt processing (down to 6 CPU
cycles) with tail chaining
■ Memories
– 32-to-128 Kbytes of Flash memory – 6-to-20 Kbytes of SRAM
■ Up to 7 timers
– Up to three 16-bit timers, each with up to 4 IC/OC/PWM or pulsΒιβλιοθήκη Baidu counter
– 16-bit, 6-channel advanced control timer: up to 6 channels for PWM output Dead time generation and emergency stop
2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3
Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
■ Clock, reset and supply management
– 2.0 to 3.6 V application supply and I/Os – POR, PDR, and programmable voltage
detector (PVD) – 4-to-16 MHz quartz oscillator – Internal 8 MHz factory-trimmed RC – Internal 32 kHz RC – PLL for CPU clock – Dedicated 32 kHz oscillator for RTC with
Preliminary Data
Features
■ Core: ARM 32-bit Cortex™-M3 CPU
– 72 MHz, 90 DMIPS with 1.25 DMIPS/MHz – Single-cycle multiplication and hardware
division – Nested interrupt controller with 43