计算机体系结构第二章
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Figure 2.2 Possible combinations of memory operands and total operands per typical ALU instruction with examples of machines
Number of memory addresses Maximum number of operands allowed Type of architecture Examples
Stack Accumulator Register (register-memory) Register (load-store)
Push A Push B Add Pop C
Load A Add B Store C
Load R1,A Add R1,B Store C,R1
Load R1,A Load R2,B Add R3,R1,R2 Store C,R3
3
There are really two classes of register computers. register-memory architecture :one class can access memory as part of any instruction load-store or register-register architecture: one class can access memory only with load and store instructions memory-memory architecture: keeps all operands in memory, not found in machines shipping today
87 87
65 65
43 43
21 21
87、65、43、21 will be arranged in memory 480~483 according to Big Endian
480 481 482
483
482
481
480
2) Intel 80x86 Systems store multibyte values in Little Endian bytes order
Computer Architecture
Chapter 2 Instruction Set Wangbing
1
Chapter 2 Instruction Set
2.1 2.2 2.3 2.4 2.5 2.6 2.7 Classifying Instruction Set Architecture Interpreting Memory Addresses Addressing Modes Optimizing Instruction Formats Operation in the Instruction Set RISC vs. CISC The DLX Architecture
X…X00
2byte
1byte
0byte
The address of a datum
10
Example:Suppose you have the 32-bit hexadecimal value 87654321 stored as a 32-bit word in byte-addressable memory at byte location 480,481,482,and 483. 1) What will be arranged in memory 480~483 according to Little Endian and Big Endian? 2) In which bytes order do Intel 80x86 Systems store multibyte values? Answer: 1)21、43、65、87 will be arranged in memory 480~483 according to Little Endian
4
Figure 2.1 The code sequence for C=A+B for four instruction sets
The major reasons for the emergence of generalpurpose register(GPR) machines :
Register—like other forms of storage internal to the CPU– are faster than memory. Registers are easier for a compiler to use and can be used more effectively than other forms of internal storage. when variables are allocated to registers,the memory traffic reduces,the program speeds up ,and the code density improves.
Register Simple,fixed-length instruction -register encoding.Simple code-generation model.Instruction take similar (0,3) numbers of clocks to execute.
Add R3,R1,R2
0 1 2 3
3 2 2 3
Register-register
SPARC,MIPS,PowerPC, Precision Architecture, ALPHA Intel 80x86,Motorola 68000 VAX(also has threeoperand formats) VAX(also has twooperand formats)
3byte 2byte 1byte 0byte
X…X00
Big Endian byte order puts the byte whose address is “x…x00”at the most-significant position in the word (the big end)
3byte
9
2.2 Interpreting Memory Addresses
Little Endian byte order puts the byte whose address is “x…x00”at the least-significant position in the word (the little end)
Compiler writers would prefer that all register be equivalent and unreserved.
5
Most compilers reserve some registers for : expression evaluation parameter passing hold variables Two major instruction set characteristics divide GPR(General-Purpose Register) architecture.Both characteristics concern the nature of operands for a typical arithmetic or logical instruction(ALU instruction ). (Figure 2.2) whether an ALU instruction has two or three operands. how many of the operands may be memory addresses in ALU instructions.
7
Register-memory Memory-memory Memory-memory
Type
Advantages
Disadvantages Higher instruction count than architectures with memory references in instruction.More instructions and lower instruction density leads to larger programs.
2
2.1 Classifying Instruction Set Architecture
The type of internal storage in the CPU is the most basic differentiation.(stack,accumulator,registers) stack architecture The operands are implicitly on the top of the stack accumulator architecture one operand is implicitly the accumulator general-purpose register(GPR) architecture The operands is explicitly either registers or memory locations
8
Memory memory (3,3)
Figure 2.3 Advantages and disadvantages of the three most common types of general-purpose register machines
Summary
Summary:Use general-purpose register machines with a load-store architecture How memory addresses are interpreted ? How memory addresses are specified? All the instruction sets discussed in this book are byte addressed and provideபைடு நூலகம்access for bytes(8 bits),half words(16 bits) and words(32 bits).Most of the machines also provide access for double words(64bits)
Register memory (1,2)
Data can be accessed without a Operands are not equivalent since separate load instruction First. a source operand in a binary Instruction format tends to be easy to operation is destroyed. Encoding encode and yields good density. a register number and a memory address in each instruction may restrict the number of registers. Clocks per instruction varies by Add R1,B operand location. Most compact. Doesn’t waste registers for temporaries. Large variation in instruction size,especially for three-operand instruction.Also,large variation in work per instruction.Memory accesses create memory bottleneck.
Figure 2.2 Possible combinations of memory operands and total operands per typical ALU instruction with examples of machines
Number of memory addresses Maximum number of operands allowed Type of architecture Examples
Stack Accumulator Register (register-memory) Register (load-store)
Push A Push B Add Pop C
Load A Add B Store C
Load R1,A Add R1,B Store C,R1
Load R1,A Load R2,B Add R3,R1,R2 Store C,R3
3
There are really two classes of register computers. register-memory architecture :one class can access memory as part of any instruction load-store or register-register architecture: one class can access memory only with load and store instructions memory-memory architecture: keeps all operands in memory, not found in machines shipping today
87 87
65 65
43 43
21 21
87、65、43、21 will be arranged in memory 480~483 according to Big Endian
480 481 482
483
482
481
480
2) Intel 80x86 Systems store multibyte values in Little Endian bytes order
Computer Architecture
Chapter 2 Instruction Set Wangbing
1
Chapter 2 Instruction Set
2.1 2.2 2.3 2.4 2.5 2.6 2.7 Classifying Instruction Set Architecture Interpreting Memory Addresses Addressing Modes Optimizing Instruction Formats Operation in the Instruction Set RISC vs. CISC The DLX Architecture
X…X00
2byte
1byte
0byte
The address of a datum
10
Example:Suppose you have the 32-bit hexadecimal value 87654321 stored as a 32-bit word in byte-addressable memory at byte location 480,481,482,and 483. 1) What will be arranged in memory 480~483 according to Little Endian and Big Endian? 2) In which bytes order do Intel 80x86 Systems store multibyte values? Answer: 1)21、43、65、87 will be arranged in memory 480~483 according to Little Endian
4
Figure 2.1 The code sequence for C=A+B for four instruction sets
The major reasons for the emergence of generalpurpose register(GPR) machines :
Register—like other forms of storage internal to the CPU– are faster than memory. Registers are easier for a compiler to use and can be used more effectively than other forms of internal storage. when variables are allocated to registers,the memory traffic reduces,the program speeds up ,and the code density improves.
Register Simple,fixed-length instruction -register encoding.Simple code-generation model.Instruction take similar (0,3) numbers of clocks to execute.
Add R3,R1,R2
0 1 2 3
3 2 2 3
Register-register
SPARC,MIPS,PowerPC, Precision Architecture, ALPHA Intel 80x86,Motorola 68000 VAX(also has threeoperand formats) VAX(also has twooperand formats)
3byte 2byte 1byte 0byte
X…X00
Big Endian byte order puts the byte whose address is “x…x00”at the most-significant position in the word (the big end)
3byte
9
2.2 Interpreting Memory Addresses
Little Endian byte order puts the byte whose address is “x…x00”at the least-significant position in the word (the little end)
Compiler writers would prefer that all register be equivalent and unreserved.
5
Most compilers reserve some registers for : expression evaluation parameter passing hold variables Two major instruction set characteristics divide GPR(General-Purpose Register) architecture.Both characteristics concern the nature of operands for a typical arithmetic or logical instruction(ALU instruction ). (Figure 2.2) whether an ALU instruction has two or three operands. how many of the operands may be memory addresses in ALU instructions.
7
Register-memory Memory-memory Memory-memory
Type
Advantages
Disadvantages Higher instruction count than architectures with memory references in instruction.More instructions and lower instruction density leads to larger programs.
2
2.1 Classifying Instruction Set Architecture
The type of internal storage in the CPU is the most basic differentiation.(stack,accumulator,registers) stack architecture The operands are implicitly on the top of the stack accumulator architecture one operand is implicitly the accumulator general-purpose register(GPR) architecture The operands is explicitly either registers or memory locations
8
Memory memory (3,3)
Figure 2.3 Advantages and disadvantages of the three most common types of general-purpose register machines
Summary
Summary:Use general-purpose register machines with a load-store architecture How memory addresses are interpreted ? How memory addresses are specified? All the instruction sets discussed in this book are byte addressed and provideபைடு நூலகம்access for bytes(8 bits),half words(16 bits) and words(32 bits).Most of the machines also provide access for double words(64bits)
Register memory (1,2)
Data can be accessed without a Operands are not equivalent since separate load instruction First. a source operand in a binary Instruction format tends to be easy to operation is destroyed. Encoding encode and yields good density. a register number and a memory address in each instruction may restrict the number of registers. Clocks per instruction varies by Add R1,B operand location. Most compact. Doesn’t waste registers for temporaries. Large variation in instruction size,especially for three-operand instruction.Also,large variation in work per instruction.Memory accesses create memory bottleneck.