verilog HDL 语言的数字钟设计

module shuzizhong(clk,rst,en,fyx,syx,naozhong,clk2,dsec,sec,kzf,kzs,a,b,c,d,e,f,g,h,kk,aa); input clk,en,fyx,syx,rst,clk2,kzf,kzs,kk,aa;
output naozhong;
output [3:0] dsec,sec,a,b,c,d,e,f,g,h;
reg[3:0] cn,dcn,xh,dxh,nf,dnf,ns,dns;
reg [3:0] sec,dsec;
reg [7:0] qr,qy,qn,data;
reg clkn,clky;
reg [3:0] a,b,c,d,e,f,g,h;
reg naozhong;
reg minclk, hourclk,dayclk,monthclk,yearclk;
显示模块
always @(kk)
begin
if(kk)
begin
a<=dxh;
b<=xh;
c<=dcn;
d<=cn;
e<=dns;
f<=ns;
g<=dnf;
h<=nf;
end
else
begin
a<=qn[7:4];
b<=qn[3:0];
c<=0;
d<=qy[7:4];
e<=qy[3:0];
f<=0;
g<=qr[7:4];
h<=qr[3:0];
end
end
秒计数和秒校正模块
always@(posedge clk or negedge rst)
begin
if(!rst)
begin
sec[3:0]<=4'b0000;
dsec[3:0]<=4'b0000;
end
else
begin
if(en==1 && aa==1)
begin
if(sec[3:0]==9)
begin
sec[3:0]<=0;
if(dsec[3:0]==5)
begin
dsec[3:0]<=0;
minclk<=1;
end
else
begin
dsec[3:0]<=dsec[3:0]+1'b1;
minclk<=0;
end
end
else
begin
sec[3:0]<=sec[3:0]+1'b1;
minclk<=0;
end
end
end
end
分计数和分校正模块
always@(posedge clk or negedge rst)
begin
if(!rst)
begin
dcn[3:0]<=4'b0000;
cn[3:0]<=4'b0000;
end
else
begin
if(minclk==1)
begin
if(en==1 && aa==1)
begin
if(cn[3:0]==9)
begin
cn[3:0]<=0;
if(dcn[3:0]==5)
begin
dcn[3:0]<=0;
hourclk<=1;
end
else
begin
dcn[3:0]<=dcn[3:0]+1'b1;
hourclk<=0;
end
end
else
begin
cn[3:0]<=cn[3:0]+1'b1;
hourclk<=0;
end
end
end
else
begin
if(en==0 && aa==1)
begin
hourclk<=0;
if(fyx)
begin
if(cn<9)
cn<=cn+1'b1;
else
begin
cn[3:0]<=4'b0000;
if(dcn[3:0]<5)
dcn[3:0]<=dcn[3:0]+1'b1;
else
dcn[3:0]<=4'b0000;
end
end
end
end
end
end
时计数和时校正模块
always@(posedge hourclk or negedge rst)
begin
if(!rst)
begin
xh[3:0]<=4'b0000;
dxh[3:0]<=4'b0000;
end
else
begin
if(hourclk==1)
begin
if(en==1 && aa==1 )
begin
if(xh[3:0]==3 && dxh[3:0]==2)
begin
xh[3:0]<=0;
dxh[3:0]<=0;
dayclk<=1;
end
else
begin
dayclk<=0;
if(xh[3:0]<9)
xh[3:0]<=xh[3:0]+1'b1;
else
begin
xh[3:0]<=0;
if(dxh[3:0]<2)
dxh[3:0]<=dxh[3:0]+1'b1;
else
dxh[3:0]<=0;
end
end
end
end
else
begin
if (en==0 && aa==1 )
begin
if(syx)
begin
if(xh[3:0]==3 && dxh[3:0]==2)
begin
xh[3:0]<=0;
dxh[3:0]<=0;
end
else
begin
if(xh[3:0]<9)
xh[3:0]<=xh[3:0]+1'b1;
else
begin
xh[3:0]<=0;
if(dxh[3:0]<2)
dxh[3:0]<=dxh[3:0]+1'b1;
else
dxh[3:0]<=0;
end
end
end
end
end
end
end
日计数和日校正模块
always@(posedge clk or negedge rst)
begin
if(!rst)
begin
qr=8'b1;
end
else
if(dayclk==1)
begin
if(en==1 && aa==0)
begin
monthclk=0;
if(qr==data)
begin
qr=8'b1;
monthclk=1;
end
else if(qr[3:0]==4'b1001)
begin
qr[7:4]=qr[7:4]+2'b1;
qr[3:0]=4'b0;
end
else qr=qr+2'b1;
end
end
else if(en==0 && aa==0 )
begin
if(kzs)
begin
if(qr[7:4]==3)
begin
if (qr[3:0]==1)
begin
qr[7:4]<=0;
qr[3:0]<=1;
end
else
qr[3:0]=qr[3:0]+1'b1;
end
else
begin
if(qr[3:0]==9)
begin
qr[3:0]=0;
qr[7:4]<=qr[7:4]+1'b1;
end
else
qr[3:0]<=qr[3:0]+1'b1;
end
end
end
end
//月计数器和校正模块
always @(posedge clk or negedge rst)
begin
if(!rst)
begin
qy=8'b1;
end
else
if(monthclk==1)
begin
if(en==1 && aa==0)
begin
yearclk=0;
if(qy==8'b10010)
begin
qy=8'b1;
yearclk=1;
end
else if(qy[3:0]==4'b1001)
begin
qy[7:4]=4'b1;
qy[3:0]=4'b0;
end
else qy=qy+2'b1;
end
end
else if(en==0 && aa==0)
begin
if(kzf)
begin
if(qy[7:4]==1)
begin
if(qy[3:0]==2)
begin
qy[7:4]<=0;
qy[3:0]<=1;
end
else
qy[3:0]<=qy[3:0]+1'b1;
end
else
begin
if(qy[3:0]==9)
begin
qy[3:0]<=0;
qy[7:4]<=qy[7:4]+1'b1;
end
else
qy[3:0]<=qy[3:0]+1'b1;
end
end
end
end
//data的产生
always
begin
case(qy)
8'b1:data=8'b110001;
8'b11:data=8'b110001;
8'b101:data=8'b110001;
8'b111:data=8'b110001;
8'b1000:data=8'b110001;
8'b10000:data=8'b110001;
8'b10010:data=8'b110001;
8'b100:data=8'b110000;
8'b110:data=8'b110000;
8'b1001:data=8'b110000;
8'b10001:data=8'b110000;
8'b10:data=8'b101000;
endcase
end
//年计数模块和年校正模块
always @(posedge clk or negedge rst)
begin
if(!rst)
begin
qn=8'b0;
end
else
if(yearclk==1)
begin
if(en==1 && aa==0)
begin
if(qn==8'b10011001)
qn=8'b0;
else if(qn[3:0]==4'b1001)
begin
qn[7:4]=qn[7:4]+2'b1;
qn[3:0]=4'b0;
end
else qn=qn+2'b1;
end
end
else if(en==0 && aa==0)
begin
if(syx)
begin
if(qn[7:4]==9)
begin
if(qn[3:0]==9)
begin
qn[7:4]<=0;
qn[3:0]<=0;
end
else
qn[3:0]<=qn[3:0]+1'b1;
end
else
begin
if(qn[3:0]==9)
begin
qn[3:0]<=0;
qn[7:4]<=qn[7:4]+1'b1;
end
else
qn[3:0]<=qn[3:0]+1'b1;
end
end
end
end
闹钟模块
always@(posedge clk2)
begin
if(!rst)
begin
nf[3:0]<=4'b0000;
dnf[3:0]<=4'b0000;
ns[3:0]<=4'b0000;
dns[3:0]<=4'b0000;
end
else if(en)
begin
if(kzf)
begin
if(nf<9)
nf[3:0]<=nf[3:0]+1'b1;
else
begin
nf[3:0]<=4'b0000;
if(dnf<5)
dnf<=dnf+1'b1;
else
dnf[3:0]<=4'b0000;
end
end
else if(kzs)
begin
if(dns[3:0]==2 && ns[3:0]==3)
begin
dns<=0;
ns<=0;
end
else
begin
if(ns<9)
ns[3:0]<=ns[3:0]+1'b1;
else
begin
ns[3:0]<=4'b0000;
if(dns<2)
dns<=dns+1'b1;
else
dns<=0;
end
end
end
end
end
always @(en)
begin
if(en)
begin
if((cn==nf) && (dcn==dnf) && (xh==ns) && (dxh==dns)) naozhong<=1;
else
naozhong<=0;
end
end
endmodule。