SAA6579_SAA6579T-RDS解码芯片
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The data signal RDDA and the clock signal RDCL are provided as outputs for further processing by a suitable decoder (microcomputer).
The operational functions of the device are in accordance with the “CENELEC EN 50067”.
SYMBOL
VDDA VDDD Vn Tstg Tamb Ves
PARAMETER
analog supply voltage (pin 5) digital supply voltage (pin 12) voltage on all pins; grounds excluded storage temperature operating ambient temperature electrostatic handling for all pins except pins 9 and 10
functions • Differential decoder • Signal quality detector • Subcarrier output.
GENERAL DESCRIPTION
The integrated CMOS circuit SAA6579 is an RDS demodulator. It recovers the additional inaudible RDS information which is transmitted by FM radio broadcasting.
6
ground for analog part (0 V)
7
subcarrier input to comparator
8
subcarrier output of reconstruction filter
9
oscillator mode/test control input
10 test enable input
CONDITIONS
note 1 note 2
MIN.
0 0 −0.5 −40 −40 ±300 +1 500
MAX.
6 6 VDDX + 0.5 +150 +85 − −3 000
UNIT
V V V °C °C V V
Notes 1. Equivalent to discharging a 200 pF capacitor via a 0 Ω series resistor. 2. Equivalent to discharging a 100 pF capacitor via a 1.5 kΩ series resistor.
质量位发生器
振荡器和分频器
COSTAS LOOP VARIABLE AND FIXED DIVIDER
SAA6579
BIPHASE SYMBOL DECODER
DIFFERENTIAL 2 DECODER
差分译码器
16
RDDA RDCL
CLOCK REGENERATION
AND SYNC
TEST LOGIC AND OUTPUT SELECTOR SWITCH
9 MODE
MGD684
handbook, halfpage
QUAL 1
16 RDCL
RDDA 2
15 T57
Vref 3
14 OSCO
MUX 4
13 OSCI
SAA6579T
VDDA 5
12 VDDD
VSSA 6
11 VSSD
CIN 7
10 TEST
SCOUT 8
9 MODE
MGD685
Fig.2 Pin configuration.
PIN
DESCRIPTION
1
quality indication output
2
RDS data output
3
reference voltage output (0.5VDDA)
4
multiplex signal input
5
+5 V supply voltage for analog part
signals • Selectable 4.332/8.664 MHz crystal oscillator with
variable dividers • Clock regeneration with lock on biphase data rate • Biphase symbol decoder with integrate and dump
Fig.3 Pin configuration.
1997 Feb 24
4
Philips Semiconductors
Radio Data System (RDS) demodulator
Product specification
SAA6579
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134); ground pins 6 and 11 connected together.
Product specification
SAA6579
handbook, halfpage
QUAL 1
16 RDCL
RDDA 2
15 T57
Vref 3 MUX 4 VDDA 5 VSSA 6
CIN 7
14 OSCO
13 OSCI
SAA6579
12 VDDD
11 VSSD
10 TEST
SCOUT 8
MIN.
3.6 3.6 − 1 4.4 − −40
TYP.
5.0 5.0 6 − − − −
MAX. UNIT
5.5 V
5.5 V
−
mA
−
mV
−
V
0.4 V
+85 °C
ORDERING INFORMATION
TYPE NUMBER
SAA6579 SAA6579T
NAME DIP16 SO16
PACKAGE DESCRIPTION plastic dual in-line package; 16 leads (300 mil); long body plastic small outline package; 16 leads; body width 7.5 mm
11 ground for digital part (0 V)
12 +5 V supply voltage for digital part
13 oscillator input
14 oscillator output
15 57 kHz clock signal output
16 RDS clock output
FUNCTIONAL DESCRIPTION
The SAA6579 is a demodulator circuit for RDS applications. It contains a 57 kHz bandpass filter and a digital demodulator to regenerate the RDS data stream out of the multiplex signal (MPX).
逻辑输出开关
9 MODE
10 TEST
15 T57
11 VSSD
MEH162
Via pin MODE two different crystal frequencies can be used.
MODE LOW HIGH
CRYSTAL CLOCK 4.332 MHz 8.664 MHz
Fig.1 Block diagram and application circuit.
MPX signal
MUX 4
330 pF
SCOUT 8
ANTIALIASING
FILTER
560 pF
CIN 7
CLOCKED
COMPARATOR
+5 V VDDA 5 0.1 µF Vref 3
VP1
REFERENCE VOLTAGE
2.2 µF
6 VSSA
47 pF 4.332/8.664 MHz
Filter part
The MUX signal is band-limited by a second-order anti-aliasing-filter and fed through a 57 kHz band-pass filter (8th order band-pass filter with 3 kHz bandwidth) to separate the RDS signals. This filter uses switched capacitor technique and is clocked by a clock frequency of 541.5 kHz derived from the 4.332/8.664 MHz crystal oscillator. Then the signal is fed to the reconstruction filter to smooth the sampled and filtered RDS signal before it is output on pin 8. The signal is AC-coupled to the comparator (pin 7). The comparator is clocked with a frequency of 228 kHz (synchronized by the 57 kHz of the demodulator).
1997 Feb 24
Philips Semiconductors
Radio Data System (RDS) demodulator
Product specification
SAA6579
FEATURES
• Anti-aliasing filter (2nd order) • Integrated 57 kHz band-pass filter (8th order) • Reconstruction filter (2nd order) • Clocked comparator with automatic offset compensation • 57 kHz carrier regeneration • Synchronous demodulator for 57 kHz modulated RDS
1997 Feb 24
3
Philips Semiconductors
Radio Data System (RDS) demodulator
PINNING
SYMBOL QUAL RDDA Vref MUX VDDA VSSA CIN SCOUT MODE TEST VSSD VDDD OSCI OSCO T57 RDCL
VERSION SOT38-1 SOT162-1
1997 Feb 24
2
Philips Semiconductors
Radio Data System (RDS) demodulator
BLOCK DIAGRAM
Product specification
SAA6579
handbook, full pagewidth
INTEGRATED CIRCUITS
DATA SHEET
SAA6579 Radio Data System (RDS) demodulator
Product specification Supersedes data of January 1994 File under Integrated Circuits, IC01
82 pF
+5 V
2.2 k Ω
0.1 µF
57K Hz第八阶带通滤波
57 kHz BANDPASS (8th ORDER)
RECONSTRUCTION
FILTER
重构滤波器
Biblioteka Baidu
OSCI 13
OSCO 14
V DDD 12
OSCILLATOR AND
DIVIDER
QUALITY BIT 1 QUAL
GENERATOR
QUICK REFERENCE DATA
SYMBOL
VDDA VDDD Itot Vi(rms) VOH VOL Tamb
PARAMETER analog supply voltage (pin 5) digital supply voltage (pin 12) total supply current RDS input amplitude (RMS value; pin 4) HIGH level output voltage for signals RDDA, RDCL, QUAL and T57 LOW level output voltage for signals RDDA, RDCL, QUAL and T57 operating ambient temperature
The operational functions of the device are in accordance with the “CENELEC EN 50067”.
SYMBOL
VDDA VDDD Vn Tstg Tamb Ves
PARAMETER
analog supply voltage (pin 5) digital supply voltage (pin 12) voltage on all pins; grounds excluded storage temperature operating ambient temperature electrostatic handling for all pins except pins 9 and 10
functions • Differential decoder • Signal quality detector • Subcarrier output.
GENERAL DESCRIPTION
The integrated CMOS circuit SAA6579 is an RDS demodulator. It recovers the additional inaudible RDS information which is transmitted by FM radio broadcasting.
6
ground for analog part (0 V)
7
subcarrier input to comparator
8
subcarrier output of reconstruction filter
9
oscillator mode/test control input
10 test enable input
CONDITIONS
note 1 note 2
MIN.
0 0 −0.5 −40 −40 ±300 +1 500
MAX.
6 6 VDDX + 0.5 +150 +85 − −3 000
UNIT
V V V °C °C V V
Notes 1. Equivalent to discharging a 200 pF capacitor via a 0 Ω series resistor. 2. Equivalent to discharging a 100 pF capacitor via a 1.5 kΩ series resistor.
质量位发生器
振荡器和分频器
COSTAS LOOP VARIABLE AND FIXED DIVIDER
SAA6579
BIPHASE SYMBOL DECODER
DIFFERENTIAL 2 DECODER
差分译码器
16
RDDA RDCL
CLOCK REGENERATION
AND SYNC
TEST LOGIC AND OUTPUT SELECTOR SWITCH
9 MODE
MGD684
handbook, halfpage
QUAL 1
16 RDCL
RDDA 2
15 T57
Vref 3
14 OSCO
MUX 4
13 OSCI
SAA6579T
VDDA 5
12 VDDD
VSSA 6
11 VSSD
CIN 7
10 TEST
SCOUT 8
9 MODE
MGD685
Fig.2 Pin configuration.
PIN
DESCRIPTION
1
quality indication output
2
RDS data output
3
reference voltage output (0.5VDDA)
4
multiplex signal input
5
+5 V supply voltage for analog part
signals • Selectable 4.332/8.664 MHz crystal oscillator with
variable dividers • Clock regeneration with lock on biphase data rate • Biphase symbol decoder with integrate and dump
Fig.3 Pin configuration.
1997 Feb 24
4
Philips Semiconductors
Radio Data System (RDS) demodulator
Product specification
SAA6579
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134); ground pins 6 and 11 connected together.
Product specification
SAA6579
handbook, halfpage
QUAL 1
16 RDCL
RDDA 2
15 T57
Vref 3 MUX 4 VDDA 5 VSSA 6
CIN 7
14 OSCO
13 OSCI
SAA6579
12 VDDD
11 VSSD
10 TEST
SCOUT 8
MIN.
3.6 3.6 − 1 4.4 − −40
TYP.
5.0 5.0 6 − − − −
MAX. UNIT
5.5 V
5.5 V
−
mA
−
mV
−
V
0.4 V
+85 °C
ORDERING INFORMATION
TYPE NUMBER
SAA6579 SAA6579T
NAME DIP16 SO16
PACKAGE DESCRIPTION plastic dual in-line package; 16 leads (300 mil); long body plastic small outline package; 16 leads; body width 7.5 mm
11 ground for digital part (0 V)
12 +5 V supply voltage for digital part
13 oscillator input
14 oscillator output
15 57 kHz clock signal output
16 RDS clock output
FUNCTIONAL DESCRIPTION
The SAA6579 is a demodulator circuit for RDS applications. It contains a 57 kHz bandpass filter and a digital demodulator to regenerate the RDS data stream out of the multiplex signal (MPX).
逻辑输出开关
9 MODE
10 TEST
15 T57
11 VSSD
MEH162
Via pin MODE two different crystal frequencies can be used.
MODE LOW HIGH
CRYSTAL CLOCK 4.332 MHz 8.664 MHz
Fig.1 Block diagram and application circuit.
MPX signal
MUX 4
330 pF
SCOUT 8
ANTIALIASING
FILTER
560 pF
CIN 7
CLOCKED
COMPARATOR
+5 V VDDA 5 0.1 µF Vref 3
VP1
REFERENCE VOLTAGE
2.2 µF
6 VSSA
47 pF 4.332/8.664 MHz
Filter part
The MUX signal is band-limited by a second-order anti-aliasing-filter and fed through a 57 kHz band-pass filter (8th order band-pass filter with 3 kHz bandwidth) to separate the RDS signals. This filter uses switched capacitor technique and is clocked by a clock frequency of 541.5 kHz derived from the 4.332/8.664 MHz crystal oscillator. Then the signal is fed to the reconstruction filter to smooth the sampled and filtered RDS signal before it is output on pin 8. The signal is AC-coupled to the comparator (pin 7). The comparator is clocked with a frequency of 228 kHz (synchronized by the 57 kHz of the demodulator).
1997 Feb 24
Philips Semiconductors
Radio Data System (RDS) demodulator
Product specification
SAA6579
FEATURES
• Anti-aliasing filter (2nd order) • Integrated 57 kHz band-pass filter (8th order) • Reconstruction filter (2nd order) • Clocked comparator with automatic offset compensation • 57 kHz carrier regeneration • Synchronous demodulator for 57 kHz modulated RDS
1997 Feb 24
3
Philips Semiconductors
Radio Data System (RDS) demodulator
PINNING
SYMBOL QUAL RDDA Vref MUX VDDA VSSA CIN SCOUT MODE TEST VSSD VDDD OSCI OSCO T57 RDCL
VERSION SOT38-1 SOT162-1
1997 Feb 24
2
Philips Semiconductors
Radio Data System (RDS) demodulator
BLOCK DIAGRAM
Product specification
SAA6579
handbook, full pagewidth
INTEGRATED CIRCUITS
DATA SHEET
SAA6579 Radio Data System (RDS) demodulator
Product specification Supersedes data of January 1994 File under Integrated Circuits, IC01
82 pF
+5 V
2.2 k Ω
0.1 µF
57K Hz第八阶带通滤波
57 kHz BANDPASS (8th ORDER)
RECONSTRUCTION
FILTER
重构滤波器
Biblioteka Baidu
OSCI 13
OSCO 14
V DDD 12
OSCILLATOR AND
DIVIDER
QUALITY BIT 1 QUAL
GENERATOR
QUICK REFERENCE DATA
SYMBOL
VDDA VDDD Itot Vi(rms) VOH VOL Tamb
PARAMETER analog supply voltage (pin 5) digital supply voltage (pin 12) total supply current RDS input amplitude (RMS value; pin 4) HIGH level output voltage for signals RDDA, RDCL, QUAL and T57 LOW level output voltage for signals RDDA, RDCL, QUAL and T57 operating ambient temperature