计算机组成

bit
2.2.3 Byte Ordering big endian computer SPARC IBM little endian computer Intel family
110 110
0 4 8 12 16
2.2.4 Error-Correcting Codes (1)Concepts Codeword , n=m(data bits)+r(check bits) Hamming distance (two codewords) , 10001001 and 10110001, Hamming code 10110 110001, 10001001 001 distance is 3. code distance (complete code), minimum Hamming distance of two codewords in list of the legal codewords.
0 1
7
2Figure 2-3 An interpreter for a simple computer (written in Java)
Interpreter A program that fetches, examines and executes the instructions of another program is called interpreter.
(2) Relationship between code distance and detecting capacity – detect d bit errors, code distance need d+1 bits ; correct d bit errors, code distance need 2d+ 1 bits . – L – 1 =D + C D≥C L : smallest code distance D : detecting error bits C : correcting error bits
error(4) error-correcting code
A code with only four valid code words 0000000000 0000011111 1111100000 1111111111
(5) Hamming Checking (correct 1 errors) Relationship between data bits (m) and m+r+1≤ check Bits (r) : m+r+1≤2r
• develop of microprogram technique
2.1.3 RISC versus SISC CISC Complex Instruction Set Computer RISC Reduced Instruction Set Computer
2.1.4 Design Principles for Modern Computers All Instructions Are Directly Executed by Hardware Maximize the Rate at Which Instruction Are Issued MIPS(Million of Instruction Per Second) Instructions Should be Easy to Decode Only Loads and Stores Should Reference Memory Provide Plenty Registers
2.1.2 Instruction Execution The step that CPU executes each instruction 1. Fetch the next instruction from memory into the instruction register. 2. Change the program counter to point to the following instruction. 3. Determine the type of instruction just fetched. 4. If the instruction uses a word in memory , determine where it is. 5. Fetch the word, if needed, into a CPU register.
Bit 1 checks bits ,1,3,5,7,9,11,13,15,17,19,21a a Bit 2 checks bits , 2,3,6,7,10,11,14,15,18,19 Bit 4 checks bits ,4,5,6,7,12,13,14,15,20,21 a Bit 8 checks bits ,8,9,10,11,12,13,14,15 Bit 16 checks bits ,16,17,18,19,20,21 b1+b2+…..bj=b
Coding method
grouping parity check
m (data ) + r (check) = n The bits are numbered starting at 1,not 0, with bit 1 the leftmost (high -order) bit.All bits whose bit number is a power of 2 are parity, the rest are used for data.
–PC(Program counter) execution –IR(Instruction Register)
point the
next instruction to be fetched for hold the
instruction currently being executed –general purpose registers and
(3) Parity Checking(error-detecting code)
Organization:Data + 1 checking bit , to make the number of “1” in a codeword 1 to be odd (even). Example : 10010011(0) ,10000101(1) Code Distance : 2 Checking capacity : detecting 1 bit error
–The equivalence between hardware
processors and interpreter • family of computer architecture
1).The ability to fix incorrectly implemented instructions in the field,or even make up for design deficiencies in the basic hardware. 2).The opportunity to add new instructions at minimal cost ,even after delivery of the machine. 3).Structured design that permitted efficient development , testing,and documenting of complex instructions.
6. Execute the instruction. 7. Go to step 1 to begin executing the following instruction.
Fetch instructions Analyze instructions Execute instructions
0
A simple method for finding the incorrect bit is first to compute all the parity bits.If all are correct,there was no error.Otherwise add up all the incorrect parity bits,the resulting sun is the position of the incorrect bit. Code Distance : 3 Check Capacity : detect 1 bit and correct 1 bit
Instruction2.1.5 Instruction-Level Parallelism (1) Pipeline
Latency——how Latency——how long it takes to execute an instruction . ——how Processor bandwidth ——how many MIPS the CPU has. With a cycle time of T nsec, and n stage in the pipeline,the latency is nT nsec and the bandwidth is 1000/T MIPS.
(2) Superscalar Architectures
Dual five-stage pipelines with a common instruction fetch unit
2.2 PRIMARY MEMORY
Store programs and data 2.2.1 Bits bit BCD (Binary Coded Decimal) code The number 1944 is shown below: 0001 1001 0100 0100 0000 0111 1001 1000 BCD binary 2.2.2 Memory Addresses Cell(or Cell(or location),each of which can store a piece information. Address,number Address,number of each cell.
specific purpose registers
2.1.1 CPU Organization data path
Most instruction can be divided into one of two categories : register memory instruction register register instruction. Word cycle:the data path cycle:the process of running two operands through the ALU and storing the result
2.1 Processors
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Bus : A collection of parallel wires for transmitting address , data ,control signals . CPU: Central Processing Unit (brain) Function : Execute program stored in the main memory by fetching their instructions , examining them, and then executing them one after another .
Organization : • Control Unit fetching instruction from main memory and determining their type. • ALU (Arithmetic Logic Unit) to carry out instruction by performing operations such as addition and Boolean AND . • Registers to store temporary results and certain control information.