数字逻辑课程设计(数字时钟)

武汉纺织大学《数字逻辑》课程设计报告题目：院系：专业班级：学号：学生姓名：指导教师：年月日一、引言《数字逻辑》课程设计是配合本课程课堂和实验教学的一个实践性教学环节。

其目的是巩固所学知识，提高实验动手能力，加强综合应用能力，启发创新思维。

其任务是让学生通过动手动脑进行大中型数字逻辑电路的设计、仿真、调试，巩固和应用所学的理论和实验技能；掌握应用EDA开发工具设计大中型数字电路系统的设计流程、仿真、检测技术直至下载到FPGA物理器件进行实际物理测试的能力；提高设计能力和实验技能，为以后进行毕业设计、电子电路的综合设计、研制电子产品等打下基础。

二、系统介绍1.设计平台介绍1)本次《数字逻辑》课程设计使用Altera公司的PLD/FPGA开发软件QuartusⅡ11.0和机房SOPC EDA工具箱。

2)本课程设计使用EP3C80F484C8逻辑芯片，需用Quartus创建一个工程，完成工程中各部分设计后画出总电路图，经过编译后分配管脚，下载到芯片中，在试验箱上连接导线，实现设计。

2.知识点及技术难点分析1)本次课程设计涉及到的知识点主要有：VHDL硬件语言、八段段显示器（数码管）相关知识、时序电路设计、EDA软件及试验箱的使用等。

2)其中较难的是时序电路的设计及EDA软件的使用。

三、设计任务及设计原理1.设计任务此次课程设计课题为数字电子逻辑电路设计，需在试验箱上实现一个24小时制动态显示的数字时钟，具有小时，分钟和秒的显示，且具有整点报时效果（例如在10:59:00开始，每隔2秒发出一次声音，前四次低频率，最后进位时发出高频率声响。

）2.设计原理1)这次课题中需用VHDL硬件语言编出秒钟、分钟、24小时制时钟、8选1数据选择器、八进制计数器、译码器、控制器等7个器件的功能。

2)用控制器实现控制整点报时，快速调小时、分钟，清零秒钟，分频功能。

4HZ脉冲信号经过控制器分频得到1HZ脉冲，512HZ和1024HZ脉冲控制蜂鸣器发出低频率和高频率声音3)秒钟由控制器分频的1HZ频率脉冲控制4)分钟正常情况下由秒钟的进位输出作为脉冲信号控制，在快速调整时间时由4HZ脉冲控制5)时钟同分钟一样。

6)八选一数据选择器接收时钟、分钟、秒钟传来的信号，经过一个S端控制选择输出一个数据传给译码器，选择一个设备上的8段数码管输出所选择的数据。

7)八进制计数器循环产生一个数传送给数据选择器的地址端，用以选择数据。

8)译码器接收数据选择器输出的一个数据进行八段数码管的相应显示分配。

9)总电路图10)管脚分配图四、源代码1.控制器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity control isport ( clk4hz ,clk1024hz,clk500hz,set_h,set_m,clr_s: in std_logic;second_h : in std_logic_vector(3 downto 0);second_l : in std_logic_vector(3 downto 0);minute_h : in std_logic_vector(3 downto 0);minute_l : in std_logic_vector(3 downto 0);bee,clk1hz,set_hh,set_mm,clr_ss: out std_logic);end control;architecture aa of control issignal count : std_logic_vector(1 downto 0);beginclk_label:PROCESS (clk4hz)BEGINIF clk4hz'event and clk4hz='1' THENcount<=count+1;END IF;END PROCESS clk_label;clk1024_label:PROCESS (clk1024hz)BEGINIF clk1024hz'event and clk1024hz='1' THENset_hh<=set_h;set_mm<=set_m;clr_ss<=clr_s;END IF;END PROCESS clk1024_label;clk1hz<=count(1);bee<= clk500hzwhen minute_h & minute_l="01011001" and second_h ="0101" and second_L(0)='0' else clk1024hzwhen minute_h & minute_l & second_h & second_l="0000000000000000"else '0';end aa;2.秒钟library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity second isport ( clk1hz,clr_ss :in std_logic;co : out std_logic;second_h :out std_logic_vector (3 downto 0);second_l :out std_logic_vector (3 downto 0));end second ;architecture aa of second issignal out1,out2 :integer range 0 to 9;signal out3,out4 :std_logic_vector (3 downto 0);beginprocess(clk1hz)beginif clr_ss='1' thenout1<=0; out2<=0;elsif clk1hz'event and clk1hz='1' thenif (out2=5) and (out1=9) thenout1<=0;out2<=0;co<='1';elseout1<=out1+1;co<='0';if out1=9 and out2/=5 thenout1<=0;out2<=out2+1;co<='0';end if;end if;end if;out3<= conv_std_logic_vector(out1,4);out4<= conv_std_logic_vector(out2,4);second_h <=out4;second_l <=out3;end process;end aa;3.分钟library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity minute isport ( clkin,clk4hz,set_mm :in std_logic;co : out std_logic;minute_h :out std_logic_vector (3 downto 0);minute_l :out std_logic_vector (3 downto 0)); end minute ;architecture aa of minute issignal out1,out2 :integer range 0 to 9;signal out3,out4 :std_logic_vector (3 downto 0);signal clk,cay:std_logic;beginco<= cay when set_mm ='0' else '0';clk<=clkin when set_mm ='0' else clk4hz;process(clk)beginif clk'event and clk='1' thenif (out2=5) and (out1=9) thenout1<=0;out2<=0;cay<='1';elseout1<=out1+1;cay<='0';if out1=9 and out2/=5 thenout1<=0;out2<=out2+1;cay<='0';end if;end if;end if;out3<= conv_std_logic_vector(out1,4);out4<= conv_std_logic_vector(out2,4);minute_h<=out4;minute_l<=out3;end process;end aa;4.时钟library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity hour24 isport ( clkin, clk4hz ,set_hh:in std_logic;co : out std_logic;hour_h :out std_logic_vector (3 downto 0);hour_l :out std_logic_vector (3 downto 0)); end hour24 ;architecture aa of hour24 issignal out1,out2 :integer range 0 to 9;signal out3,out4 :std_logic_vector (3 downto 0); signal clk ,cay:std_logic;beginco<=cay when set_hh='0' else '0';clk<=clkin when set_hh='0' else clk4hz;process(clk)beginif clk'event and clk='1' thenif (out2=2) and (out1=3) thenout1<=0;out2<=0;cay<='1';elseout1<=out1+1;cay<='0';if out1=9 thenout1<=0;out2<=out2+1;end if;end if;end if;out3<= conv_std_logic_vector(out1,4);out4<= conv_std_logic_vector(out2,4);hour_h<=out4;hour_l<=out3;end process;end aa;5.8选1数据选择器ENTITY mux81a ISPORT ( data0,data1,data2,data3,data4,data5,data6,data7: IN BIT_vector(3 DOWNTO 0);s: IN BIT_vector(2 DOWNTO 0);seg : OUT BIT_vector(3 DOWNTO 0);sel:OUT BIT_vector(7 DOWNTO 0) );END ENTITY mux81a;ARCHITECTURE one OF mux81a ISBEGINseg <= data0 when s="000" ELSEdata1 when s="001" ELSEdata2 when s="010" ELSEdata3 when s="011" ELSEdata4 when s="100" ELSEdata5 when s="101" ELSEdata6 when s="110" ELSEdata7 when s="111" ELSE"0000";sel <= "01111111" when s="000" ELSE"10111111" when s="001" ELSE"11011111" when s="010" ELSE"11101111" when s="011" ELSE"11110111" when s="100" ELSE"11111011" when s="101" ELSE"11111111" when s="110" ELSE"11111111" when s="111" ELSE"11111111";END ARCHITECTURE one ;6.八进制计数器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity cnt8 isport ( clk :in std_logic;cout :BUFFER std_logic_vector (2 downto 0)); end cnt8 ;architecture aa of cnt8 isbeginprocess(clk)beginif clk'event and clk='1' thencout<=cout+1;end if;end process;end aa;7.译码器ENTITY disp_decode ISPORT ( data: IN bit_vector(3 downto 0);seg:out bit_vector(7 downto 0));END disp_decode;ARCHITECTURE behav OF disp_decode ISBEGINd:process(data)begincase data iswhen "0000" => seg <= "00111111";--0when "0001" => seg <= "00000110";--1when "0010" => seg <= "01011011";--2when "0011" => seg <= "01001111";--3when "0100" => seg <= "01100110";--4when "0101" => seg <= "01101101";--5when "0110" => seg <= "01111101";--6when "0111" => seg <= "00000111";--7when "1000" => seg <= "01111111";--8when "1001" => seg <= "01101111";--9when "1010" => seg <= "10001000";--awhen "1011" => seg <= "10000011";--bwhen "1100" => seg <= "10100110";--cwhen "1101" => seg <= "10100001";--dwhen "1110" => seg <= "10000110";--ewhen "1111" => seg <= "10001110";--fend case;end process;END behav;五、程序调试心得体会1.系统仿真及调试情况1)在机房用工具箱调试时，遇到的第一个问题是显示错误，不能通过编译。