VHDL TestBench基础

作业
• 分析VHDL描述功能，并给以说明 • Байду номын сангаас采用TESTBENCH验证。 • 给出DATAFLOW流向图
LIBRARY IEEE; USE IEEE.STd_LOGIC_1164.ALL; ENTITY chk IS PORT(din:IN STd_LOGIC; clk,clr:IN STd_LOGIC; d:IN STd_LOGIC_VECTOR(7 dOWNTO 0); ab:OUT STd_LOGIC_VECTOR(3 dOWNTO 0)); ENd chk; ARCHITECTURE art OF chk IS SIGNAL q :INTEGER RANGE 0 TO 8; BEGIN PROCESS ( clk,clr ) BEGIN IF clr= '1' THEN q<=0; ELSIF clk'EVENT ANd clk= '1' THEN CASE q IS WHEN 0 => IF din =d(7) THEN q<= 1 ;ELSE q<=0;ENd IF; WHEN 1 => IF din =d(6) THEN q<= 2 ;ELSE q<=0;ENd IF; WHEN 2 => IF din =d(5) THEN q<= 3 ;ELSE q<=0;ENd IF; WHEN 3 => IF din =d(4) THEN q<= 4;ELSE q<=0; ENd IF; WHEN 4 => IF din =d(3) THEN q<= 5 ;ELSE q<=0;ENd IF; WHEN 5 => IF din =d(2) THEN q<= 6 ;ELSE q<=0;ENd IF; WHEN 6 => IF din =d(1) THEN q<= 7 ;ELSE q<=0;ENd IF; WHEN 7 => IF din =d(0) THEN q<= 8 ;ELSE q<=0;ENd IF;
VHDL TestBench基础
TestBench的主要目标
• 实例化DUT-Design Under Test • 为DUT产生激励波形 • 产生参考输出，并将DUT的输出与参考输出进行 比较 • 提供测试通过或失败的指示 • TestBench产生激励的三种方式： • 直接在testbench中产生 • 从矢量中读入 • 从单独的激励文件中读入
源程序：试分析功能，并采用TESTBENCH验证 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; ENTITY exam IS PORT(clk,rst_n:IN STD_LOGIC; a,b:IN UNSIGNED (2 DOWNTO 0); y:OUT UNSIGNED (3 DOWNTO 0)); END exam; ARCHITECTURE archi OF exam IS BEGIN PROCESS(clk,rst_n) BEGIN IF (rst_n='0') THEN Y<=(OTHERS =>'0'); ELSIF (clk'EVENT AND clk='1') THEN Y<=('0' & a) +('0' & b); END IF; END PROCESS; END archi;
WHEN S3=>outa<="1101";IF ina="001" THEN ps<=S3; ELSE ps<=S0; END IF; WHEN OTHERS=>ps<=S0; END CASE; END IF; END PROCESS; END one;
• 比较流行的做法是使用matlab产生激励文 件，由testbench读入该激励文件并将激励 馈送到DUT，DUT产生的相应输出以文件 的形式存储，由matlab读取并与理想的响 应作比较。
• 下面以一个简单的同步加法器为例，分析 不同形式的testbench的写法。 • 简单的testbench只适合于相对比较简单的 设计。如图1-1所示，在testbench中只是简 单的实例化了一个DUT，激励在testbench 中产生。可见这种方式的testbench可重用 性比较差。
具有独立激励源的TESTBENCH
• 将激励源作为一个文件在testbench中进行实例化， 比较适合于具有复杂输入和简单输出的设计 • 当设计的输入输出都比较复杂时，尤其是在做复 杂的算法仿真时，需要产生多种形式的激励输入， 还要对仿真结果输出做复杂的分析时，使用 TextIO的testbench具有最高的效率。在使用 TextIO的testbench中，为DUT从输入文件读取激 励输入，激励信号经过DUT处理后写入到输出文 件中。其原理如下图所示。
简单的TESTBENCH代码
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; ENTITY tb IS END tb; ARCHITECTURE stimu OF tb IS COMPONENT exam IS PORT(clk,rst_n:IN STD_LOGIC; a,b:IN UNSIGNED (2 DOWNTO 0); y:OUT UNSIGNED (3 DOWNTO 0)); END COMPONENT; CONSTANT period:time:=50 ns; SIGNAL clk:STD_LOGIC:='0'; SIGNAL rst_n:STD_LOGIC; SIGNAL a,b:UNSIGNED (2 DOWNTO 0); SIGNAL y: UNSIGNED (3 DOWNTO 0); BEGIN clk<=NOT clk AFTER period/2;
简单的TESTBENCH代码
rst_n<='0' ,'1' AFTER 20 ns,'0' AFTER 400 ns,'1' AFTER 420 ns; a<="000", "001" AFTER 100 ns, "010" AFTER 200 ns, "011" AFTER 250 ns, "101" AFTER 300 ns; b<="000", "001" AFTER 100 ns, "010" AFTER 200 ns, "011" AFTER 250 ns, "101" AFTER 300 ns; U0: exam PORT MAP(clk,rst_n,a,b,y); END stimu;
WHEN OTHERS => q<=0; END CASE; END IF; END PROCESS; PROCESS(q) BEGIN IF q= 8 THEN ab<= "1010"; ELSE ab<= "1011"; END IF ; ENd PROCESS; ENd art;
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY fsm IS PORT(clk,reset:IN STD_LOGIC; ina:IN STD_LOGIC_VECTOR(2 DOWNTO 0); outa:OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); END fsm; ARCHITECTURE one OF fsm IS TYPE STATES IS (S0,S1,S2,S3); SIGNAL ps:STATES; BEGIN PROCESS(clk,reset,ps) BEGIN IF reset='1' THEN ps<=S0; ELSIF RISING_EDGE(clk) THEN CASE ps IS WHEN S0=>outa<="0010";IF ina="101" THEN ps<=S1; ELSE ps<=S0; END IF;