LTCC射频模块设计(HFSS)

LTCC Considerations
-Conductors

Line width and spacing
-The minimum conductor line width shall be 200µm(A) -Maximum line width is 1.5mm with unlimited length. -The use of 90o lines is recommended for the optimum line width control. But 45o lines are allowed -The minimum conductors spacing shall be 200µm(B) -The minimum conductor line spacing to a via catch pad shall be 175 µm(C) -The minimum conductor line clearance to the substrate edge shall be 380 µm(D). Lead frame pad clearance to the substrate edge shall be 125 µm -The minimum SMD pad spacing to a via catch pad shall be 200 µm(F) -The minimum SMD pad spacing to a conductor line shall be 200 µm -The minimum SMD pad spacing to substrate edge shall be 500 µm(G)
LTCC Background

What is LTCC ?
- LTCC is a Process Technology which allows RF engineers to create Passive components in the LTCC substrate

LTCC(Low Temperature Ceramic Cofired)

LTCC Considerations
-Vias

Stacked vias
-Stacking of vias is acceptable through any number of layers. -A stacked via connection results in a bump on the part surface. Staggering of vias is recommended ro avoid this. -A minimum of one layer of via stagger is recommended for hermeticity.
LTCC Manufacturing process
Package Styles


Castellated
-Most recent development -Best RF performance -Lowest cost

Clip lead
-Backward Clip lead -Backward compatible -Good mechanical strength -Medium cost



Thermal vias
-Recommended thermal via diameter is 200µm for tape materials 951-A2 and 951-AX and 150µm for 951-AT -The minimum via pitch (center to center) in a thermal via shall be 3 x via diameter -The maximum thermal via array size is 6.5mm length and width -The minimum thermal via array to part edge clearance shall be 4mm
A
LTCC Considerations
-Cavities

Cavities
-Cavities or holes are produced in the unfired state by punching the cavity windows to the tape sheets before lamination. -The cavity walls shall be a minimum of 3.0 mm wide(B) -Via edge to cavity wall clearance shall be a minimum of 2.5 x via diameter(C) -The cavity bottom conductor to cavity wall clearance shall be 200µm (D) -Buried or exposed conductor to cavity wall clearance shall be a minimum of 250 µm(E) -Bond shelf minimum width shall be 0.8 mm(F)


LTCC Considerations
-Ground and power planes



-GrouLeabharlann d and power planes shall be a grid pattern of less than 50% conductor coverage. -The preferred plane uses 250µm lines and 550 µm spaces. -The grid pattern of planes on adjacent layers should be offset to provide a uniform substrate thickness. -Solid conductor areas on the gridded plane can be used locally to improve RF performance -The grid plane connection to a via can be improved by using a square catch pad that shares the current flow to several grid lines(A) -A minimum of 300 µm spacing shall separate the plane pattern and ant feed through via. 550µm 250µm 300µm
LTCC Considerations


Via sizes
-Vias-
-Via sizes are 150µm, 200µm and 250µm, as punched to the unfired tape. -Via diameter is recommended to be close to the rape thickness. -One via diameter on any tape layer recommended.
-Silver and Gold metal alloys are printed onto selected layers of the substrate -Each layer is a ceramic composite with very stable dielectric properties -Compliments silicon integration with embedded passives -Ceramic technology circuit elements such as capacitors resistors & inductors -Low-Temperature process allows for the use of highly conductive metals(AG,AU)
F D B E



A
C
Challenges in LTCC RF Module design

RF characterization data is not readily available For large embedded components(spiral inductor and parallel plate capacitors), considerable electrical modeling required. - coupling with ground and amongst components Integrated simulation between Circuit modeling and passive components realization required - L : length of unconventional line and via , C : area of arbitrary shape of plates - May use coupling amongst components to realize circuit components ("intentional" parasitic)


BGA
-Standard footprint -Good mechanical strength -Medium cost
LTCC Materials
Substrate & Package
Company Dupont Ferro Heraeus Kyocera Dielectric constant 7.8 7.5 5.9 5.9 7.68 9.15 5.6~5.7 9.4~9.5 Tangent δ 0.0063 0.002 0.0012 0.0039 0.0027 Model 951 943 A6M A6S CT800 CT2000 GL550 GL660