用VerilogHDL编写四路抢答器
合集下载
相关主题
- 1、下载文档前请自行甄别文档内容的完整性，平台不提供额外的编辑、内容补充、找答案等附加服务。
- 2、"仅部分预览"的文档,不可在线预览部分如存在完整性等问题,可反馈申请退款(可完整预览的文档不适用该条件!)。
- 3、如文档侵犯您的权益，请联系客服反馈,我们会尽快为您处理(人工客服工作时间：9:00-18:30)。
input wire [3:0]qiang_da; reg [2:0]bian_ma; wire suo; input wire qing_ling; input wire fankui; output reg [2:0]bian_ma_cun; output wire suo_1;
always@(*) begin case(qiang_da) 1:bian_ma=3'b001; 2:bian_ma=3'b010; 4:bian_ma=3'b011; 8:bian_ma=3'b100; default:bian_ma=3'b000; endcase end
assign suo=(~bian_ma_cun[0])&(~bian_ma_cun[1])&(~bian_ma_cun [2]);
assign suo_1=suo&fankui;
always@(*) begin if(qing_ling==1) bian_ma_cun<=3'b000; else if(suo_1==0) bian_ma_cun<=bian_ቤተ መጻሕፍቲ ባይዱa_cun; else bian_ma_cun<=bian_ma; end
output wire [6:0]a_to_g; output wire [3:0]A_TO_D; input wire clk;//50MHz时钟 wire [3:0]qian; wire [3:0]bai; wire [2:0]shi; wire [2:0]ge; wire cp;//1s时钟 input wire [3:0]qiang_da; input button; wire suo_1; wire [2:0]bian_ma_cun; wire fankui; output wire xuan; shumaguan shumaguan0(a_to_g,A_TO_D,clk,qian,bai,shi,ge); cp_1s cp_1s0(clk,cp); xuan_shou xuan_shou0(qiang_da,button,suo_1,bian_ma_cun,fankui); wei_xuan wei_xuan0(bian_ma_cun,xuan,shi,ge); fuwei_kongzhi fuwei_kongzhi0(button,xuan); jishu_kongzhi jishu_kongzhi0(bai,qian,cp,suo_1,xuan,fankui); endmodule
endcase
always@(*)//4位位选译码 case(wei) 3:begin A_TO_D=4'b1110; duan=qian; end 2:begin A_TO_D=4'b1101; duan=bai; end 1:begin A_TO_D=4'b1011; duan=shi; end 0:begin A_TO_D=4'b0111; duan=ge; end default:A_TO_D=4'b1110; endcase
if(q==49999) begin q<=0; a<=~a; end else q<=q+1; end
always@(*)//7位段译码 case(duan) 0:a_to_g=7'b0000001; 1:a_to_g=7'b1001111; 2:a_to_g=7'b0010010; 3:a_to_g=7'b0000110; 4:a_to_g=7'b1001100; 5:a_to_g=7'b0100100; 6:a_to_g=7'b0100000; 7:a_to_g=7'b0001111; 8:a_to_g=7'b0000000; 9:a_to_g=7'b0000100; default:a_to_g=7'b0000001;
endmodule
module wei_xuan(bian_ma_cun,xuan,bai,ge);//控制选手是否提前抢答模块 input wire [2:0]bian_ma_cun; input wire xuan; output reg [2:0]bai; output reg [2:0]ge; always@(*) begin case(xuan) 0: begin bai=bian_ma_cun; ge=3'b000; end 1: begin bai=3'b000; ge=bian_ma_cun; end default: begin bai=3'b000; ge=3'b000; end endcase end endmodule
begin if(q==24999999) begin q<=0; a<=~a; end else q<=q+1; end endmodule
module xuan_shou(qiang_da,qing_ling,suo_1,bian_ma_cun,fankui);//选手抢答模块， 某选手抢答后结果锁存
always@(posedge a)//四个状态循环 if(wei==3) wei<=0; else wei<=wei+1;
endmodule
module cp_1s(clk,a); //提供1秒脉冲 input wire clk; output reg a; reg [25:0]q; always@(posedge clk)
四路抢答器设计
——Verilog HDL语言
抢答器为四路，20秒倒计时，抢 到后显示锁定，计时停止，若 提前抢答会在另外数码管显示 抢答号码。
在BASYS 2 开发板上可以实现
module qiang_da_qi(a_to_g,A_TO_D,clk,qiang_da,button,xuan );
module shumaguan(a_to_g,A_TO_D,clk,qian,bai,shi,ge);//数码管驱动 output reg [6:0]a_to_g; output reg [3:0]A_TO_D; input wire clk; input wire [3:0]qian; input wire [3:0]bai; input wire [2:0]shi; input wire [2:0]ge; reg [3:0]duan; reg [1:0]wei; reg a; reg [16:0]q; always@(posedge clk) begin
always@(*) begin case(qiang_da) 1:bian_ma=3'b001; 2:bian_ma=3'b010; 4:bian_ma=3'b011; 8:bian_ma=3'b100; default:bian_ma=3'b000; endcase end
assign suo=(~bian_ma_cun[0])&(~bian_ma_cun[1])&(~bian_ma_cun [2]);
assign suo_1=suo&fankui;
always@(*) begin if(qing_ling==1) bian_ma_cun<=3'b000; else if(suo_1==0) bian_ma_cun<=bian_ቤተ መጻሕፍቲ ባይዱa_cun; else bian_ma_cun<=bian_ma; end
output wire [6:0]a_to_g; output wire [3:0]A_TO_D; input wire clk;//50MHz时钟 wire [3:0]qian; wire [3:0]bai; wire [2:0]shi; wire [2:0]ge; wire cp;//1s时钟 input wire [3:0]qiang_da; input button; wire suo_1; wire [2:0]bian_ma_cun; wire fankui; output wire xuan; shumaguan shumaguan0(a_to_g,A_TO_D,clk,qian,bai,shi,ge); cp_1s cp_1s0(clk,cp); xuan_shou xuan_shou0(qiang_da,button,suo_1,bian_ma_cun,fankui); wei_xuan wei_xuan0(bian_ma_cun,xuan,shi,ge); fuwei_kongzhi fuwei_kongzhi0(button,xuan); jishu_kongzhi jishu_kongzhi0(bai,qian,cp,suo_1,xuan,fankui); endmodule
endcase
always@(*)//4位位选译码 case(wei) 3:begin A_TO_D=4'b1110; duan=qian; end 2:begin A_TO_D=4'b1101; duan=bai; end 1:begin A_TO_D=4'b1011; duan=shi; end 0:begin A_TO_D=4'b0111; duan=ge; end default:A_TO_D=4'b1110; endcase
if(q==49999) begin q<=0; a<=~a; end else q<=q+1; end
always@(*)//7位段译码 case(duan) 0:a_to_g=7'b0000001; 1:a_to_g=7'b1001111; 2:a_to_g=7'b0010010; 3:a_to_g=7'b0000110; 4:a_to_g=7'b1001100; 5:a_to_g=7'b0100100; 6:a_to_g=7'b0100000; 7:a_to_g=7'b0001111; 8:a_to_g=7'b0000000; 9:a_to_g=7'b0000100; default:a_to_g=7'b0000001;
endmodule
module wei_xuan(bian_ma_cun,xuan,bai,ge);//控制选手是否提前抢答模块 input wire [2:0]bian_ma_cun; input wire xuan; output reg [2:0]bai; output reg [2:0]ge; always@(*) begin case(xuan) 0: begin bai=bian_ma_cun; ge=3'b000; end 1: begin bai=3'b000; ge=bian_ma_cun; end default: begin bai=3'b000; ge=3'b000; end endcase end endmodule
begin if(q==24999999) begin q<=0; a<=~a; end else q<=q+1; end endmodule
module xuan_shou(qiang_da,qing_ling,suo_1,bian_ma_cun,fankui);//选手抢答模块， 某选手抢答后结果锁存
always@(posedge a)//四个状态循环 if(wei==3) wei<=0; else wei<=wei+1;
endmodule
module cp_1s(clk,a); //提供1秒脉冲 input wire clk; output reg a; reg [25:0]q; always@(posedge clk)
四路抢答器设计
——Verilog HDL语言
抢答器为四路，20秒倒计时，抢 到后显示锁定，计时停止，若 提前抢答会在另外数码管显示 抢答号码。
在BASYS 2 开发板上可以实现
module qiang_da_qi(a_to_g,A_TO_D,clk,qiang_da,button,xuan );
module shumaguan(a_to_g,A_TO_D,clk,qian,bai,shi,ge);//数码管驱动 output reg [6:0]a_to_g; output reg [3:0]A_TO_D; input wire clk; input wire [3:0]qian; input wire [3:0]bai; input wire [2:0]shi; input wire [2:0]ge; reg [3:0]duan; reg [1:0]wei; reg a; reg [16:0]q; always@(posedge clk) begin