基于VHDL的分频器设计【毕业作品】

BI YE SHE JI

( 届)

基于VHDL的分频器设计

(英文) Design of Divider Based on VHDL

所在学院电子信息学院

专业班级电子信息工程

学生姓名学号

指导教师职称

完成日期年月日

摘要

在数字逻辑电路设计中，分频器是一种基本电路。通常用来对某个给定频率进行分频，以得到所需的频率。基于FPGA实现的分频器可以实现在线修改,设计周期短。VHDL是一种典型的硬件描述语言,具有很强的电路行为描述、系统描述能力。基于VHDL的分频器作为一个模块,具有较强的可移植性。

论文实现了以下几种分频器。1）等占空比/可控占空比整数分频。等占控比整数分频的核心思想是利用一个模N计数器。当计数值为N/2-1时，使输出信号发生翻转。可控占空比整数分频的设计思想是引入可预置初值的计数器，控制该计数器的高低电平输出比例，从而实现对占空比的调节。3）任意小数分频。在此实现了两种不同的实现方案。方法一的基本原理是采用脉冲吞吐计数器和锁相环技术设计两个不同分频比的整数分频器，通过控制单位时间内两种分频比出现的不同次数来获得所需要的小数分频值。方法二为通过可变分频和多次平均的方法实现。4）改进的小数分频。目前广泛采用的小数分频方法是双模前置方式，双模的模值均采用整数。此方法实现的分频器抖动性能较差，误差较大。论文提出一种改进的小数分频设计方案，将两个整数分频器由一个整数分频器和一个半整数分频器代替，以克服上述缺点。

论文先对现状进行了概述，阐明了分频器在数字信号处理中的重要地位；然后对于分频器的理论知识如分类、优缺点和原理进行了分析，详细阐述了上述分频器的实现原理、设计思想。再对每一种分频进行实现，给出了VHDL源代码和必要的行为级仿真波形。最后，利用ALTERA公司的DE II平台，将整个系统下载至目标板EP2C35F672C6N，锁定相关引脚，用示波器观察输出波形。最终验证了设计的正确性。

关键词：分频器，FPGA，VHDL，占空比，改进小数分频

Abstract

The divider is a basic circuit in the design of digital logic circuit. It used to divide on a given frequency in order to obtain the desired frequency. The divider based on FPGA can realize the on-line modification and the short of design cycle. The VHDL has the very strong circuit behavior description, description of the hierarchical system ability and program structure. Based on VHDL, the divider as a module has strong portability.

Paper achieved the following several divider.1) The equal duty cycle / the controllable duty cycle integer frequency. The core idea of the equal duty cycle integer frequency is to use a module N counter. When the count value for N/2-1 , the output signal occurs rollover. The controllable duty cycle integer divider design idea leads into a counter of the frequency preset initial value , controlling the counter of high and low level output ratio, so as to realize the duty cycle to be adjusted. 3) The any fractional frequency. Two different schemes can be achieved in this point. The basic principle of method 1 is taking the pulse-throughput counters and the PLL to design two integer divider of different divide ratio, through controlling the emergence of the number of two different divide ratio in the unit of time to gain needed decimal frequency value.The methods 2 achieved through the variable frequency and many times the average method.4) The improved fractional divider. At present fractional frequency is widely used dual mod front way, and the dual mode of modulus is using an integer. The divider achieved by this method is poor in jitter performance, and the error is larger. This paper puts forward an improved design of fractional frequency taking place two integer dividers of a integer frequency divider and a half-integer frequency divider, in order to overcome these shortcomings.

The paper first has an overview of the status quo, and clarifies the important position of the divider in digital signal processing. And the paper analyses the theory knowledge of the divider, such as classification, advantages, disadvantages and principle, and elaborated on the divider Principles of design ideas. Then the