第3章组合逻辑电路设计

• Implementing Combinational Functions with Decoders
– Encoding using Encoders – Selecting using Multiplexers
• Implementing Combinational Functions with Multiplexers
Chapter 3 - Part 1 13
Hierarchy for Parity Tree Example
X X X X X X X X X
0 1 2 3 4 5 6 7 8
9-Input odd function
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O
X X X X X X X X X
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A A A A
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(a) Symbol for circuit
第3章 组合逻辑电路设计（续）
习题
完成下列练习, 其中标为红色的要用Multisim完成: 52, 54, 55, 56, 58, 62. （第5章）3, 4, 5, 28, 29, 30.
2018/10/10
1
Overview
• Part 1 – Design Procedure
– Steps
Apply 2-level and multiple-level optimization Draw a logic diagram or provide a netlist for the resulting circuit using ANDs, ORs, and inverters
3. Optimization
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Chapter 3 - Part 1 9
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Design Example (continued)
3. Optimization (continued)
b. Multiple-level using transformations
W = AB + BC B + BD C D X= C+ D DB C+ Y = CD D+ Z=
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Chapter 3 - Part 1 12
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Beginning Hierarchical Design
• To control the complexity of the function mapping inputs to outputs:
– Decompose the function into smaller pieces called blocks – Decompose each block’s function into smaller blocks, repeating as necessary until all blocks are small enough – Any block not decomposed is called a primitive block – The collection of all blocks including the decomposed ones is a hierarchy
• A block diagram:
Combinatorial Logic Circuit
Chapter 3 - Part 1 4
m Boolean Inputs
n Boolean Outputs
Design Procedure
1. Specification
– Write a specification for the circuit if one is not already available
• Example: 9-input parity tree (see next slide)
– – – – – Top Level: 9 inputs, one output 2nd Level: Four 3-bit odd parity trees in two levels 3rd Level: Two 2-bit exclusive-OR functions Primitives: Four 2-input NAND gates Design requires 4 X 2 X 4 = 32 2-input NAND gates
• • • • Specification Formulation Optimization Technology Mapping
– Beginning Hierarchical Design – Technology Mapping - AND, OR, and NOT to NAND or NOR – Verification
11
Design Example (continued)
4. Technology Mapping
–
A
Mapping with a library containing inverters and 2-input NAND, 2-input NOR, and 2-2 AOI gates
A W W
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G = 7 + 10 + 6 + 0 = 23
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Perform extraction, finding factor:
T1 = C + D W = AB + BT1 C D X = T1 + BC D Y = CD D+ Chapter 3 - Part 1 Z=
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G = 2 + 1 + 4 + 7 + 6 + 0 = 19
1001 1011
–
–
Chapter 3 - Part 1 8
Design Example (continued)
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3. Optimization
a. 2-level using K-maps
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(c) 3-input odd function circuit as interconnected exclusive-OR blocks
Chapter 3 - Part 1 14
(d) Exclusive-OR block as interconnected NANDs
Reusable Functions
Chapter 3 - Part 1 3
Combinational Circuits
• A combinational logic circuit has:
– A set of m Boolean inputs, – A set of n Boolean outputs, and – n switching functions, each mapping the 2m input combinations to an output such that the current output depends only on the current input values
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W = AB + BC B + BD CD X= C+ D +B CD Y = CD + D x Z=
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• multiple-level circuit • NAND gates (including inverters) Chapter 3 - Part 1
7
Design Example (continued)
2. Formulation
– – Conversion of 4-bit codes can be most easily formulated by a truth table Variables Input BCD Output Excess-3 - BCD: ABCD WXYZ A,B,C,D 0000 0011 0001 0100 Variables 0010 0101 - Excess-3 0011 0110 W,X,Y,Z 0100 0111 0101 1000 Don’t Cares 0110 1001 - BCD 1010 0111 1010 to 1111 1000 1011
• Manual • Simulation
Chapter 3 - Part 1 2
Overview (continued)
• Part 2 – Combinational Logic
– Functions and functional blocks – Rudimentary logic functions – Decoding using Decoders
• Whenever possible, we try to decompose a complex design into common, reusable function blocks • These blocks are
Design Example (continued)
3. Optimization (continued)
b. Multiple-level using transformations T1 = C + D W = A + BT1 X = B T1 + B C D Y = CD + C D Z =D G = 19 – An additional extraction not shown in the text since it uses a CD T1 D = ): Boolean transformation: ( =C+ W = A + BT1 X = B T1 + B T1 Y = CD + T1 Z1 = D G = 2 +1 + 4 + 6 + 4 + 0 = 16! Chapter 3 - Part
3-Input odd function
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A A A A
3-Input odd function
A B
OFra Baidu bibliotek
0 1 2
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3-Input odd function
B
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6 7 8
0 1 2
3-Input odd function
B
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(b) Circuit as interconnected 3-input odd function blocks A A A
Chapter 3 - Part 1 5
Design Procedure
4. Technology Mapping
– Map the logic diagram or netlist to the implementation technology selected Verify the correctness of the final design manually or using simulation
5. Verification
–
Chapter 3 - Part 1 6
Design Example
1. Specification
– BCD to Excess-3 code converter – Transforms BCD code for the decimal digits to Excess-3 code for the decimal digits – BCD code words for digits 0 through 9: 4-bit patterns 0000 to 1001, respectively – Excess-3 code words for digits 0 through 9: 4-bit patterns consisting of 3 (binary 0011) added to each BCD code word – Implementation:
2. Formulation
–
– – –
Derive a truth table or initial Boolean equations that define the required relationships between the inputs and outputs, if not in the specification Apply hierarchical design if appropriate