对外 意法半导体 Co-packaged Optics-WJ-0809 - REVIEWED

From Optical Transceivers to

Co-package Optics with ASIC

CIOE, September 2018

Silicon Photonics Engine

for Scale Deployment

•Volume capacity and low cost from the start

•Optical passive and active devices integrated on silicon

•Optical process control and wafer automatic testing for high yields •TRX electrical optical Integration without complex sub-assemblies •

Electro-optical chip automated test

Electrical die assemble on Silicon Photonics

wafers

Optical devices integrated in

Silicon Ge p +

n +

Waveguide optical splitter

Grating couplers

High Speed PD

Carrier Depletion Based High Speed phase modulator

3D chips on wafers testing

2

Fiber Assembly Options

•Bent fiber array

•8-12 fibers

•Low bending radius fiber used

•Low profile, compatible with

QSFP and on-board module

mechanics

•Fiber with MT ferrule or direct

ferrule versions

•Standard fiber assembly

•12-16 fibers (8 for TRX I/Os plus

alignment loops and CW laser in

=> PM fiber)

•Fiber block polished at 8 deg

•+/-1um position accuracy

•Ideal for prototyping

•PLC

•Metalized mirror on 41

deg polished surface

•Low profile

•Fan-out and WDM

features possible

•Standard fiber block glued

to PLC

3

“No Package” and Low Cost PCB •To complete the Silicon Photonics engine

•Fiber attachment

•CW Laser in micro-package attachment

•Assembled with biasing from electrical probes and active alignment monitoring Tx output •No ‘package’ for the 3D engine, directly chip on board with wire-bonding

•Low cost 4 layer-layout, cut out in the board for top and bottom heat dissipation

4

Silicon Photonics Engine

Next Level of Integration •Electro-optical TRX from 5Gbps/mm2 to 16Gbps/mm2: 3x density

•More dense electrical driver and more efficient optical modulator

•TSV on silicon photonics process for compact board assembly

•External laser in case of on board optics or co-packaged optics 5

80mm2 4x100G

200mm2 32x100G

Co-package ASIC

with Silicon Photonics Engine

•ASIC IC and a 3D stack Silicon Photonics engine on the same interposer •I/O Energy-bandwidth optimization: ASIC IC directly couple with Photonics die via a very short electrical interface

•112Gbps PAM4 USR ( <10mm, <3dB@28Ghz) serdes for MCM communication or parallel chip to chip interfaces

•Eliminating power hungry CDR or expensive Gearbox of the pluggable Optical module •TSV on Silicon Photonics process for a better signal integrity 6

ASIC

OIC

EIC

Co-Package Optics