Variables, Attributes, Functions and Procedures

ECE 545 – Introduction to VHDL
10
Parity generator architecture using variables
ARCHITECTURE behavioral OF oddParityLoop IS BEGIN PROCESS (ad) VARIABLE loopXor: STD_LOGIC; BEGIN loopXor := '0'; FOR i IN 0 to width -1 LOOP loopXor := loopXor XOR ad( i ) ; END LOOP ; oddParity <= loopXor ; END PROCESS; END behavioral ;
ECE 545 – Introduction to VHDL 2
Variables
ECE 545 – Introduction to VHDL
3
Variable – Example (1)
LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY Numbits IS PORT ( X Count END Numbits ;
ECE 545 – Introduction to VHDL
13
N-bit NAND architecture using variables
ARCHITECTURE behavioபைடு நூலகம்al1 OF NANDn IS BEGIN PROCESS (X) VARIABLE Tmp: STD_LOGIC; BEGIN Tmp := X(1); AND_bits: FOR i IN 2 TO n LOOP Tmp := Tmp AND X( i ) ; END LOOP AND_bits ; Y <= NOT Tmp ; END PROCESS; END behavioral1 ;
ECE 545 – Introduction to VHDL 15
Correct N-bit NAND architecture using signals
ARCHITECTURE dataflow1 OF NANDn IS SIGNAL Tmp: STD_LOGIC_VECTOR(1 TO n); BEGIN Tmp(1) <= X(1); AND_bits: FOR i IN 2 TO n GENERATE Tmp(i) <= Tmp(i-1) AND X( i ) ; END LOOP AND_bits ; Y <= NOT Tmp(n) ; END dataflow1 ;
ECE 545 – Introduction to VHDL 19
One-dimensional arrays – Examples (2)
type controller_state is (initial, idle, active, error); type state_counts_imp is array(idle to error) of natural; type state_counts_exp is array(controller_state range idle to error) of natural; type state_counts_full is array(controller_state) of natural; ….. variable counters: state_counts_exp; ….. counters(active) := 0; ….. counters(active) := counters(active) + 1;
ECE 545 – Introduction to VHDL
12
N-bit NAND
library ieee; use ieee.std_logic_1164.all; ENTITY NANDn IS GENERIC (n: INTEGER := 4) PORT ( X : IN STD_LOGIC_VECTOR(1 TO n); Y : OUT STD_LOGIC); END NANDn;
ECE 545 Lecture 10 Variables, Attributes, Functions and Procedures
ECE 545 – Introduction to VHDL
George Mason University
Resources
• Volnei A. Pedroni, Circuit Design with VHDL Chapter 7, Signals and Variables Chapter 11, Functions and Procedures
ECE 545 – Introduction to VHDL
17
Constrained Array Types
ECE 545 – Introduction to VHDL
18
One-dimensional arrays – Examples (1)
type word_asc is array(0 to 31) of std_logic; type word_desc is array(31 downto 0) of std_logic; ….. signal buffer_register: word_desc; ….. buffer_register(6) <= ‘1’; ….. variable tmp : word_asc; ….. tmp(5):= ‘0’;
• Sundar Rajan, Essential VHDL: RTL Synthesis
Done Right Chapter 11, Scalable and Parameterizable Design Chapter 12, Enhancing Design Readability and Reuse
ECE 545 – Introduction to VHDL
5
Variables - features
• Can only be declared within processes and subprograms (functions & procedures) • Initial value can be explicitly specified in the declaration • When assigned take an assigned value immediately • Variable assignments represent the desired behavior, not the structure of the circuit • Should be avoided, or at least used with caution in a synthesizable code
ECE 545 – Introduction to VHDL 6
Variables vs. Signals
ECE 545 – Introduction to VHDL
7
Variable – Example
ARCHITECTURE Behavior OF Numbits IS BEGIN PROCESS(X) – count the number of bits in X equal to 1 VARIABLE Tmp: INTEGER; BEGIN Tmp := 0; FOR i IN 1 TO 3 LOOP IF X(i) = ‘1’ THEN Tmp := Tmp + 1; END IF; END LOOP; Count <= Tmp; END PROCESS; END Behavior ;
ECE 545 – Introduction to VHDL
8
Incorrect Code using Signals
ARCHITECTURE Behavior OF Numbits IS SIGNAL Tmp BEGIN PROCESS(X) – count the number of bits in X equal to 1 BEGIN Tmp <= 0; FOR i IN 1 TO 3 LOOP IF X(i) = ‘1’ THEN Tmp <= Tmp + 1; END IF; END LOOP; Count <= Tmp; END PROCESS; END Behavior ;
ECE 545 – Introduction to VHDL 14
Incorrect N-bit NAND architecture using signals
ARCHITECTURE behavioral2 OF NANDn IS SIGNAL Tmp: STD_LOGIC; BEGIN PROCESS (X) BEGIN Tmp <= X(1); AND_bits: FOR i IN 2 TO n LOOP Tmp <= Tmp AND X( i ) ; END LOOP AND_bits ; Y <= NOT Tmp ; END PROCESS; END behavioral2 ;
ECE 545 – Introduction to VHDL 11
Parity generator architecture using signals
ARCHITECTURE dataflow OF oddParityGen IS SIGNAL genXor: STD_LOGIC_VECTOR(width DOWNTO 0); BEGIN genXor(0) <= '0'; parTree: FOR i IN 1 TO width GENERATE genXor(i) <= genXor(i - 1) XOR ad(i - 1); END GENERATE; oddParity <= genXor(width) ; END dataflow ;