CY7C1061BV33-10ZC中文资料
中秀3000资料
CY7C1012AV33-10BGC中文资料
512K x 24 Static RAMCY7C1012AV33Features•High speed—t AA = 8, 10, 12 ns •Low active power —1080 mW (max.)•Operating voltages of 3.3 ± 0.3V •2.0V data retention•Automatic power-down when deselected •TTL-compatible inputs and outputs•Easy memory expansion with CE 0, CE 1 and CE 2 featuresFunctional DescriptionThe CY7C1012AV33 is a high-performance CMOS static RAM organized as 512K words by 24 bits. Each data byte is separately controlled by the individual chip selects (CE 0, CE 1,CE 2). CE 0 controls the data on the I/O 0–I/O 7, while CE 1controls the data on I/O 8–I/O 15, and CE 2 controls the data on the data pins I/O 16–I/O 23. This device has an automatic power-down feature that significantly reduces power consumption when deselected.Writing the data bytes into the SRAM is accomplished when the chip select controlling that byte is LOW and the write enable input (WE) input is LOW. Data on the respective input/output (I/O) pins is then written into the location specified on the address pins (A 0–A 18). Asserting all of the chip selects LOW and write enable LOW will write all 24 bits of data into the SRAM. Output enable (OE) is ignored while in WRITE mode.Data bytes can also be individually read from the device.Reading a byte is accomplished when the chip select controlling that byte is LOW and write enable (WE) HIGH while output enable (OE) remains LOW. Under these conditions, the contents of the memory location specified on the address pins will appear on the specified data input/output (I/O) pins.Asserting all the chip selects LOW will read all 24 bits of data from the SRAM.The 24 I/O pins (I/O 0–I/O 23) are placed in a high-impedance state when all the chip selects are HIGH or when the output enable (OE) is HIGH during a READ mode. For further details,refer to the truth table of this data sheet.The CY7C1012AV33 is available in a standard 119-ball BGA.Selection Guide–8–10–12Unit Maximum Access Time81012ns Maximum Operating Current Commercial 300275260mA Industrial300275260Maximum CMOS Standby CurrentCommercial/Industrial505050mAFunctional Block Diagram1516A 1A 2A 3A 4A 5A 6A 7A 8COLUMN DECODERR O W D E C O D E RS E N S E A M P SINPUT BUFFER512K x 24ARRAY A 0A 12A 14A 13A A A 17A 18A 10A 114096 x 4096I/O 0–I/O 7OEI/O 8–I/O 15CE 0, CE 1, CE 2WE A 9I/O 16–I/O 23CONTROL LOGICPin Configurations119 BGATop View1234567A NC A A A A A NCB NC A A CE0A A NCC I/O12NC CE1NC CE2NC I/O0D I/O13V DD V SS V SS V SS V DD I/O1E I/O14V SS V DD V SS V DD V SS I/O2F I/O15V DD V SS V SS V SS V DD I/O3G I/O16V SS V DD V SS V DD V SS I/O4H I/O17V DD V SS V SS V SS V DD I/O5J NC V SS V DD V SS V DD V SS DNUK I/O18V DD V SS V SS V SS V DD I/O6L I/O19V SS V DD V SS V DD V SS I/O7M I/O20V DD V SS V SS V SS V DD I/O8N I/O21V SS V DD V SS V DD V SS I/O9P I/O22V DD V SS V SS V SS V DD I/O10R I/O23A NC NC NC A I/O11T NC A A WE A A NCU NC A A OE A A NCMaximum Ratings(Above which the useful life may be impaired. For user guide-lines, not tested.)Storage Temperature .................................–65°C to +150°C Ambient Temperature withPower Applied.............................................–55°C to +125°C Supply Voltage on V CC to Relative GND[1]....–0.5V to +4.6V DC Voltage Applied to Outputsin High-Z State[1]....................................–0.5V to V CC + 0.5V DC Input Voltage[1]................................–0.5V to V CC + 0.5V Current into Outputs (LOW).........................................20 mAOperating RangeRangeAmbientTemperature V CC Commercial0°C to +70°C 3.3V ± 0.3V Industrial–40°C to +85°CDC Electrical Characteristics Over the Operating RangeParameter Description Test Conditions[2]–8–10–12Unit Min.Max.Min.Max.Min.Max.V OH Output HIGH Voltage V CC = Min.,I OH = –4.0 mA2.4 2.4 2.4VV OL Output LOW Voltage V CC = Min.,I OL = 8.0 mA0.40.40.4VV IH Input HIGH Voltage 2.0V CC+ 0.32.0V CC+ 0.32.0V CC+ 0.3VV IL[1]Input LOW Voltage–0.30.8–0.30.8–0.30.8V I IX Input Load Current GND < V I < V CC–1+1–1+1–1+1µA I OZ Output Leakage Current GND < V OUT < V CC, Output Disabled–1+1–1+1–1+1µAI CC V CC OperatingSupply Current V CC = Max.,f = f MAX = 1/t RCCommercial300275260mAIndustrial300275260mAI SB1Automatic CEPower-down Current—TTL Inputs Max. V CC, CE > V IHV IN > V IH orV IN < V IL, f = f MAX100100100mAI SB2Automatic CEPower-down Current—CMOS Inputs Max. V CC,CE > V CC– 0.3V,V IN > V CC– 0.3V,or V IN < 0.3V, f = 0Commercial/Industrial505050mACapacitance[3]Parameter Description Test Conditions Max.Unit C IN Input Capacitance T A = 25°C, f = 1 MHz, V CC = 3.3V8pF C OUT I/O Capacitance10pF Notes:1.V IL (min.) = –2.0V for pulse durations of less than 20 ns.2.0123.Tested initially and after any design or process changes that may affect these parameters.AC Test Loads and Waveforms [4]90%10%3.3V GND 90%10%ALL INPUT PULSES3.3V OUTPUT5 pFINCLUDING JIG AND SCOPE(a)(b)R1 317ΩR2351ΩRise time > 1 V/nsFall time:> 1 V/ns(c)OUTPUT50ΩZ 0= 50ΩV TH = 1.5V30 pF** Capacitive Load consists of all compo-nents of the test environment.AC Switching Characteristics Over the Operating Range [5]Parameter Description–8–10–12UnitMin.Max.Min.Max.Min.Max.Read Cycle t power [6]V CC (typical) to the first access 111ms t RC Read Cycle Time 81012ns t AA Address to Data Valid81012ns t OHA Data Hold from Address Change 333ns t ACE CE 1, CE 2, and CE 3 LOW to Data Valid 81012ns t DOE OE LOW to Data Valid 556ns t LZOE OE LOW to Low-Z [7]111ns t HZOE OE HIGH to High-Z [7]556ns t LZCE CE 1, CE 2, and CE 3 LOW to Low-Z [7]333ns t HZCE CE 1, CE 2, or CE 3 HIGH to High-Z [7]556ns t PU CE 1, CE 2, and CE 3 LOW to Power-up [8]0ns t PD CE 1, CE 2, or CE 3 HIGH to Power-down [8]81012ns t DBE Byte Enable to Data Valid 556ns t LZBE Byte Enable to Low-Z [7]111ns t HZBEByte Disable to High-Z [7]556nsWrite Cycle [9, 10]t WC Write Cycle Time81012ns t SCECE 1, CE 2, and CE 3 LOW to Write End678nsNotes:4.Valid SRAM operation does not occur until the power supplies have reached the minimum operating V DD (3.0V). As soon as 1 ms (T power ) after reachingthe minimum operating V DD , normal SRAM operation can begin including reduction in V DD to the data retention (V CCDR , 2.0V) voltage.5.Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specifiedI OL /I OH and transmission line loads. Test conditions for the read cycle use output loading as shown in part a) of the AC test loads, unless specified otherwise.6.This part has a voltage regulator which steps down the voltage from 3V to 2V internally. t power time has to be provided initially before a read/write operationis started.7.t HZOE , t HZCE , t HZWE , t HZBE , and t LZOE , t LZCE , t LZWE , t LZBE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured±200 mV from steady-state voltage.8.These parameters are guaranteed by design and are not tested.9.The internal write time of the memory is defined by the overlap of CE 1, CE 2, and CE 3 LOW and WE LOW. The chip enables must be active and WE mustbe LOW to initiate a write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.10.The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of t HZWE and t SD .t AW Address Set-up to Write End 678ns t HA Address Hold from Write End 000ns t SA Address Set-up to Write Start 000ns t PWE WE PulseWidth 678ns t SD Data Set-up to Write End 5 5.56ns t HD Data Hold from Write End 000ns t LZWE WE HIGH to Low-Z [7]333ns t HZWE WE LOW to High-Z [7]556ns t BWByte Enable to End of Write678nsAC Switching Characteristics Over the Operating Range (continued)[5]Parameter Description–8–10–12Unit Min.Max.Min.Max.Min.Max.Switching WaveformsRead Cycle No. 1[11, 12]Read Cycle No. 2 (OE Controlled)[2, 12, 13]Notes:11.Device is continuously selected. OE, CE = V IL .12.WE is HIGH for read cycle.13.PREVIOUS DATA VALIDDATA VALIDt RCt AAt OHAADDRESSDATA OUT50%50%DATA VALIDt RCt ACEt DOEt LZOEt LZCE t PUHIGH IMPEDANCEt HZOEt HZCEt PDHIGH OECEI CC I SBIMPEDANCEADDRESSDATA OUT V CC SUPPLY CURRENTWrite Cycle No. 1 (CE Controlled)[2, 14, 15]Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[14, 15]Write Cycle No. 3 (WE Controlled, OE LOW)[2, 15]Notes:14.Data I/O is high impedance if OE = V IH .15.16.During this period the I/Os are in the output state and input signals should not be applied.Switching Waveforms (continued)t WCDATA VALIDt AWt SAt PWEt HAt HDt SDt SCEt SCECEADDRESSWEDATA I/Ot HDt SDt PWEt SAt HAt AWt SCEt WCt HZOEDATA IN VALIDCEADDRESSWEDATA I/OOENOTE 16DATA VALIDt HDt SDt LZWEt PWEt SAt HAt AWt SCEt WCt HZWECEADDRESSWEDATA I/ONOTE 16Truth TableCE0CE1CE2OE WE I/O0–I/O23Mode PowerH H H X X High-Z Power-down Standby (I SB)L H H L H I/O0–I/O7 Data Out Read Active (I CC)H L H L H I/O8–I/O15 Data Out Read Active (I CC)H H L L H I/O16–I/O23 Data Out Read Active (I CC)L L L L H Full Data Out Read Active (I CC) L H H X L I/O0–I/O7 Data In Write Active (I CC)H L H X L I/O8–I/O15 Data In Write Active (I CC)H H L X L I/O16–I/O23 Data In Write Active (I CC)L L L X L Full Data In Write Active (I CC) L L L H H High-Z Selected, Outputs Disabled Active (I CC) Ordering InformationSpeed(ns)Ordering Code PackageName Package TypeOperatingRange8CY7C1012AV33-8BGC BG11914 × 22 mm 119-ball BGA Commercial CY7C1012AV33-8BGI Industrial 10CY7C1012AV33-10BGC Commercial CY7C1012AV33-10BGI Industrial 12CY7C1012AV33-12BGC Commercial CY7C1012AV33-12BGI IndustrialCY7C1012AV33 Package Diagram119-ball PBGA (14 x 22 x 2.4 mm) BG119CY7C1012AV33 Document History PageDocument Title: CY7C1012AV33 512K x 24 Static RAMDocument Number: 38-05254REV.ECN NO.IssueDateOrig. ofChange Description of Change**11371103/11/02NSL New Data Sheet*A11705707/31/02DFP Removed 15-ns bin.*B11798809/03/02DFP Added 8-ns bin.*C11899209/19/02DFP Change Cin - input capacitance -from 6 pF to 8 pF.Change Cout -output capacitance from 8 pF to 10 pF.*D1*******/15/02DFP Final data sheet. Added note 4 to “AC Test Loads and Waveforms.”。
CY7C1051DV33芯片手册
PRELIMINARY 8-Mbit (512K x 16) Static RAMCY7C1051DV33Features•High speed —t AA = 10 ns •Low active power—I CC = 110 mA @ 10 ns •Low CMOS standby power —I SB2 = 20 mA •2.0V data retention•Automatic power-down when deselected •TTL-compatible inputs and outputs•Easy memory expansion with CE and OE features•Available in lead-free 48-ball FBGA and 44-pin TSOP II packagesFunctional Description [1]The CY7C1051DV33 is a high-performance CMOS Static RAM organized as 512K words by 16 bits.Write to the device by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte LOW Enable (BLE) is LOW,then data from IO pins (IO 0–IO 7), is written into the location specified on the address pins (A 0–A 18). If Byte HIGH Enable (BHE) is LOW, then data from IO pins (IO 8–IO 15) is written into the location specified on the address pins (A 0–A 18).Read from the device by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH.If Byte LOW Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on IO 0–IO 7.If Byte HIGH Enable (BHE) is LOW, then data from memory will appear on IO 8 to IO 15. See the “Truth Table” on page 8 for a complete description of Read and Write modes.The input/output pins (IO 0–IO 15) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or a Write operation (CE LOW,and WE LOW) is in progress.The CY7C1051DV33 is available in a 44-pin TSOP II package with center power and ground (revolutionary) pinout, as well as a 48-ball fine-pitch ball grid array (FBGA) package.Note1.For guidelines on SRAM system design, please refer to the “System Design Guidelines” Cypress application note, available on the internet at .1415Logic Block DiagramA 1A 2A 3A 4A 5A 6A 7A 8COLUMN DECODERR O W D E C O D E RS E N S E A M P SINPUT BUFFER512K × 16ARRAYA 0A 11A 13A 12A A A 16A 17A 18A 9A 10IO 0–IO 7OE IO 8–IO 15CE WE BLEBHEPRELIMINARY CY7C1051DV33Selection Guide–10Unit Maximum Access Time 10ns Maximum Operating Current 110mA Maximum CMOS Standby Current20mAPin Configurations [2]48-ball Mini FBGAWE V CC A 11A 10NC A 6A 0A 3CE IO 10IO 8IO 9A 4A 5IO 11IO 13IO 12IO 14IO 15V SS A 9A 8OE V SS A 7IO 0BHE NC A 17A 2A 1BLE V CC IO 2IO 1IO 3IO 4IO 5IO 6IO 7A 15A 14A 13A 12NC A 18NC326541D E B A C F G HA 16(Top View)TSOP IIWE 1234567891011143132363534333740393812134144434216152930V CC A 5A 6A 7A 8A 0A 1OE V SS A 17IO 15A 2CE IO 2IO 0IO 1BHE A 3A 418172019IO 32728252622212324V SS IO 6IO 4IO 5IO 7A 16A 15BLE V CC IO 14IO 13IO 12IO 11IO 10IO 9IO 8A 14A 13A 12A 11A 9A 10A 18(Top View)Note2.NC pins are not connected on the diePRELIMINARY CY7C1051DV33Maximum Ratings(Exceeding the maximum ratings may impair the useful life of the device. These are for user guidelines, they are not tested.)Storage Temperature .................................–65°C to +150°C Ambient Temperature withPower Applied.............................................–55°C to +125°C Supply Voltage on V CC to Relative GND [3]....–0.5V to +4.6V DC Voltage Applied to Outputsin High-Z State [3]....................................–0.3V to V CC + 0.3V DC Input Voltage [3].................................–0.3V to V CC + 0.3VCurrent into Outputs (LOW).........................................20 mA Static Discharge Voltage............................................>2001V (per MIL-STD-883, Method 3015)Latch-up Current......................................................>200 mAOperating RangeRange Ambient Temperature V CC Industrial–40°C to +85°C3.3V ± 0.3VDC Electrical Characteristics Over the Operating RangeParameter DescriptionTest Conditions–10Unit Min MaxV OH Output HIGH Voltage V CC = Min, I OH = –4.0 mA 2.4V V OL Output LOW Voltage V CC = Min, I OL = 8.0 mA0.4V V IH Input HIGH Voltage 2.0V CC + 0.3V V IL [3]Input LOW Voltage –0.30.8V I IX Input Leakage Current GND < V I < V CC–1+1μA I OZ Output Leakage Current GND < V OUT < V CC , Output Disabled –1+1μA I CCV CC Operating Supply CurrentV CC = Max, f = f MAX = 1/t RC100 MHz 110mA83 MHz 100 66 MHz 9040 MHz80I SB1Automatic CE Power Down Current —TTL Inputs Max V CC , CE > V IH V IN > V IH or V IN < V IL , f = f MAX 40mA I SB2Automatic CE Power Down Current —CMOS Inputs Max V CC , CE > V CC – 0.3V,V IN > V CC – 0.3V or V IN < 0.3V, f = 020mACapacitance [4]Parameter DescriptionTest ConditionsMax.Unit C IN Input Capacitance T A = 25°C, f = 1 MHz, V CC = 3.3V12pF C OUTIO Capacitance12pFNotes3.V IL (min) = –2.0V and V IH (max) = V CC + 2.0V for pulse durations of less than 20 ns.4.Tested initially and after any design or process changes that may affect these parametersThermal Resistance [4]ParameterDescription Test ConditionsFBGA PackageTSOP II PackageUnit ΘJA Thermal Resistance (Junction to Ambient)Still Air, soldered on a 3 × 4.5 inch, four-layer printed circuit board28.3151.43°C/W ΘJCThermal Resistance (Junction to Case)11.415.8°C/WPRELIMINARYCY7C1051DV33AC Test Loads and Waveforms [5]AC Switching Characteristics [6] Over the Operating RangeParameterDescription–10UnitMinMaxRead Cycle t power [7]V CC (typical) to the first access 100μs t RC Read Cycle Time 10ns t AA Address to Data Valid10ns t OHA Data Hold from Address Change 3ns t ACE CE LOW to Data Valid 10ns t DOE OE LOW to Data Valid 5ns t LZOE OE LOW to Low-Z 0ns t HZOE OE HIGH to High-Z [8, 9]5ns t LZCE CE LOW to Low-Z [9]3ns t HZCE CE HIGH to High-Z [8, 9]5ns t PU CE LOW to Power Up 0ns t PD CE HIGH to Power Down 10ns t DBE Byte Enable to Data Valid 5ns t LZBE Byte Enable to Low-Z 0ns t HZBEByte Disable to High-Z6nsNotes5.AC characteristics (except High-Z) are tested using the load conditions shown in Figure (a). High-Z characteristics are tested for all speeds using the test loadshown in Figure (c).6.Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V.7.t POWER gives the minimum amount of time that the power supply should be at typical V CC values until the first memory access can be performed.8.t HZOE , t HZCE , t HZBE and t HZWE are specified with a load capacitance of 5 pF as in part (d) of AC Test Loads.Transition is measured when the outputs enter ahigh impedance state.9.At any given temperature and voltage condition, t HZCE is less than t LZCE , t HZOE is less than t LZOE , t HZBE is less than t LZBE , and t HZWE is less than t LZWE for anygiven device.90%10%3.0VGND90%10%ALL INPUT PULSES * CAPACITIVE LOAD CONSISTS OF ALL COMPONENTS OF THE TEST ENVIRONMENTRise Time: 1 V/nsFall Time: 1 V/ns30 pF*OUTPUTZ = 50Ω50Ω1.5V (a)3.3V OUTPUT5 pF(c)R 317ΩR2351ΩHigh-Z Characteristics(b)PRELIMINARY CY7C1051DV33Data Retention WaveformWrite Cycle [10, 11]t WC Write Cycle Time 10ns t SCE CE LOW to Write End 7ns t AW Address Setup to Write End 7ns t HA Address Hold from Write End 0ns t SA Address Setup to Write Start 0ns t PWE WE Pulse Width 7ns t SD Data Setup to Write End 5ns t HD Data Hold from Write End 0ns t LZWE WE HIGH to Low-Z [9]3ns t HZWE WE LOW to High-Z [8, 9]5ns t BWByte Enable to End of Write7nsData Retention Characteristics Over the Operating RangeParameter DescriptionConditions [12]Min MaxUnit V DR V CC for Data Retention 2.0V I CCDR Data Retention CurrentV CC = V DR = 2.0V , CE > V CC – 0.3V , V IN > V CC – 0.3V or V IN < 0.3V20mA t CDR [4]Chip Deselect to Data Retention Time 0ns t R [13]Operation Recovery Timet RCnsAC Switching Characteristics [6] Over the Operating Range (continued)ParameterDescription–10UnitMinMax3.0V 3.0V t CDRV DR > 2VDATA RETENTION MODEt RCEV CC Notes10.The internal Write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a Write, and the transition ofeither of these signals can terminate the Write. The input data setup and hold timing should be referenced to the leading edge of the signal that terminates the Write.11.The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of t HZWE and t SD .12.No inputs may exceed V CC + 0.3V13.Full device operation requires linear V CC ramp from V DR to V CC (min) > 50 μs or stable at V CC (min) > 50 μs.PRELIMINARY CY7C1051DV33Switching WaveformsRead Cycle No. 1[14, 15]Read Cycle No. 2 (OE Controlled)[15, 16]Notes14.Device is continuously selected. OE, CE, BHE or BHE or both= V IL .15.WE is HIGH for Read cycle.16.Address valid prior to or coincident with CE transition LOW.PREVIOUS DATA VALIDDATA VALIDt RCt AAt OHAADDRESSDATA OUT50%50%DATA VALIDt RCt ACEt DOE t LZOE t LZCE t PUHIGH IMPEDANCEt HZOEt HZBEt PDHIGHOE CEICC ISB IMPEDANCEADDRESSDATA OUT V CC SUPPLY t DBE t LZBEt HZCE BHE,BLECURRENTI CCI SBPRELIMINARY CY7C1051DV33Write Cycle No. 1 (CE Controlled)[17, 18]Write Cycle No. 2 (BLE or BHE Controlled)Notes17.Data I/O is high-impedance if OE or BHE or BLE or both = V IH .18.If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.Switching Waveforms (continued)t HDt SDt SCEt SA t HAt AWt PWEt WCBWDATAI/OADDRESSCEWEBHE,BLEt t HDt SDt BWt SA t HAt AWt PWEt WCt SCEDATAI/OADDRESSBHE,BLEWECEPRELIMINARY CY7C1051DV33Write Cycle No. 3 (WE Controlled, OE LOW)Switching Waveforms (continued)t HDt SDt SCEt HAt AWt PWEt WCt BWDATA I/OADDRESSCEWEBHE,BLEt SAt LZWEt HZWETruth TableCE OE WE BLE BHE I/O 0–I/O 7I/O 8–I/O 15ModePower H X X X X High-Z High-Z Power-down Standby (I SB )L L H L L Data Out Data Out Read All Bits Active (I CC )L L H L H Data Out High-Z Read Lower Bits Only Active (I CC )L L H H L High-Z Data Out Read Upper Bits Only Active (I CC )L X L L L Data In Data In Write All Bits Active (I CC )L X L L H Data In High-Z Write Lower Bits Only Active (I CC )L X L H L High-Z Data In Write Upper Bits Only Active (I CC )LHHXXHigh-ZHigh-ZSelected, Outputs DisabledActive (I CC )Ordering InformationSpeed (ns)Ordering Code Package Diagram Package TypeOperating Range 10CY7C1051DV33-10BAXI 51-8510648-ball FBGA (Pb-Free)IndustrialCY7C1051DV33-10ZSXI51-8508744-pin TSOP II (Pb-Free)Please contact your local Cypress sales representative for availability of these parts.PRELIMINARY CY7C1051DV33 Package DiagramsPRELIMINARY CY7C1051DV33Document #: 001-00063 Rev. *C Page 10 of 11© Cypress Semiconductor Corporation, 2006-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the All products and company names mentioned in this document may be the trademarks of their respective holders.Figure 2. 44-pin TSOP II (51-85087)Package Diagrams (continued)51-85087-*APRELIMINARY CY7C1051DV33Document #: 001-00063 Rev. *C Page 11 of 11Document History Page Document Title: CY7C1051DV33 8-Mbit (512K x 16) Static RAM Document Number: 001-00063REV.ECN NO.Issue Date Orig. of Change Description of Change **342195See ECN PCI New Data Sheet *A 380574See ECN SYT Redefined I CC values for Com’l and Ind’l temperature rangesI CC (Com’l): Changed from 110, 90 and 80 mA to 110, 100 and 95 mA for 8, 10and 12 ns speed bins respectivelyI CC (Ind’l): Changed from 110, 90 and 80 mA to 120, 110 and 105 mA for 8, 10and 12 ns speed bins respectivelyChanged the Capacitance values from 8 pF to 10 pF on Page # 3*B 485796See ECN NXR Changed address of Cypress Semiconductor Corporation on Page# 1 from“3901 North First Street” to “198 Champion Court”Removed -8 and -12 Speed bins from product offering,Removed Commercial Operating Range option,Modified Maximum Ratings for DC input voltage from -0.5V to -0.3V andV CC + 0.5V to V CC + 0.3VChanged the Description of I IX from Input Load Current toInput Leakage Current.Changed t HZBE from 5 ns to 6 nsUpdated footnote #7 on High-Z parameter measurementAdded footnote #11Updated the Ordering Information table and Replaced Package Name columnwith Package Diagram.*C 866000See ECN NXRChanged ball E3 from V SS to NC in FBGA pin configuration [+] FeedbThis datasheet has been downloaded from:Free DownloadDaily Updated Database100% Free Datasheet Search Site100% Free IC Replacement Search SiteConvenient Electronic DictionaryFast Search SystemAll Datasheets Cannot Be Modified Without PermissionCopyright © Each Manufacturing Company。
CY7C1470BV25资料
72-Mbit (2M x 36/4M x 18/1M x 72)Pipelined SRAM with NoBL™ ArchitectureCY7C1470BV25CY7C1472BV25, CY7C1474BV25Features■Pin-compatible and functionally equivalent to ZBT™ ■Supports 250 MHz bus operations with zero wait states ❐Available speed grades are 250, 200, and 167 MHz■Internally self-timed output buffer control to eliminate the need to use asynchronous OE■Fully registered (inputs and outputs) for pipelined operation■Byte Write capability ■Single 2.5V power supply ■2.5V IO supply (V DDQ )■Fast clock-to-output times ❐3.0 ns (for 250-MHz device)■Clock Enable (CEN) pin to suspend operation ■Synchronous self-timed writes■CY7C1470BV25, CY7C1472BV25 available inJEDEC-standard Pb-free 100-pin TQFP , Pb-free and non-Pb-free 165-ball FBGA package. CY7C1474BV25available in Pb-free and non-Pb-free 209-ball FBGA package ■IEEE 1149.1 JTAG Boundary Scan compatible ■Burst capability—linear or interleaved burst order ■“ZZ” Sleep Mode option and Stop Clock optionFunctional DescriptionThe CY7C1470BV25, CY7C1472BV25, and CY7C1474BV25are 2.5V, 2M x 36/4M x 18/1M x 72 synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL ™) logic, respectively.They are designed to support unlimited true back-to-back read or write operations with no wait states. The CY7C1470BV25,CY7C1472BV25, and CY7C1474BV25 are equipped with the advanced (NoBL) logic required to enable consecutive read or write operations with data being transferred on every clock cycle.This feature dramatically improves the throughput of data in systems that require frequent read or write transitions. The CY7C1470BV25, CY7C1472BV25, and CY7C1474BV25 are pin-compatible and functionally equivalent to ZBT devices.All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable (CEN) signal, which when deasserted suspends operation and extends the previous clock cycle. Write operations are controlled by the Byte Write Selects (BW a –BW d for CY7C1470BV25, BW a –BW b for CY7C1472BV25, and BW a –BW h for CY7C1474BV25) and a Write Enable (WE) input. All writes are conducted with on-chip synchronous self-timed write circuitry.Three synchronous Chip Enables (CE 1, CE 2, CE 3) and an asynchronous Output Enable (OE) provide for easy bank selection and output tri-state control. To avoid bus contention,the output drivers are synchronously tri-stated during the data portion of a write sequence.Selection GuideDescription250 MHz 200 MHz 167 MHz Unit Maximum Access Time3.0 3.0 3.4ns Maximum Operating Current450450400mA Maximum CMOS Standby Current120120120mALogic Block Diagram – CY7C1470BV25 (2M x 36)Logic Block Diagram – CY7C1472BV25 (4M x 18)Logic Block Diagram – CY7C1474BV25 (1M x 72)Pin ConfigurationsA A A A A 1A 0V S SV D DA A A A A AV DDQ V SSDQb DQb DQb V SS V DDQDQb DQb V SSNCV DDDQaDQa V DDQ V SSDQa DQa V SS V DDQ V DDQV SS DQc DQc V SS V DDQ DQc V DD V SS DQd DQd V DDQ V SS DQd DQd DQd V SS V DDQ A A C E 1C E 2B W aC E 3V D DV S SC L K W E C E N O E A A123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495080797877767574737271706968676665646362616059585756555453525110099989796959493929190898887868584838281A AA D V /L D ZZCY7C1470BV25A A A A A 1A 0V S SV D DA A A A A AA NC NC V DDQ V SS NC DQPa DQa DQa V SS V DDQ DQa DQa V SS NC V DD DQa DQa V DDQ V SS DQa DQa NC NC V SS V DDQ NC NC NCNC NC NC V DDQ V SS NC NC DQb DQb V SS V DDQDQb DQbV DD V SS DQb DQb V DDQV SS DQb DQb DQPbNC V SS V DDQNC NC NCA A C E 1C E 2N C N C B W b B W a C E 3V D DV S SC L K W E C E N O E A A123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495080797877767574737271706968676665646362616059585756555453525110099989796959493929190898887868584838281A AA D V /L D ZZ M O D E CY7C1472BV25B W d M O D E B W c DQc DQc DQc DQc DQPc DQd DQd DQd DQPb DQb DQa DQaDQa DQaDQPa DQb DQb (2M × 36)(4M × 18)B W b NC NC NC DQc NC N C (288)N C (144)N C (288)N C (144)DQPdA A A A A A Figure 1. 100-Pin TQFP PinoutPin Configurations (continued)165-Ball FBGA (15 x 17 x 1.4 mm) PinoutCY7C1470BV25 (2M x 36)CY7C1472BV25 (4M x 18)2345671A B C D E F G H J K L M N P RTDO NC/576M NC/1G DQP c DQ c DQP d NC DQ d A CE 1BW b CE 3BW c CEN A CE2DQ c DQ d DQ d MODENC DQ c DQ c DQ d DQ d DQ d AV DDQ BW d BW a CLKWEV SS V SS V SS V SS V DDQ V SS V DD V SS V SS V SS NC V SS V SS V SS V SS V DDQ V DDQ NC V DDQ V DDQ V DDQ V DDQ A AV DD V SS V DD V SS V SS V DDQ V DD V SS V DD V SS V DD V SS V SS V SS V DD V DD V SS V DD V SS V SS NC TCKA0V SS TDIAA DQ c V SS DQ c V SS DQ c DQ c NC V SS V SS V SS V SS NC V SS A1DQ d DQ d NC/144M NCV DDQ V SS TMS891011NC/288MAA ADV/LDNC OE A A NC V SS V DDQ NC DQP b V DDQ V DD DQ b DQ b DQ b NC DQ b NC DQ a DQ a V DD V DDQ V DD V DDQ DQ b V DD NC V DD DQ a V DD V DDQ DQ a V DDQ V DD V DD V DDQ V DD V DDQ DQ a V DDQ AAV SS AAADQ b DQ b DQ b ZZ DQ a DQ a DQP aDQ a A V DDQ AA 2345671A B C D E F G H J K L M N P RTDO NC/576M NC/1G NC NC DQP b NC DQ b A CE 1CE 3BW b CEN A CE2NC DQ b DQ b MODENC DQ b DQ b NC NC NC AV DDQ BW a CLKWE V SS V SS V SS V SSV DDQ V SS V DD V SS V SS V SS NC V SS V SS V SS V SS V DDQ V DDQ NC V DDQ V DDQ V DDQ V DDQ A AV DD V SS V DD V SS V SS V DDQ V DD V SS V DD V SS V DD V SS V SS V SS V DD V DD V SS V DD V SS V SS NC TCKA0V SS TDIAA DQ b V SS NC V SS DQ b NC NC V SS V SS V SS V SS NC V SS A1DQ b NC NC/144M NCV DDQ V SS TMS891011NC/288MAA ADV/LDA OE A A NC V SSV DDQ NC DQPa V DDQ V DD NC DQ a DQ a NC NC NC DQ a NC V DD V DDQ V DD V DDQ DQ a V DD NC V DD NC V DD V DDQ DQ a V DDQ V DD V DD V DDQ V DD V DDQ NC V DDQ AAV SS AAADQ a NC NC ZZ DQ a NC NCDQ a A V DDQ AA NC NCPin Configurations (continued)CY7C1474BV25 (1M × 72)209-Ball FBGA (14 x 22 x 1.76 mm) PinoutA B C D E F G H J K L M N P R T U V W1234567891110DQgDQgDQgDQgDQgDQgDQgDQgDQcDQcDQcDQcNCDQPgDQhDQhDQhDQhDQdDQdDQdDQdDQPdDQPcDQcDQcDQcDQcNCDQhDQhDQhDQhDQPhDQdDQdDQdDQdDQbDQbDQbDQbDQbDQbDQbDQbDQfDQfDQfDQfNCDQPfDQaDQaDQaDQaDQeDQeDQeDQeDQPaDQPbDQfDQfDQfDQfNCDQaDQaDQaDQaDQPeDQeDQeDQeDQeA A A ANC NCNC/144M A A NC/288MA A AA A A A1A0A A AA AANC/576MNCNCNC NCNCBWS b BWS fBWS e BWS aBWS c BWS gBWS dBWS hTMS TDI TDO TCKNCNC MODE NCCEN V SSNCCLK NC V SSV DD V DD V DDV DDV DDV DDV DDV DDV DDV DDV DDV DDV DDV SS V SSV SSV SSV SSV SS V SSV SSNC/1GV DDNCOECE3CE1CE2ADV/LDWEV SSV SSV SSV SS V SS V SS VSSZZV SS V SS V SS V SSNCV DDQV SSV SS NC V SS V SSV SS V SS VSSV SSNCV SSV DDQ V DDQ V DDQ V DDQV DDQ NC V DDQ VDDQV DDQ V DDQ NC V DDQ V DDQV DDQ V DDQ NC V DDQ VDDQV DDQV DDQV DDQ V DDQV DDQ VDDQV DDQ V DDQTable 1. Pin DefinitionsPin Name IO Type Pin DescriptionA0 A1 AInput-SynchronousAddress Inputs Used to Select One of the Address Locations. Sampled at the rising edge of theCLK.BW a BW b BW c BW d BW e BW f BW g BW hInput-SynchronousByte Write Select Inputs, Active LOW. Qualified with WE to conduct writes to the SRAM. Sampledon the rising edge of CLK. BW a controls DQ a and DQP a, BW b controls DQ b and DQP b, BW c controlsDQ c and DQP c, BW d controls DQ d and DQP d, BW e controls DQ e and DQP e, BW f controls DQ f andDQP f, BW g controls DQ g and DQP g, BW h controls DQ h and DQP h.WE Input-Synchronous Write Enable Input, Active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This signal must be asserted LOW to initiate a write sequence.ADV/LD Input-Synchronous Advance/Load Input Used to Advance the On-Chip Address Counter or Load a New Address. When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new address can be loaded into the device for an access. After being deselected, ADV/LD must be driven LOW to load a new address.CLK Input-Clock Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK is only recognized if CEN is active LOW.CE1Input-Synchronous Chip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2 and CE3 to select/deselect the device.CE2Input-Synchronous Chip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE3 to select/deselect the device.CE3Input-Synchronous Chip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE2 to select/deselect the device.OE Input-Asynchronous Output Enable, Active LOW. Combined with the synchronous logic block inside the device to control the direction of the IO pins. When LOW, the IO pins can behave as outputs. When deasserted HIGH, IO pins are tri-stated, and act as input data pins. OE is masked during the data portion of a write sequence, during the first clock when emerging from a deselected state and when the device has been deselected.CEN Input-Synchronous Clock Enable Input, Active LOW. When asserted LOW the clock signal is recognized by the SRAM. When deasserted HIGH the clock signal is masked. Since deasserting CEN does not deselect the device, CEN can be used to extend the previous cycle when required.DQ s IO-Synchronous Bidirectional Data IO Lines. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by A[18:0] during the previous clock rise of the read cycle. The direction of the pins is controlled by OE and the internal control logic. When OE is asserted LOW, the pins can behave as outputs. When HIGH, DQ a–DQ h are placed in a tri-state condition. The outputs are automatically tri-stated during the data portion of a write sequence, during the first clock when emerging from a deselected state, and when the device is deselected, regardless of the state of OE.DQP X IO-Synchronous Bidirectional Data Parity IO Lines. Functionally, these signals are identical to DQ[71:0]. During write sequences, DQP a is controlled by BW a, DQP b is controlled by BW b, DQP c is controlled by BW c, and DQP d is controlled by BW d, DQP e is controlled by BW e, DQP f is controlled by BW f, DQP g is controlled by BW g, DQP h is controlled by BW h.MODE Input Strap Pin Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order.Pulled LOW selects the linear burst order. MODE must not change states during operation. Whenleft floating MODE defaults HIGH, to an interleaved burst order.TDO JTAG SerialOutputSynchronousSerial Data Out to the JTAG Circuit. Delivers data on the negative edge of TCK.TDI JTAG Serial InputSynchronousSerial Data In to the JTAG Circuit. Sampled on the rising edge of TCK.Functional OverviewThe CY7C1470BV25, CY7C1472BV25, and CY7C1474BV25 are synchronous-pipelined Burst NoBL SRAMs designed specif-ically to eliminate wait states during read or write transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock signal is qualified with the Clock Enable input signal (CEN). If CEN is HIGH, the clock signal is not recognized and all internal states are maintained. All synchronous operations are qualified with CEN. All data outputs pass through output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise (t CO) is 3.0 ns (250-MHz device).Accesses can be initiated by asserting all three Chip Enables (CE1, CE2, CE3) active at the rising edge of the clock. If CEN is active LOW and ADV/LD is asserted LOW, the address presented to the device is latched. The access can either be a read or write operation, depending on the status of the Write Enable (WE). BW[x] can be used to conduct Byte Write opera-tions.Write operations are qualified by the Write Enable (WE). All writes are simplified with on-chip synchronous self-timed write circuitry.Three synchronous Chip Enables (CE1, CE2, CE3) and an asynchronous Output Enable (OE) simplify depth expansion. All operations (reads, writes, and deselects) are pipelined. ADV/LD must be driven LOW after the device is deselected to load a new address for the next operation.Single Read AccessesA read access is initiated when the following conditions are satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2, and CE3 are ALL asserted active, (3) the input signal WE is deasserted HIGH, and (4) ADV/LD is asserted LOW. The address presented to the address inputs is latched into the Address Register and presented to the memory core and control logic. The control logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At the rising edge of the next clock the requested data is allowed to propagate through the output register and onto the data bus within 2.6 ns (250-MHz device) provided OE is active LOW. After the first clock of the read access the output buffers are controlled by OE and the internal control logic. OE must be driven LOW to drive out the requested data. During the second clock, a subsequent operation (read, write, or deselect) can be initiated. Deselecting the device is also pipelined. Therefore, when the SRAM is deselected at clock rise by one of the chip enable signals, its output tri-states following the next clock rise.Burst Read AccessesThe CY7C1470BV25, CY7C1472BV25, and CY7C1474BV25 have an on-chip burst counter that enables the user to supply a single address and conduct up to four reads without reasserting the address inputs. ADV/LD must be driven LOW to load a new address into the SRAM, as described in the Single Read Accesses section. The sequence of the burst counter is deter-mined by the MODE input signal. A LOW input on MODE selects a linear burst mode, a HIGH selects an interleaved burst sequence. Both burst counters use A0 and A1 in the burst sequence, and wraps around when incremented sufficiently. A HIGH input on ADV/LD increments the internal burst counter regardless of the state of chip enables inputs or WE. WE is latched at the beginning of a burst cycle. Therefore, the type of access (read or write) is maintained throughout the burst sequence.Single Write AccessesWrite accesses are initiated when the following conditions are satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2, and CE3 are ALL asserted active, and (3) the signal WE is asserted LOW. The address presented to the address inputs is loaded into the Address Register. The write signals are latched into the Control Logic block.On the subsequent clock rise the data lines are automatically tri-stated regardless of the state of the OE input signal. This allows the external logic to present the data on DQ and DQP (DQ a,b,c,d/DQP a,b,c,d for CY7C1470BV25, DQ a,b/DQP a,b for CY7C1472BV25, and DQ a,b,c,d,e,f,g,h/DQP a,b,c,d,e,f,g,h for CY7C1474BV25). In addition, the address for the subsequentTMS Test Mode SelectSynchronousTMS Pin Controls the Test Access Port State Machine. Sampled on the rising edge of TCK. TCK JTAG Clock Clock Input to the JTAG Circuitry.V DD Power Supply Power Supply Inputs to the Core of the Device.V DDQ IO Power Supply Power Supply for the IO Circuitry.V SS Ground Ground for the Device. Must be connected to ground of the system.NC–No Connects. This pin is not connected to the die.NC(144M, 288M, 576M, 1G)–These Pins are Not Connected. They are used for expansion to the 144M, 288M, 576M, and 1G densities.ZZ Input-Asynchronous ZZ “Sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition with data integrity preserved. For normal operation, this pin has must be LOW or left floating.ZZ pin has an internal pull down.Table 1. Pin Definitions (continued)Pin Name IO Type Pin Descriptionaccess (read, write, or deselect) is latched into the Address Register (provided the appropriate control signals are asserted). On the next clock rise the data presented to DQ and DQP (DQ a,b,c,d/DQP a,b,c,d for CY7C1470BV25, DQ a,b/DQP a,b for CY7C1472BV25, DQ a,b,c,d,e,f,g,h/DQP a,b,c,d,e,f,g,h for CY7C1474BV25) (or a subset for Byte Write operations, see “Partial Write Cycle Description” on page11 for details) inputs is latched into the device and the Write is complete.The data written during the Write operation is controlled by BW (BW a,b,c,d for CY7C1470BV25, BW a,b for CY7C1472BV25, and BW a,b,c,d,e,f,g,h for CY7C1474BV25) signals. The CY7C1470BV25, CY7C1472BV25, and CY7C1474BV25 provides Byte Write capability that is described in “Partial Write Cycle Description” on page11. Asserting the WE input with the selected BW input selectively writes to only the desired bytes. Bytes not selected during a Byte Write operation remain unaltered. A synchronous self-timed write mechanism has been provided to simplify the write operations. Byte Write capability has been included to greatly simplify read, modify, or write sequences, which can be reduced to simple Byte Write opera-tions.Because the CY7C1470BV25, CY7C1472BV25, and CY7C1474BV25 are common IO devices, data must not be driven into the device while the outputs are active. OE can be deasserted HIGH before presenting data to the DQ and DQP (DQ a,b,c,d/DQP a,b,c,d for CY7C1470BV25, DQ a,b/DQP a,b for CY7C1472BV25, and DQ a,b,c,d,e,f,g,h/DQP a,b,c,d,e,f,g,h for CY7C1474BV25) inputs. Doing so tri-states the output drivers. As a safety precaution, DQ and DQP (DQ a,b,c,d/DQP a,b,c,d for CY7C1470BV25, DQ a,b/DQP a,b for CY7C1472BV25, and DQ a,b,c,d,e,f,g,h/DQP a,b,c,d,e,f,g,h for CY7C1474BV25) are automatically tri-stated during the data portion of a write cycle, regardless of the state of OE.Burst Write AccessesThe CY7C1470BV25, CY7C1472BV25, and CY7C1474BV25 has an on-chip burst counter that enables the user to supply a single address and conduct up to four write operations without reasserting the address inputs. ADV/LD must be driven LOW to load the initial address, as described in “Single Write Accesses”on page8. When ADV/LD is driven HIGH on the subsequent clock rise, the Chip Enables (CE1, CE2, and CE3) and WE inputs are ignored and the burst counter is incremented. The correct BW (BW a,b,c,d for CY7C1470BV25, BW a,b for CY7C1472BV25, and BW a,b,c,d,e,f,g,h for CY7C1474BV25) inputs must be driven in each cycle of the burst write to write the correct bytes of data. Sleep ModeThe ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation “sleep” mode. Two clock cycles are required to enter into or exit from this “sleep” mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the “sleep” mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected before entering the “sleep” mode. CE1, CE2, and CE3, must remain inactive for the duration of t ZZREC after the ZZ input returns LOW.Table 2. Linear Burst Address Table (MODE = GND) FirstAddressSecondAddressThirdAddressFourthAddress A1,A0A1,A0A1,A0A1,A000011011011011001011000111000110Table 3. Interleaved Burst Address Table(MODE = Floating or V DD)FirstAddressSecondAddressThirdAddressFourthAddress A1,A0A1,A0A1,A0A1,A000011011010011101011000111100100ZZ Mode Electrical CharacteristicsParameter Description Test Conditions Min Max Unit I DDZZ Sleep mode standby current ZZ > V DD − 0.2V120mA t ZZS Device operation to ZZ ZZ > V DD− 0.2V2t CYC ns t ZZREC ZZ recovery time ZZ < 0.2V2t CYC ns t ZZI ZZ active to sleep current This parameter is sampled2t CYC ns t RZZI ZZ Inactive to exit sleep current This parameter is sampled0nsTable 4. Truth TableThe truth table for CY7C1470BV25, CY7C1472BV25, and CY7C1474BV25 follows.[1, 2, 3, 4, 5, 6, 7]Operation AddressUsed CE ZZ ADV/LD WE BW x OE CEN CLK DQ Deselect Cycle None H L L X X X L L-H Tri-State Continue Deselect Cycle None X L H X X X L L-H Tri-StateExternal L L L H X L L L-H Data Out (Q) Read Cycle(Begin Burst)Next X L H X X L L L-H Data Out (Q) Read Cycle(Continue Burst)External L L L H X H L L-H Tri-State NOP/Dummy Read(Begin Burst)Next X L H X X H L L-H Tri-State Dummy Read(Continue Burst)External L L L L L X L L-H Data In (D) Write Cycle(Begin Burst)Next X L H X L X L L-H Data In (D) Write Cycle(Continue Burst)None L L L L H X L L-H Tri-State NOP/Write Abort(Begin Burst)Next X L H X H X L L-H Tri-State Write Abort(Continue Burst)Ignore Clock Edge (Stall)Current X L X X X X H L-H–Sleep Mode None X H X X X X X X Tri-StateNotes1.X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands for ALL Chip Enables active. BW x = L signifies at least one Byte Write Select is active, BW x = Validsignifies that the desired Byte Write Selects are asserted, see “Partial Write Cycle Description” on page11 for details.2.[a:d]. See “Partial Write Cycle Description” on page11 for details.3.When a write cycle is detected, all IOs are tri-stated, even during Byte Writes.4.The DQ and DQP pins are controlled by the current cycle and the OE signal.5.6.Device powers up deselected with the IOs in a tri-state condition, regardless of OE.7.OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles.During a Read cycle DQ s and DQP[a:d] = tri-state when OE isinactive or when the device is deselected, and DQ s = data when OE is active.Table 5. Partial Write Cycle DescriptionThe partial write cycle description for CY7C1470BV25, CY7C1472BV25, and CY7C1474BV25 follows.[1, 2, 3, 8]Function (CY7C1470BV25)WE BW d BW c BW b BW a Read H X X X X Write – No bytes written L H H H H Write Byte a – (DQ a and DQP a)L H H H L Write Byte b – (DQ b and DQP b)L H H L H Write Bytes b, a L H H L L Write Byte c – (DQ c and DQP c)L H L H H Write Bytes c, a L H L H L Write Bytes c, b L H LL L H Write Bytes c, b, a L H L L L Write Byte d – (DQ d and DQP d)L L H H H Write Bytes d, a L L H H L Write Bytes d, b L L H L H Write Bytes d, b, a L L H L L Write Bytes d, c L L L H H Write Bytes d, c, a L L L H L Write Bytes d, c, b L L L L H Write All Bytes L L L L LFunction (CY7C1472BV25)WE BW b BW aRead H x xWrite – No Bytes Written L H HWrite Byte a – (DQ a and DQP a)L H LWrite Byte b – (DQ b and DQP b)L L HWrite Both Bytes L L LFunction (CY7C1474BV25)WE BW xRead H xWrite – No Bytes Written L HWrite Byte X − (DQ x and DQP x)L LWrite All Bytes L All BW = LNote8.Table lists only a partial listing of the Byte Write combinations. Any combination of BW[a:d] is valid. Appropriate write is based on which Byte Write is active.IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1470BV25, CY7C1472BV25, and CY7C1474BV25incorporates a serial boundary scan test access port (TAP). This port operates in accordance with IEEE Standard 1149.1-1990 but does not have the set of functions required for full 1149.1 compliance. These functions from the IEEE specification are excluded because their inclusion places an added delay in the critical speed path of the SRAM. Note that the TAP controller functions in a manner that does not conflict with the operation of other devices using 1149.1 fully compliant TAPs. The TAP operates using JEDEC-standard 2.5V IO logic levels.The CY7C1470BV25, CY7C1472BV25, and CY7C1474BV25 contains a TAP controller, instruction register, boundary scan register, bypass register, and ID register.Disabling the JTAG FeatureIt is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (V SS) to prevent clocking of the device. TDI and TMS are inter-nally pulled up and may be unconnected. They may alternately be connected to V DD through a pull up resistor. TDO must be left unconnected. During power up, the device comes up in a reset state, which does not interfere with the operation of the device. The 0/1 next to each state represents the value of TMS at therising edge of TCK.Test Access Port (TAP)Test Clock (TCK)The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK.Test MODE SELECT (TMS)The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. It is allowable to leave this ball unconnected if the TAP is not used. The ball is pulled up internally, resulting in a logic HIGH level.Test Data-In (TDI)The TDI ball is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information about loading the instruction register, see the TAP Controller State Diagram. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) of any register. (See TAP Controller Block Diagram.)Test Data-Out (TDO)The TDO output ball is used to serially clock data-out from the registers. The output is active depending upon the current state of the TAP state machine. The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register. (See TAP Controller State Diagram.)Performing a TAP ResetA RESET is performed by forcing TMS HIGH (V DD) for five rising edges of TCK. This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating. During power up, the TAP is reset internally to ensure that TDO comes up in a High-Z state.TAP RegistersRegisters are connected between the TDI and TDO balls to scan the data in and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction register. Data is serially loaded into the TDI ball on the rising edge of TCK. Data is output on the TDO ball on the falling edge of TCK.Figure 2. TAP Controller State DiagramFigure 3. TAP Controller Block DiagramInstruction RegisterThree-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO balls as shown in the “TAP Controller Block Diagram”on page12. During power up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section.When the TAP controller is in the Capture-IR state, the two least significant bits are loaded with a binary ‘01’ pattern to enable fault isolation of the board-level serial test data path.Bypass RegisterTo save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a single-bit register that can be placed between the TDI and TDO balls. This shifts the data through the SRAM with minimal delay. The bypass register is set LOW (V SS) when the BYPASS instruction is executed.Boundary Scan RegisterThe boundary scan register is connected to all the input and bidirectional balls on the SRAM.The boundary scan register is loaded with the contents of the RAM IO ring when the TAP controller is in the Capture-DR state and is then placed between the TDI and TDO balls when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions can be used to capture the contents of the IO ring.The Boundary Scan Order tables on page 17 show the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI and the LSB is connected to TDO. Identification (ID) RegisterThe ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has a vendor code and other information described in “Identification Register Definitions” on page16.TAP Instruction SetOverviewEight different instructions are possible with the three-bit instruction register. All combinations are listed in “Identification Codes” on page17. Three of these instructions are listed as RESERVED and must not be used. The other five instructions are described in this section in detail.The TAP controller used in this SRAM is not fully compliant to the 1149.1 convention because some of the mandatory 1149.1 instructions are not fully implemented.The TAP controller cannot be used to load address data or control signals into the SRAM and cannot preload the IO buffers. The SRAM does not implement the 1149.1 commands EXTEST or INTEST or the PRELOAD portion of SAMPLE/PRELOAD; rather, it performs a capture of the IO ring when these instruc-tions are executed.Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO balls. To execute the instruction after it is shifted in, the TAP controller must be moved into the Update-IR state.EXTESTEXTEST is a mandatory 1149.1 instruction which is executed whenever the instruction register is loaded with all 0s. EXTEST is not implemented in this SRAM TAP controller, and therefore this device is not compliant to 1149.1. The TAP controller does recognize an all-0 instruction.When an EXTEST instruction is loaded into the instruction register, the SRAM responds as if a SAMPLE/PRELOAD instruction has been loaded. There is one difference between the two instructions. Unlike the SAMPLE/PRELOAD instruction, EXTEST places the SRAM outputs in a High-Z state.IDCODEThe IDCODE instruction loads a vendor-specific, 32-bit code into the instruction register. It also places the instruction register between the TDI and TDO balls and shifts the IDCODE out of the device when the TAP controller enters the Shift-DR state.The IDCODE instruction is loaded into the instruction register during power up or whenever the TAP controller is in a test logic reset state.SAMPLE ZThe SAMPLE Z instruction connects the boundary scan register between the TDI and TDO pins when the TAP controller is in a Shift-DR state. It also places all SRAM outputs into a High-Z state.SAMPLE/PRELOADSAMPLE/PRELOAD is a 1149.1 mandatory instruction. The PRELOAD portion of this instruction is not implemented, so the device TAP controller is not fully 1149.1 compliant.When the SAMPLE/PRELOAD instruction is loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the inputs and bidirectional balls is captured in the boundary scan register.The user must be aware that the TAP controller clock can only operate at a frequency up to 20 MHz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output may undergo a transition. The TAP may then try to capture a signal while in transition (metastable state). This does not harm the device, but there is no guarantee as to the value that is captured. Repeatable results may not be possible.To guarantee that the boundary scan register captures the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller’s capture setup plus hold time (t CS plus t CH).The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is still。
ZC7310系列使用说明书
目录目录................................................................................................................................... - 1 -第一章概述 ......................................................................................................................... - 3 -1.1 使用条件 .............................................................................................................................................. - 4 -第二章操作规范和措施....................................................................................................... - 6 -2.1 操作规范 .............................................................................................................................................. - 6 -2.2 处理措施 .............................................................................................................................................. - 9 -第三章仪器面板概述......................................................................................................... - 11 -3.1 前面板说明 ........................................................................................................................................ - 11 -3.2 后面板说明 ........................................................................................................................................ - 13 -第四章操作说明 ................................................................................................................ - 14 -4.1 仪器界面结构描述 ............................................................................................................................ - 14 -4.2 测量显示界面（TEST界面）............................................................................................................ - 15 -4.2.1 测试结果界面--------------------------------------------------------------------------------------------------- - 16 -4.2.2 清零---------------------------------------------------------------------------------------------------------------- - 17 -4.3 测量设置界面 .................................................................................................................................... - 17 -4.3.1 交流耐压测试设置 -------------------------------------------------------------------------------------------- - 18 -4.3.2 直流耐压测试设置---------------------------------------------------------------------------------------------- - 21 -4.3.3 绝缘电阻测试设置 -------------------------------------------------------------------------------------------- - 24 -4.3.4 暂停模式测试设置 -------------------------------------------------------------------------------------------- - 27 -4.3.5 开路侦测测量设置 -------------------------------------------------------------------------------------------- - 28 -4.4 系统设置界面 .................................................................................................................................... - 29 -4.4.1 测试界面 --------------------------------------------------------------------------------------------------------- - 30 -4.4.2 环境界面 --------------------------------------------------------------------------------------------------------- - 34 -4.4.3 通讯设置界面--------------------------------------------------------------------------------------------------- - 35 -4.5 文件设置界面 .................................................................................................................................... - 36 -4.6 测试步骤 ............................................................................................................................................ - 37 -4.6.1 测试线/测试夹具清零---------------------------------------------------------------------------------------- - 37 -4.6.2 标准电容的采样 ----------------------------------------------------------------------------------------------- - 37 -4.6.3 连接被测件 ------------------------------------------------------------------------------------------------------ - 37 -4.6.4 测试程序 --------------------------------------------------------------------------------------------------------- - 38 -第五章接口与通讯 .......................................................................................................... - 40 -5.1 HANDLER接口 ................................................................................................................................... - 40 -5.1.1 外部控制线图例 ----------------------------------------------------------------------------------------------- - 41 -5.2 RS232C接口....................................................................................................................................... - 43 -5.2.1 与计算机通讯--------------------------------------------------------------------------------------------------- - 45 -5.2.2 软件协议 --------------------------------------------------------------------------------------------------------- - 45 -5.3 串口指令集说明 ................................................................................................................................ - 46 -5.3.1 SCPI指令集 ------------------------------------------------------------------------------------------------------ - 47 -5.3.2 DISPlay 子系统命令集-------------------------------------------------------------------------------------- - 47 -5.3.3 FUNCtion 子系统命令集 ------------------------------------------------------------------------------------ - 48 -5.3.4 SYSTem 子系统命令集 --------------------------------------------------------------------------------------- - 63 -5.3.5 MMEM 子系统命令集 --------------------------------------------------------------------------------------- - 71 -5.3.6 USB 子系统命令集-------------------------------------------------------------------------------------------- - 73 -5.3.7 FETCh 子系统命令集 ----------------------------------------------------------------------------------------- - 74 -5.3.8 其他控制命令集 ----------------------------------------------------------------------------------------------- - 75 -第六章技术指标 .............................................................................................................. - 76 -版本历史：本说明书将不断完善以利于使用。
BC107中文资料
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
open emitter open base open collector
Tamb ≤ 25 °C
THERMAL CHARACTERISTICS
SYMBOL
PARAMETER
CONDITIONS
Rth j-a Rth j-c
thermal resistance from junction to ambient note 1 thermal resistance from junction to case
DESCRIPTION emitter base collector, connected to the case
CY7C1041CV33-10ZXI中文资料
Industrial
100
95
Automotive-A
100
Automotive-E
Commercial/
10
10
Industrial
Automotive-A
10
Automotive-E
48-ball FBGA
(Top View)
12
3
4
5
6
CY7C1041CV33
-15
-20
Unit
15
20
ns
80
28
A6, E3, G2, H1, No Connect No Connects. This pin is not connected to the die
H6
17
G5
Input/Control Write Enable Input, active LOW. When selected LOW, a
A5 18 A6 19 A7 20 A8 21 A9 22
44 A17 43 A16 42 A15 41 OE
40 BHE 39 BLE
38 I/O15 37 I/O14 36 I/O13 35 I/O12 34 VSS 33 VCC 32 I/O11 31 I/O10 30 I/O9 29 I/O8 28 NC
WRITE is conducted. When selected HIGH, a READ is
conducted.
6
ห้องสมุดไป่ตู้B5
Input/Control Chip Enable Input, active LOW. When LOW, selects the chip.
When HIGH, deselects the chip.
CY7C63723-PC中文资料
元器件交易网CY7C63743CY7C63722/23CY7C63743enCoRe™ USBCombination Low-Speed USB & PS/2Peripheral ControllerTABLE OF CONTENTS1.0 FEATURES (5)2.0 FUNCTIONAL OVERVIEW (6)2.1 enCoRe USB - The New USB Standard (6)3.0 LOGIC BLOCK DIAGRAM (7)4.0 PIN CONFIGURATIONS (7)5.0 PIN ASSIGNMENTS (7)6.0 PROGRAMMING MODEL (8)6.1 Program Counter (PC) (8)6.2 8-bit Accumulator (A) (8)6.3 8-bit Index Register (X) (8)6.4 8-bit Program Stack Pointer (PSP) (8)6.5 8-bit Data Stack Pointer (DSP) (9)6.6 Address Modes (9)6.6.1 Data (9)6.6.2 Direct (9)6.6.3 Indexed (9)7.0 INSTRUCTION SET SUMMARY (10)8.0 MEMORY ORGANIZATION (11)8.1 Program Memory Organization (11)8.2 Data Memory Organization (12)8.3 I/O Register Summary (13)9.0 CLOCKING (14)9.1 Internal/External Oscillator Operation (15)9.2 External Oscillator (16)10.0 RESET (16)10.1 Low-voltage Reset (LVR) (16)10.2 Brown Out Reset (BOR) (16)10.3 Watchdog Reset (WDR) (17)11.0 SUSPEND MODE (17)11.1 Clocking Mode on Wake-up from Suspend (18)11.2 Wake-up Timer (18)12.0 GENERAL PURPOSE I/O PORTS (18)12.1 Auxiliary Input Port (21)13.0 USB SERIAL INTERFACE ENGINE (SIE) (22)13.1 USB Enumeration (22)13.2 USB Port Status and Control (22)14.0 USB DEVICE (24)14.1 USB Address Register (24)14.2 USB Control Endpoint (24)14.3 USB Non-control Endpoints (25)14.4 USB Endpoint Counter Registers (26)15.0 USB REGULATOR OUTPUT (27)16.0 PS/2 OPERATION (27)17.0 SERIAL PERIPHERAL INTERFACE (SPI) (28)17.1 Operation as an SPI Master (29)17.2 Master SCK Selection (29)17.3 Operation as an SPI Slave (29)17.4 SPI Status and Control (30)17.5 SPI Interrupt (31)17.6 SPI Modes for GPIO Pins (31)18.0 12-BIT FREE-RUNNING TIMER (31)19.0 TIMER CAPTURE REGISTERS (32)20.0 PROCESSOR STATUS AND CONTROL REGISTER (35)21.0 INTERRUPTS (36)21.1 Interrupt Vectors (37)21.2 Interrupt Latency (37)21.3 Interrupt Sources (37)22.0 USB MODE TABLES (42)23.0 REGISTER SUMMARY (47)24.0 ABSOLUTE MAXIMUM RATINGS (48)25.0 DC CHARACTERISTICS (48)26.0 SWITCHING CHARACTERISTICS (50)27.0 ORDERING INFORMATION (55)28.0 PACKAGE DIAGRAMS (55)LIST OF FIGURESFigure 8-1. Program Memory Space with Interrupt Vector Table (11)Figure 8-2. Data Memory Organization (12)Figure 9-1. Clock Oscillator On-chip Circuit (14)Figure 9-2. Clock Configuration Register (Address 0xF8) (14)Figure 10-1. Watchdog Reset (WDR, Address 0x26) (17)Figure 12-1. Block Diagram of GPIO Port (one pin shown) (19)Figure 12-2. Port 0 Data (Address 0x00) (19)Figure 12-3. Port 1 Data (Address 0x01) (19)Figure 12-4. GPIO Port 0 Mode0 Register (Address 0x0A) (20)Figure 12-5. GPIO Port 0 Mode1 Register (Address 0x0B) (20)Figure 12-6. GPIO Port 1 Mode0 Register (Address 0x0C) (20)Figure 12-7. GPIO Port 1 Mode1 Register (Address 0x0D) (20)Figure 12-8. Port 2 Data Register (Address 0x02) (21)Figure 13-1. USB Status and Control Register (Address 0x1F) (23)Figure 14-1. USB Device Address Register (Address 0x10) (24)Figure 14-2. Endpoint 0 Mode Register (Address 0x12) (25)Figure 14-3. USB Endpoint EP1, EP2 Mode Registers (Addresses 0x14 and 0x16) (26)Figure 14-4. Endpoint 0,1,2 Counter Registers (Addresses 0x11, 0x13 and 0x15) (26)Figure 17-1. SPI Block Diagram (28)Figure 16-1. Diagram of USB-PS/2 System Connections (28)Figure 17-2. SPI Data Register (Address 0x60) (29)Figure 17-3. SPI Control Register (Address 0x61) (30)Figure 17-4. SPI Data Timing (31)Figure 18-1. Timer LSB Register (Address 0x24) (31)Figure 18-2. Timer MSB Register (Address 0x25) (32)Figure 18-3. Timer Block Diagram (32)Figure 19-1. Capture Timers Block Diagram (33)Figure 19-2. Capture Timer A-Rising, Data Register (Address 0x40) (33)Figure 19-3. Capture Timer A-Falling, Data Register (Address 0x41) (34)Figure 19-4. Capture Timer B-Rising, Data Register (Address 0x42) (34)Figure 19-5. Capture Timer B-Falling, Data Register (Address 0x43) (34)Figure 19-6. Capture Timer Status Register (Address 0x45) (34)Figure 19-7. Capture Timer Configuration Register (Address 0x44) (34)Figure 20-1. Processor Status and Control Register (Address 0xFF) (35)Figure 21-1. Global Interrupt Enable Register (Address 0x20) (38)Figure 21-2. Endpoint Interrupt Enable Register (Address 0x21) (39)Figure 21-3. Interrupt Controller Logic Block Diagram (40)Figure 21-4. Port 0 Interrupt Enable Register (Address 0x04) (40)Figure 21-5. Port 1 Interrupt Enable Register (Address 0x05) (40)Figure 21-6. Port 0 Interrupt Polarity Register (Address 0x06) (41)Figure 21-7. Port 1 Interrupt Polarity Register (Address 0x07) (41)Figure 21-8. GPIO Interrupt Diagram (41)Figure 26-1. Clock Timing (51)Figure 26-2. USB Data Signal Timing (51)Figure 26-3. Receiver Jitter Tolerance (52)Figure 26-4. Differential to EOP Transition Skew and EOP Width (52)Figure 26-5. Differential Data Jitter (52)Figure 26-7. SPI Slave Timing, CPHA = 0 (53)Figure 26-6. SPI Master Timing, CPHA = 0 (53)Figure 26-8. SPI Master Timing, CPHA = 1 (54)Figure 26-9. SPI Slave Timing, CPHA = 1 (54)LIST OF TABLESTable 8-1. I/O Register Summary (13)Table 11-1. Wake-up Timer Adjust Settings (18)Table 12-1. Ports 0 and 1 Output Control Truth Table (21)Table 13-1. Control Modes to Force D+/D– Outputs (24)Table 17-1. SPI Pin Assignments (31)Table 19-1. Capture Timer Prescalar Settings (Step size and range for FCLK = 6 MHz) (35)Table 21-1. Interrupt Vector Assignments (37)Table 22-1. USB Register Mode Encoding for Control and Non-Control Endpoints (42)Table 22-2. Decode table for Table 22-3: “Details of Modes for Differing Traffic Conditions” (44)Table 22-3. Details of Modes for Differing Traffic Conditions (45)Table 28-1. CY7C63722-XC Probe Pad Coordinates in microns ((0,0) to bond pad centers) (57)1.0 Features•enCoRe™ USB - enhanced Component Reduction—Internal oscillator eliminates the need for an external crystal or resonator—Interface can auto-configure to operate as PS/2 or USB without the need for external components to switch between modes (no GPIO pins needed to manage dual mode capability)—Internal 3.3V regulator for USB pull-up resistor—Configurable GPIO for real-world interface without external components•Flexible, cost-effective solution for applications that combine PS/2 and low-speed USB, such as mice, gamepads, joysticks, and many others.•USB Specification Compliance—Conforms to USB Specification, Version 2.0—Conforms to USB HID Specification, Version 1.1—Supports 1 Low-Speed USB device address and 3 data endpoints—Integrated USB transceiver—3.3V regulated output for USB pull-up resistor•8-bit RISC microcontroller—Harvard architecture—6-MHz external ceramic resonator or internal clock mode—12-MHz internal CPU clock—Internal memory—256 bytes of RAM—8 Kbytes of EPROM—Interface can auto-configure to operate as PS/2 or USB—No external components for switching between PS/2 and USB modes—No GPIO pins needed to manage dual mode capability•I/O ports—Up to 16 versatile General Purpose I/O (GPIO) pins, individually configurable—High current drive on any GPIO pin: 50 mA/pin current sink—Each GPIO pin supports high-impedance inputs, internal pull-ups, open drain outputs or traditional CMOS outputs —Maskable interrupts on all I/O pins•SPI serial communication block—Master or slave operation—2 Mbit/s transfers•Four 8-bit Input Capture registers—Two registers each for two input pins—Capture timer setting with 5 prescaler settings—Separate registers for rising and falling edge capture—Simplifies interface to RF inputs for wireless applications•Internal low-power wake-up timer during suspend mode—Periodic wake-up with no external components•Optional 6-MHz internal oscillator mode—Allows fast start-up from suspend mode•Watchdog Reset (WDR)•Low-voltage Reset at 3.75V•Internal brown-out reset for suspend mode•Improved output drivers to reduce EMI•Operating voltage from 4.0V to 5.5VDC•Operating temperature from 0 to 70 degrees Celsius•CY7C63723 available in 18-pin SOIC, 18-pin PDIP•CY7C63743 available in 24-pin SOIC, 24-pin PDIP•CY7C63722 available in DIE form•Industry standard programmer support2.0 Functional Overview2.1enCoRe USB - The New USB StandardCypress has re-invented its leadership position in the low-speed USB market with a new family of innovative microcontrollers. Introducing...enCoRe USB—“enhanced Component Reduction.” Cypress has leveraged its design expertise in USB solutions to create a new family of low-speed USB microcontrollers that enables peripheral developers to design new products with a minimum number of components. At the heart of the enCoRe USB technology is the breakthrough design of a crystal-less oscillator. By integrating the oscillator into our chip, an external crystal or resonator is no longer needed. We have also integrated other external components commonly found in low-speed USB applications such as pull-up resistors, wake-up circuitry, and a 3.3V regulator. All of this adds up to a lower system cost.The CY7C637xx is an 8-bit RISC One Time Programmable (OTP) microcontroller. The instruction set has been optimized specif-ically for USB and PS/2 operations, although the microcontrollers can be used for a variety of other embedded applications. The CY7C637xx features up to 16 general purpose I/O (GPIO) pins to support USB, PS/2 and other applications. The I/O pins are grouped into two ports (Port 0 to 1) where each pin can be individually configured as inputs with internal pull-ups, open drain outputs, or traditional CMOS outputs with programmable drive strength of up to 50 mA output drive. Additionally, each I/O pin can be used to generate a GPIO interrupt to the microcontroller. Note the GPIO interrupts all share the same “GPIO” interrupt vector. The CY7C637xx microcontrollers feature an internal oscillator. With the presence of USB traffic, the internal oscillator can be set to precisely tune to USB timing requirements (6 MHz ±1.5%). Optionally, an external 6-MHz ceramic resonator can be used to provide a higher precision reference for USB operation. This clock generator reduces the clock-related noise emissions (EMI). The clock generator provides the 6- and 12-MHz clocks that remain internal to the microcontroller.The CY7C637xx has 8 Kbytes of EPROM and 256 bytes of data RAM for stack space, user variables, and USB FIFOs.These parts include low-voltage reset logic, a watchdog timer, a vectored interrupt controller, a 12-bit free-running timer, and capture timers. The low-voltage reset (LVR) logic detects when power is applied to the device, resets the logic to a known state, and begins executing instructions at EPROM address 0x0000. LVR will also reset the part when V CC drops below the operating voltage range. The watchdog timer can be used to ensure the firmware never gets stalled for more than approximately 8 ms. The microcontroller supports 10 maskable interrupts in the vectored interrupt controller. Interrupt sources include the USB Bus-Reset, the 128-µs and 1.024-ms outputs from the free-running timer, three USB endpoints, two capture timers, an internal wake-up timer and the GPIO ports. The timers bits cause periodic interrupts when enabled. The USB endpoints interrupt after USB transactions complete on the bus. The capture timers interrupt whenever a new timer value is saved due to a selected GPIO edge event. The GPIO ports have a level of masking to select which GPIO inputs can cause a GPIO interrupt. For additional flexibility, the input transition polarity that causes an interrupt is programmable for each GPIO pin. The interrupt polarity can be either rising or falling edge.The free-running 12-bit timer clocked at 1 MHz provides two interrupt sources as noted above (128 µs and 1.024 ms). The timer can be used to measure the duration of an event under firmware control by reading the timer at the start and end of an event, and subtracting the two values. The four capture timers save a programmable 8 bit range of the free-running timer when a GPIO edge occurs on the two capture pins (P0.0, P0.1).The CY7C637xx includes an integrated USB serial interface engine (SIE) that supports the integrated peripherals. The hardware supports one USB device address with three endpoints. The SIE allows the USB host to communicate with the function integrated into the microcontroller. A 3.3V regulated output pin provides a pull-up source for the external USB resistor on the D– pin.The USB D+ and D– USB pins can alternately be used as PS/2 SCLK and SDATA signals, so that products can be designed to respond to either USB or PS/2 modes of operation. PS/2 operation is supported with internal pull-up resistors on SCLK and SDATA, the ability to disable the regulator output pin, and an interrupt to signal the start of PS/2 activity. No external components are necessary for dual USB and PS/2 systems, and no GPIO pins need to be dedicated to switching between modes. Slow edge rates operate in both modes to reduce EMI.3.0 Logic Block Diagram4.0 Pin Configurations5.0 Pin AssignmentsNameI/O CY7C63723CY7C63743CY7C63722Description18-Pin 24-Pin 25-Pad D–/SDATA,D+/SCLK I/O 121315161617USB differential data lines (D– and D+), or PS/2 clock and data signals (SDATA and SCLK)P0[7:0]I/O1, 2, 3, 4,15, 16, 17, 181, 2, 3, 4,21, 22, 23, 241, 2, 3, 4,22, 23, 24, 25GPIO Port 0 capable of sinking up to 50 mA/pin, or sinking controlled low or high programmable current.Can also source 2 mA current, provide a resistive pull-up, or serve as a high-impedance input. P0.0 and P0.1 provide inputs to Capture Timers A and B, respec-tively.P1[7:0]I/O5, 145, 6, 7, 8,17, 18, 19, 205, 6, 7, 8,18, 19, 20, 21IO Port 1 capable of sinking up to 50 mA/pin, or sinking controlled low or high programmable current. Can alsosource 2 mA current, provide a resistive pull-up, or serve as a high-impedance input.Wake-Up 12-bit Timer USB &D+,D–P1.0–P1.7Interrupt ControllerPort 0P0.0–P0.7GPIO8-bit RISC Xtal RAM 256 Byte EPROM 8K ByteCoreBrown-out Reset XcvrWatch Timer Dog 3.3V Port 1GPIO Capture TimersUSB Engine PS/2Internal Oscillator Oscillator Low ResetVoltage RegulatorTimerSPIXTALOUTXTALIN/P2.1VREG/P2.01234569111516171819202221P0.0P0.1P0.2P0.3P1.0P1.2VSS VREG/P2.0P0.6P1.5P1.1P1.3D+/SCLK P1.7D–/SDATA VCC14P0.710VPPXTALIN/P2.1XTALOUT121378P1.4P1.62423P0.4P0.524-pin SOIC/PDIPCY7C6374312346781011121315161817P0.0P0.1P0.2P0.3VSS VREG/P2.0P0.4P0.6P0.7D+/SCLK D–/SDATA VCC18-pin SOIC/PDIPP0.59VPPXTALIN/P2.1XTALOUTCY7C63723514P1.0P1.1Top View4 5 6 7 8 93 P 0.21 P 0.0 2 P 0.125 P 0.4 24 P 0.523 P 0.622 21 20 19 1811121314151617P0.3P1.0P1.2P1.4P1.6 VSS VSS V P P X T A L I N /P 2.1V R E G X T A L O U T V C C D -/S D A T A D+/SCLK P0.7P1.1P1.3P1.5P1.7CY7C63722-XCDIE106.0 Programming ModelRefer to the CYASM Assembler User’s Guide for more details on firmware operation with the CY7C637xx microcontrollers.6.1Program Counter (PC)The 14-bit program counter (PC) allows access for up to 8 Kbytes of EPROM using the CY7C637xx architecture. The program counter is cleared during reset, such that the first instruction executed after a reset is at address 0x0000. This instruction is typically a jump instruction to a reset handler that initializes the application.The lower 8 bits of the program counter are incremented as instructions are loaded and executed. The upper 6 bits of the program counter are incremented by executing an XPAGE instruction. As a result, the last instruction executed within a 256-byte “page”of sequential code should be an XPAGE instruction. The assembler directive “XPAGEON” will cause the assembler to insert XPAGE instructions automatically. As instructions can be either one or two bytes long, the assembler may occasionally need to insert a NOP followed by an XPAGE for correct execution.The program counter of the next instruction to be executed, carry flag, and zero flag are saved as two bytes on the program stack during an interrupt acknowledge or a CALL instruction. The program counter, carry flag, and zero flag are restored from the program stack only during a RETI instruction.Please note the program counter cannot be accessed directly by the firmware. The program stack can be examined by reading SRAM from location 0x00 and up.6.28-bit Accumulator (A)The accumulator is the general-purpose, do everything register in the architecture where results are usually calculated.6.38-bit Index Register (X)The index register “X” is available to the firmware as an auxiliary accumulator. The X register also allows the processor to perform indexed operations by loading an index value into X.6.48-bit Program Stack Pointer (PSP)During a reset, the program stack pointer (PSP) is set to zero. This means the program “stack” starts at RAM address 0x00 and “grows” upward from there. Note that the program stack pointer is directly addressable under firmware control, using the MOV PSP ,A instruction. The PSP supports interrupt service under hardware control and CALL, RET, and RETI instructions under firmware control.During an interrupt acknowledge, interrupts are disabled and the program counter, carry flag, and zero flag are written as two bytes of data memory. The first byte is stored in the memory addressed by the program stack pointer, then the PSP is incremented.The second byte is stored in memory addressed by the program stack pointer and the PSP is incremented again. The net effect is to store the program counter and flags on the program “stack” and increment the program stack pointer by two.The return from interrupt (RETI) instruction decrements the program stack pointer, then restores the second byte from memory addressed by the PSP . The program stack pointer is decremented again and the first byte is restored from memory addressed by the PSP . After the program counter and flags have been restored from stack, the interrupts are enabled. The effect is to restore the program counter and flags from the program stack, decrement the program stack pointer by two, and re-enable interrupts.The call subroutine (CALL) instruction stores the program counter and flags on the program stack and increments the PSP by two.XTALIN/P2.1IN 912136-MHz ceramic resonator or external clock input, or P2.1 inputXTALOUT OUT1013146-MHz ceramic resonator return pin or internal oscillator outputV PP 71011Programming voltage supply, ground for normal operation V CC111415Voltage supplyVREG/P2.0 81112Voltage supply for 1.3-k Ω USB pull-up resistor (3.3V nominal). Also serves as P2.0 input.V SS699, 10Ground5.0 Pin Assignments (continued)NameI/O CY7C63723CY7C63743CY7C63722Description18-Pin 24-Pin 25-PadThe return from subroutine (RET) instruction restores the program counter, but not the flags, from program stack and decrements the PSP by two.Note that there are restrictions in using the JMP, CALL, and INDEX instructions across the 4-KB boundary of the program memory. Refer to the CYASM Assembler User’s Guide for a detailed description.6.58-bit Data Stack Pointer (DSP)The data stack pointer (DSP) supports PUSH and POP instructions that use the data stack for temporary storage. A PUSH instruction will pre-decrement the DSP, then write data to the memory location addressed by the DSP. A POP instruction will read data from the memory location addressed by the DSP, then post-increment the DSP.During a reset, the Data Stack Pointer will be set to zero. A PUSH instruction when DSP equals zero will write data at the top of the data RAM (address 0xFF). This would write data to the memory area reserved for a FIFO for USB endpoint 0. In non-USB applications, this works fine and is not a problem.For USB applications, the firmware should set the DSP to an appropriate location to avoid a memory conflict with RAM dedicated to USB FIFOs. The memory requirements for the USB endpoints are shown in Section 8.2. For example, assembly instructions to set the DSP to 20h (giving 32 bytes for program and data stack combined) are shown below:MOV A,20h; Move 20 hex into Accumulator (must be D8h or less to avoid USB FIFOs)SWAP A,DSP; swap accumulator value into DSP register6.6Address ModesThe CY7C637xx microcontrollers support three addressing modes for instructions that require data operands: data, direct, and indexed.6.6.1DataThe “Data” address mode refers to a data operand that is actually a constant encoded in the instruction. As an example, consider the instruction that loads A with the constant 0x30:•MOV A, 30hThis instruction will require two bytes of code where the first byte identifies the “MOV A” instruction with a data operand as the second byte. The second byte of the instruction will be the constant “0xE8h”. A constant may be referred to by name if a prior “EQU” statement assigns the constant value to the name. For example, the following code is equivalent to the example shown above:•DSPINIT: EQU 30h•MOV A,DSPINIT6.6.2Direct“Direct” address mode is used when the data operand is a variable stored in SRAM. In that case, the one byte address of the variable is encoded in the instruction. As an example, consider an instruction that loads A with the contents of memory address location 0x10h:•MOV A, [10h]In normal usage, variable names are assigned to variable addresses using “EQU” statements to improve the readability of the assembler source code. As an example, the following code is equivalent to the example shown above:•buttons: EQU 10h•MOV A,[buttons]6.6.3Indexed“Indexed” address mode allows the firmware to manipulate arrays of data stored in SRAM. The address of the data operand is the sum of a constant encoded in the instruction and the contents of the “X” register. In normal usage, the constant will be the “base” address of an array of data and the X register will contain an index that indicates which element of the array is actually addressed:•array: EQU 10h•MOV X,3•MOV A,[x+array]This would have the effect of loading A with the fourth element of the SRAM “array” that begins at address 0x10h. The fourth element would be at address 0x13h.7.0 Instruction Set SummaryRefer to the CYASM Assembler User’s Guide for detailed information on these instructions. Note that conditional jump instructions (i.e., JC, JNC, JZ, JNZ) take 5 cycles if jump is taken, 4 cycles if no jump.MNEMONIC Operand Opcode Cycles MNEMONIC Operand Opcode Cycles HALT 007NOP 204ADD A,expr data014INC A acc214ADD A,[expr] direct026INC X x224ADD A,[X+expr] index037INC [expr] direct237ADC A,expr data044INC [X+expr] index248ADC A,[expr] direct056DEC A acc254ADC A,[X+expr] index067DEC X x264SUB A,expr data074DEC [expr] direct277SUB A,[expr] direct086DEC [X+expr] index288SUB A,[X+expr] index097IORD expr address295SBB A,expr data0A4IOWR expr address2A5SBB A,[expr] direct0B6POP A2B4SBB A,[X+expr] index0C7POP X2C4OR A,expr data0D4PUSH A2D5OR A,[expr] direct0E6PUSH X2E5OR A,[X+expr] index0F7SWAP A,X2F5AND A,expr data104SWAP A,DSP305AND A,[expr] direct116MOV [expr],A direct315AND A,[X+expr] index127MOV [X+expr],A index326XOR A,expr data134OR [expr],A direct337XOR A,[expr] direct146OR [X+expr],A index348XOR A,[X+expr] index157AND [expr],A direct357CMP A,expr data165AND [X+expr],A index368CMP A,[expr] direct177XOR [expr],A direct377CMP A,[X+expr] index188XOR [X+expr],A index388MOV A,expr data194IOWX [X+expr] index396MOV A,[expr] direct1A5CPL 3A4MOV A,[X+expr] index1B6ASL 3B4MOV X,expr data1C4ASR 3C4MOV X,[expr] direct1D5RLC 3D4reserved 1E RRC 3E4XPAGE 1F4RET 3F8MOV A,X404DI 704MOV X,A414EI 724MOV PSP,A604RETI 738CALL addr50 - 5F10JMP addr80-8F5JC addr C0-CF 5 (or 4) CALL addr90-9F10JNC addr D0-DF 5 (or 4)JZ addr A0-AF 5 (or 4)JACC addr E0-EF7JNZ addr B0-BF 5 (or 4)INDEX addr F0-FF148.0 Memory Organization8.1Program Memory Organization[1]After reset Address14 -bit PC0x0000Program execution begins here after a reset.0x0002USB Bus Reset interrupt vector0x0004128-µs timer interrupt vector0x0006 1.024-ms timer interrupt vector0x0008USB endpoint 0 interrupt vector0x000A USB endpoint 1 interrupt vector0x000C USB endpoint 2 interrupt vector0x000E SPI interrupt vector0x0010Capture timer A interrupt Vector0x0012Capture timer B interrupt vector0x0014GPIO interrupt vector0x0016Wake-up interrupt vector0x0018Program Memory begins here0x1FDF8 KB PROM ends here (8K - 32 bytes). See Note below Figure 8-1. Program Memory Space with Interrupt Vector TableNote:1.The upper 32 bytes of the 8K PROM are reserved. Therefore, the user’s program must not overwrite this space.8.2Data Memory OrganizationThe CY7C637xx microcontrollers provide 256 bytes of data RAM. In normal usage, the SRAM is partitioned into four areas: program stack, data stack, user variables and USB endpoint FIFOs as shown below:After reset Address8-bit DSP8-bit PSP0x00Program Stack Growth(User’s firmware movesDSP)8-bit DSP User Selected Data Stack GrowthUser Variables0xE8USB FIFO for Address A endpoint 20xF0USB FIFO for Address A endpoint 10xF8USB FIFO for Address A endpoint 0Top of RAM Memory0xFFFigure 8-2. Data Memory Organization8.3I/O Register SummaryI/O registers are accessed via the I/O Read (IORD) and I/O Write (IOWR, IOWX) instructions. IORD reads the selected port into the accumulator. IOWR writes data from the accumulator to the selected port. Indexed I/O Write (IOWX) adds the contents of X to the address in the instruction to form the port address and writes data from the accumulator to the specified port. Note that specifying address 0 with IOWX (e.g., IOWX 0h) means the I/O port is selected solely by the contents of X.Note:All bits of all registers are cleared to all zeros on reset, except the Processor Status and Control Register (Figure20-1). All registers not listed are reserved, and should never be written by firmware. All bits marked as reserved should always be written as 0 and be treated as undefined by reads.Table 8-1. I/O Register SummaryRegister Name I/O Address Read/Write Function Fig. Port 0 Data0x00R/W GPIO Port 012-2 Port 1 Data0x01R/W GPIO Port 112-3 Port 2 Data0x02R Auxiliary input register for D+, D–, VREG, XTALIN 12-8 Port 0 Interrupt Enable0x04W Interrupt enable for pins in Port 021-4 Port 1 Interrupt Enable0x05W Interrupt enable for pins in Port 121-5 Port 0 Interrupt Polarity 0x06W Interrupt polarity for pins in Port 021-6 Port 1 Interrupt Polarity 0x07W Interrupt polarity for pins in Port 121-7 Port 0 Mode0 0x0A W Controls output configuration for Port 012-4 Port 0 Mode10x0B W12-5 Port 1 Mode00x0C W Controls output configuration for Port 112-6 Port 1 Mode10x0D W12-7 USB Device Address0x10R/W USB Device Address register14-1 EP0 Counter Register0x11R/W USB Endpoint 0 counter register14-4 EP0 Mode Register0x12R/W USB Endpoint 0 configuration register14-2 EP1 Counter Register0x13R/W USB Endpoint 1 counter register14-4 EP1 Mode Register0x14R/W USB Endpoint 1 configuration register14-3 EP2 Counter Register0x15R/W USB Endpoint 2 counter register14-4 EP2 Mode Register0x16R/W USB Endpoint 2 configuration register14-3 USB Status & Control0x1F R/W USB status and control register13-1 Global Interrupt Enable0x20R/W Global interrupt enable register21-1 Endpoint Interrupt Enable0x21R/W USB endpoint interrupt enables21-2 Timer (LSB)0x24R Lower 8 bits of free-running timer (1 MHz)18-1 Timer (MSB)0x25R Upper 4 bits of free-running timer18-2 WDR Clear0x26W Watchdog Reset clear-Capture Timer A Rising0x40R Rising edge Capture Timer A data register19-2 Capture Timer A Falling0x41R Falling edge Capture Timer A data register19-3 Capture Timer B Rising0x42R Rising edge Capture Timer B data register19-4 Capture Timer B Falling0x43R Falling edge Capture Timer B data register19-5 Capture TImer Configuration0x44R/W Capture Timer configuration register19-7 Capture Timer Status0x45R Capture Timer status register19-6 SPI Data0x60R/W SPI read and write data register17-2 SPI Control0x61R/W SPI status and control register17-3 Clock Configuration0xF8R/W Internal / External Clock configuration register9-2 Processor Status & Control0xFF R/W Processor status and control20-1。
CY7C1411AV18资料
Errata Revision: *CMay 02, 2007RAM9 QDR-I/DDR-I/QDR-II/DDR- II ErrataCY7C129*DV18/CY7C130*DV25CY7C130*BV18/CY7C130*BV25/CY7C132*BV25CY7C131*BV18 / CY7C132*BV18/CY7C139*BV18CY7C191*BV18/CY7C141*AV18 / CY7C142*AV18/CY7C151*V18 /CY7C152*V18This document describes the DOFF issue for QDRII/DDRII and the Output Buffer and JTAG issues for QDRI/DDRI/QDRII/DDRII. Details include trigger conditions, possible workarounds and silicon revision applicability.This document should be used to compare to the respective datasheet for the devices to fully describe the device functionality.Please contact your local Cypress Sales Representative for availability of the fixed devices and any other questions.Devices AffectedTable 1. List of Affected devicesProduct StatusAll of the above densities and revisions are available in sample as well as production quantities.QDR/DDR DOFF Pin, Output Buffer and JTAG Issues Errata SummaryThe following table defines the issues and the fix status for the different devices which are affected.Density & Revision Part Numbers Architecture 9Mb - Ram9(90 nm)CY7C130*DV25QDRI/DDRI 9Mb - Ram9(90 nm)CY7C129*DV18QDRII 18Mb - Ram9(90nm)CY7C130*BV18CY7C130*BV25CY7C132*BV25QDRI/DDRI18Mb - Ram9(90nm)CY7C131*BV18CY7C132*BV18CY7C139*BV18CY7C191*BV18QDRII/DDRII36Mb - Ram9(90nm)CY7C141*AV18CY7C142*AV18QDRII/DDRII 72Mb -Ram9(90nm)CY7C151*V18CY7C152*V18QDRII/DDRIIItemIssueDeviceFix Status1.DOFF pin is used for enabling/dis-abling the DLL circuitry within the SRAM. To enable the DLL circuitry, DOFF pin must be externally tied HIGH. The QDR-II/DDR-II devices have an internal pull down resistor of ~5K . The value of the external pull-up resistor should be 500 or less in order to ensure DLL is enabled.9Mb - “D” Rev - Ram918Mb - “B” Rev - Ram936Mb - “A” Rev - Ram972Mb - Ram9QDR-II/DDR-II DevicesThe fix involved removing the in-ternal pull-down resistor on the DOFF pin. The fix has been im-plemented on the new revision and is now available.ΩΩTable 2.Issue Definition and fix status for different devices1. DOFF Pin Issue•ISSUE DEFINITIONThis issue involves the DLL not turning ON properly if a large resistor is used (eg:-10K ) as an external pullup resistor to enable the DLL. If a 10K or higher pullup resistor is used externally, the voltage on DOFF is not high enough to enable the DLL.•PARAMETERS AFFECTEDThe functionality of the device will be affected because of the DLL is not turning ON properly. When the DLL is enabled, all AC and DC parameters on the datasheet are met. •TRIGGER CONDITION(S)Having a 10K or higher external pullup resistor for disabling the DOFF pin.•SCOPE OF IMPACTThis issue will alter the normal functionality of the QDRII/DDRII devices when the DLL is disabled.•EXPLANATION OF ISSUEFigure 1 shows the DOFF pin circuit with an internal 5K internal resistor. The fix planned is to disable the internal 5K leaker.•WORKAROUND2.O/P Buffer enters a locked up unde-fined state after controls or clocks are left floating. No proper read/write access can be done on the device until a dummy read is performed.9Mb - “D” Rev - Ram918Mb - “B” Rev - Ram936Mb - “A” Rev - Ram972Mb - Ram9QDR-I/DDR-I/QDR-II/DDR-II Devices The fix has been implemented onthe new revision and is now avail-able.3.The EXTEST function in the JTAG test fails when input K clock is floating in the JTAG mode.9Mb - “D” Rev - Ram918Mb - “B” Rev - Ram936Mb - “A” Rev - Ram972Mb - Ram9QDR-I/DDR-I/QDR-II/DDR-II DevicesThe fix involved bypassing the ZQ circuitry in JTAG mode. This was done by overriding the ZQ circuit-ry by the JTAG signal. The fix has been implemented on the new re-vision and is now available.Figure 1.DOFF pin with the 5K internal resistorItemIssueDeviceFix StatusΩΩΩΩΩΩThe workaround is to have a low value of external pullup resistor for the DOFF pin (recommended value is <500). When DOFF pins from multiple QDR devices are connected through the same pull-up resistors on the board, it is recommended that this DOFF pin be directly connected to Vdd due to the lower effective resistance since the "leakers" are in parallel.Figure 2 shows the proposed workaround and the fix planned.•FIXSTATUSFix involved removing the internal pull-down resistor on the DOFF pin. The fix has been implemented on the new revision and is now available. The new revision is an increment of the existing revision. The following table lists the devices affected, current revision and the new revision after the fix.Table 3.List of Affected Devices and the new revison2.Output Buffer IssueFigure 2.Proposed workaround with the 500 external pullupCurrent Revision New Revision after the FixCY7C129*DV18CY7C129*EV18CY7C131*BV18CY7C131*CV18CY7C132*BV18CY7C132*CV18CY7C139*BV18CY7C139*CV18CY7C191*BV18CY7C191*CV18CY7C141*AV18CY7C141*BV18CY7C142*AV18CY7C142*BV18CY7C151*V18CY7C151*AV18CY7C152*V18CY7C152*AV18ΩΩ•ISSUE DEFINITIONThis issue involves the output buffer entering an unidentified state when the input signals (only Control signals or Clocks) are floating during reset or initialization of the memory controller after power up. •PARAMETERS AFFECTEDNo timing parameters are affected. The device may drive the outputs even though the read operation is not enabled. A dummy read is performed to clear this condition.•TRIGGER CONDITION(S)Input signals(namely RPS# for QDR-I/QDRII , WE# and LD# for DDR-I/DDRII) or Clocks (K/K# and/or C/C#) are floating during reset or initialization of the memory controller after power up.•SCOPE OF IMPACTThis issue will jeopardize any number of writes or reads which take place after the controls or clock are left floating. This can occur anywhere in the SRAM access ( all the way from power up of the memory device to transitions taking place for read/write accesses to the memory device) if the above trigger conditions are met.•EXPLANATION OF ISSUEFigure 3 shows the output register Reset circuit with an SR Latch circled. This latch has two inputs with one of them coming from some logic affected by the clock and RPS#(QDR) or WE# and LD#(DDR).The issue happens when clocks are glitching/toggling with controls floating. This will cause the SR latch to be taken into an unidentified state. The SR Latch will need to be reset by a dummy read operation if this happens. Array•WORKAROUNDThis is viable only if the customer has the trigger conditions met during reset or initialization of the memory controller after power up. In order for the workaround to perform properly, Cypress recommends the insertion of a minimum of 16 “dummy” READ operations to every SRAM device on the board prior to writing any meaningful data into the SRAM. After this one “dummy” READ operation, the device will perform properly.“Dummy” READ is defined as a read operation to the device that is not meant to retrieve required data. The “dummy” READ can be to any address location in the SRAM. Refer to Figure 4 for the dummy read implemen-tation.In systems where multiple SRAMs with multiple RPS# lines are used, a dummy read operation will have to be performed on every SRAM on the board. Below is an example sequence of events that can be performed before valid access can be performed on the SRAM.1) Initialize the Memory Controller2) Assert RPS# Low for each of the memory devicesNote:For all devices with x9 bus configuration, the following sequence needs to be performed:1) For the 72M / 36M / 18M x9 devices drive address pin A2 / A10 / A3 low respectively and perform dummyread.2) For the 72M / 36M / 18M x9 devices drive address pin A2 / A10 / A3 high respectively and perform dummyread.If the customer has the trigger conditions met during normal access to the memory then there is no workaround at this point.•FIX STATUSThe fix has been implemented on the new revision and is now available. The new revision is an increment of the existing revision. Please refer to Table 4 for the list of devices affected, current revision and the new revision after the fix.3. JTAG Mode Issue•ISSUE DEFINITIONIf the input clock (K Clock) is left floating when the device is in JTAG mode, spurious high frequency noise on this input can be interpreted by the device as valid clocks. This could cause the impedance matching circuitry (ZQ) on the QDR/DDR devices to periodically load itself with incorrect values. These incorrect values in the ZQ register could force the outputs into a High-Impedance state. The ZQ circuitry requires at least 1000 valid K clock cycles to drive the outputs from high impedance to low impedance levels.•PARAMETERS AFFECTEDThis issue only affects the EXTEST command when the device is in the JTAG mode. The normal functionality of the device will not be affected.•TRIGGER CONDITION(S)EXTEST command executed immediately after power-up without providing any K clock cycles.•SCOPE OF IMPACTThis issue only impacts the EXTEST command when device is tested in the JTAG mode. Normal functionality of the device is not affected. •EXPLANATION OF ISSUEImpedance matching circuitry (ZQ) is present on the QDR/DDR devices to set the desired impedance on the outputs. This ZQ circuitry is updated every 1000 clock cycles of K clock to ensure that the impedance of the O/P is set to valid state. However, when the device is operated in the JTAG mode immediately after power-up, high frequency noise on the input K clock can be treated by the ZQ circuitry as valid clocks thereby setting the outputs in to a high-impedance mode. If a minimum of 1000 valid K clocks are applied before performing the JTAG test, this should clear the ZQ circuitry and ensure that the outputs are driven to valid impedance levels.•WORKAROUNDElimination of the issue: After power-up, before any valid operations are performed on the device, insert a minimum of 1000 valid clocks on K input.•FIX STATUSThe fix involved bypassing the ZQ circuitry in JTAG mode. This was done by overriding the ZQ circuitry by the JTAG signal. The fix has been implemented on the new revision and is now available. The new revision is an increment of the existing revision. Please refer to Table 4 for the list of devices affected, current revision and the new revision after the fix..Table 4.List of Affected devices and the new revisionCurrent Revision New Revision after the FixCY7C129*DV18CY7C129*EV18CY7C130*DV25CY7C130*EV25CY7C130*BV18CY7C130*CV18CY7C130*BV25CY7C130*CV25CY7C132*BV25CY7C132*CV25CY7C131*BV18CY7C131*CV18CY7C132*BV18CY7C132*CV18CY7C139*BV18CY7C139*CV18CY7C191*BV18CY7C191*CV18CY7C141*AV18CY7C141*BV18CY7C142*AV18CY7C142*BV18CY7C151*V18CY7C151*AV18CY7C152*V18CY7C152*AV18ReferencesAll 90nm QDRI/DDRI/QDRII/DDRII datasheets:-Table 5.List of Datasheet spec# for the Affected devicesSpec#Part#DensityArchitecture38-05628CY7C1304DV259-MBIT QDR(TM) SRAM 4-WORD BURST 38-05632CY7C1308DV259-MBIT DDR-I SRAM 4-WORD BURST 001-00350CY7C1292DV18/1294DV189-MBIT QDR- II(TM) SRAM 2-WORD BURST 38-05621CY7C1316BV18/1916BV18/1318BV18/1320BV1818-MBIT DDR-II SRAM 2-WORD BURST 38-05622CY7C1317BV18/1917BV18/1319BV18/1321BV1818-MBIT DDR-II SRAM 4-WORD BURST 38-05623CY7C1392BV18/1393BV18/1394BV1818-MBIT DDR-II SIO SRAM 2-WORD BURST 38-05631CY7C1323BV2518-MBIT DDR-I SRAM 4-WORD BURST 38-05630CY7C1305BV25/1307BV2518-MBIT QDR(TM) SRAM 4-WORD BURST 38-05627CY7C1303BV25/1306BV2518-MBIT QDR(TM) SRAM 2-WORD BURST 38-05629CY7C1305BV18/1307BV1818-MBIT QDR(TM) SRAM 4-WORD BURST 38-05626CY7C1303BV18/1306BV1818-MBIT QDR(TM) SRAM 2-WORD BURST 38-05619CY7C1310BV18/1910BV18/1312BV18/1314BV1818-MBIT QDR - II (TM) SRAM 2-WORD BURST 38-05620CY7C1311BV18/1911BV18/1313BV18/1315BV1818-MBIT QDR - II SRAM 4-WORD BURST 38-05615CY7C1410AV18/1425AV18/1412AV18/1414AV1836-MBIT QDR-II(TM) SRAM 2-WORD BURST 38-05614CY7C1411AV18/1426AV18/1413AV18/1415AV1836-MBIT QDR(TM)-II SRAM 4-WORD BURST 38-05616CY7C1416AV18/1427AV18/1418AV18/1420AV1836-MBIT DDR-II SRAM 2-WORD BURST 38-05618CY7C1417AV18/1428AV18/1419AV18/1421AV1836-MBIT DDR-II SRAM 4-WORD BURST 38-05617CY7C1422AV18/1429AV18/1423AV18/1424AV1836-MBIT DDR-II SIO SRAM 2-WORD BURST 38-05489CY7C1510V18/1525V18/1512V18/1514V1872-MBIT QDR-II SRAM 2-WORD BURST 38-05363CY7C1511V18/1526V18/1513V18/1515V1872-MBIT QDR(TM)-II SRAM 4-WORD BURST 38-05563CY7C1516V18/1527V18/1518V18/1520V1872-MBIT DDR-II SRAM 2-WORD BURST 38-05565CY7C1517V18/1528V18/1519V18/1521V1872-MBIT DDR-II SRAM 4-WORD BURST 38-05564CY7C1522V18/1529V18/1523V18/1524V1872-MBITDDR-II SIO SRAM 2-WORD BURSTDocument History PageDocument Title: RAM9 QDR-I/DDR-I/QDR-II/DDR- II Errata Document #: 001-06217 Rev. *CREV.ECN NO.IssueDateOrig. ofChange Description of Change**419849See ECN REF New errata for Ram9 QDR2/DDR2 SRAMs.*A493936See ECN QKS Added Output buffer and JTAG mode issues, Item#2 and #3Added 9Mb QDR-II Burst of 2 and QDR-1/DDR-I part numbers.*B733176See ECN NJY Added missing part numbers in the title for Spec#’s 38-05615,38-05614,38-05363,38-05563 on Table 5 on page 7.*C1030020 See ECN TBE Updated the fix status of the three issues, and modified the description forthe Output Buffer workaround for x9 devices on page 5.。
RT1710S USB Type-C Cable ID 商品说明书
RT1710SCopyright © 2017 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.DS1710S-00 February 2017Cable ID for USB Type-C CablesGeneral DescriptionThe RT1710S is a Type-C cable ID for active and passive cables. All USB Full-Featured Type-C cables shall be electronically marked. Electronically marked cables shall support USB Power Delivery Structured VDM Discover Identity command directed to SOP’. This provides a method to determine the characteristics of the cable, e.g. its current carrying capability, its performance, vendor identification, etc. This may be referred to as the USB Type-C Cable ID function. The RT1710S is available in a WDFN-8L 2x2 package.Ordering InformationG : Green (Halogen Free and Pb Free)Note :Richtek products are :④ RoHScompliant and compatible with the current requirements of IPC/JEDEC J-STD-020.④ Suitablefor use in SnPb or Pb-free solderingprocesses.Marking Information42 : Product CodeW : Date CodeFeatures● Support SOP ’ Communication ● Integrated Transceiver (BMC PHY) ● Embedded Both Side RA Resistor ● Embedded Both Side ISO Diode ● Embedded MTP●Support Multi-Time Writable Memory to Store VDM Data●Support 4V to 5.5V Operation on VCON1/VCON2 Pin●Built-in Slew Rate Control for BMC Signal to Reduce the Effect of EMI●Support Custom Structured VDM Writing Through CC Pin● Support I 2C Bus for Programming VDM Data ●8-Lead WDFN PackageApplications●USB Full-Featured Type-C CablesPin Configuration(TOP VIEW)VCON1CCIN NC(DG0)NC(DG1)VCON2SDAGND SCL 76512348G N D9WDFN-8L 2x2RT1710STypical Application CircuitElectronically Marked Cable with VCONN connected through the cableElectronically Marked Cable with SOP’ at both endsRT1710SFunctional Block DiagramOperationSOP’ Communication is recognized by electronics in one Cable Plug (which may be attached to either the UFP or DFP). SOP Communication between the Port Partners is not recognized by the Cable Plug. the term Cable Plug in the SOP’ Communication case is used to represent a logical entity (RT1710S) in the cable which is capable of PD Communication. Both SOP Communication and SOP’ Communication take place over a single wire (CC pin). For a product which does not recognize SOP’ Packets, this will look like a non-idle channel.RT1710SCopyright © 2017 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.Absolute Maximum Ratings (Note1)● VCON1/VCON2-------------------------------------------------------------------------------------------------------- -0.3V to 6V ●Power Dissipation, P D @ T A = 25︒CWDFN-8L 2x2 ---------------------------------------------------------------------------------------------------------- 2.19W ●Package Thermal Resistance (Note 2)WDFN-8L 2x2, θJA ---------------------------------------------------------------------------------------------------- 45.5°C/W WDFN-8L 2x2, θJC ---------------------------------------------------------------------------------------------------- 11.5°C/W ● Lead Temperature (Soldering, 10 sec.) -------------------------------------------------------------------------- 260︒C ● Junction Temperature ------------------------------------------------------------------------------------------------ 150︒C● Storage Temperature Range --------------------------------------------------------------------------------------- -65︒C to 150︒C ●ESD Susceptibility (Note 3)HBM (Human Body Model) ----------------------------------------------------------------------------------------- 8kV MM (Machine Model) ------------------------------------------------------------------------------------------------- 200VRecommended Operating Conditions (Note 4)● Supply Input Voltage ------------------------------------------------------------------------------------------------- 4V to 5.5V ● Ambient Temperature Range--------------------------------------------------------------------------------------- -40︒C to 85︒C ●Junction Temperature Range -------------------------------------------------------------------------------------- -40︒C to 125︒CElectrical Characteristics(V DD = 5V, T A = 25︒C, unless otherwise specified)RT1710SNote 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These arestress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Note 2. θJA is measured under natural convection (still air) at T A = 25°C with the component mounted on a higheffective-thermal-conductivity four-layer test board on a JEDEC 51-7 thermal measurement standard. θJC is measured at the exposed pad of the package. Note 3. Devices are ESD sensitive. Handling precaution recommended. Note 4. The device is not guaranteed to function outside its operating conditions.Data InBMC0 1 0 1 0 1 0 1 0 0 0 1 1 0 0 0 1 1PreambleSync-1Sync-1BMC ExampleInter-Frame Gap TimingsBMC Encoded Start of PreambleRT1710SFinal bit Preamble forTransmitting or Receiving BMC Encoded Frame TerminatedRT1710SY9Y8Y7Y6Y5Y4Y3Y2Y1BMC Tx ‘ONE’ MaskY9Y8Y7Y6Y5Y4Y3Y2Y1BMC Tx ‘ZERO’ MaskRT1710SApplication InformationStart of Packet Sequence Prime (SOP’)The SOP’ ordered set is defined as: two Sync-1 K-codes followed by two Sync-3 K-codesA Cable Plug capable of SOP’ Communications shall only detect and communicate with packets starting with SOP’.A DFP or Source needing to communicate with a Cable Plug capable of SOP’ Communications, attached between a Port Pair will be able to communicate using both packets starting with SOP’ to communicate with the Cable Plug and starting with SOP to communicate with its Port Partner. The DFP or Source shall co-ordinate SOP and SOP’ Communication so as to avoid collisions.Structured VDM Setting the VDM Type field to 1 (Structured VDM) defines the use of bits Bit[14:0] in the Structured VDM Header. The fields in the Structured VDM Header are defined in Table.The following rules apply to the use of Structured VDM messages:●Structured VDMs shall only be used when an Explicit Contract is in place with the following exception :Prior to establishing an Explicit Contract a Source may issue Discover Identity messages, to a Cable Plug using SOP’ Packets, as an Init iator.●Only the DFP shall be an Initiator of Structured VDMs except for the Attention Command that shall only be initiated by the UFP.●Only the UFP or a Cable Plug shall be a Responder to Structured VDMs.●Structured VDMs shall not be initiated or responded to under any other circumstances.● A DFP or UFP which does not support Structured VDMs shall ignore any Structured VDMs received. ● A Command sequence shall be interruptible e.g. due to the need for a message sequence using SOP Packets.RT1710SDiscover IdentityThe Discover Identity Command is provided to enable an Initiator (DFP) to identify its Port Partner and for an Initiator (Source or DFP) to identify the attached Cable Plug (Responder).The SVID in the Discover SVIDs Command shall be set to the PD SID by both the Initiator and the Responder for this Command.The Discover Identity Command sent back by the Responder contains an ID Header, a Cert Stat VDO and some Type specific VDOs which depend on the Product Type. This specification defines the following Type specific VDOs: ID HeaderThe ID Header contains the Vendor ID corresponding to the Power Delivery Product.RT1710SCert Stat VDOThe Cert Stat VDO contains the Test ID (TID) allocated by USB-IF during certification.Product VDOThe Product VDO contains identity information relating to the product.Cable VDOThe Cable VDO defined in this section shall be sent when the Product Type is given as Passive or Active Cable.Thermal ConsiderationsThe junction temperature should never exceed the absolute maximum junction temperature T J(MAX), listed under Absolute Maximum Ratings, to avoid permanent damage to the device. The maximum allowable power dissipation depends on the thermal resistance of the IC package, the PCB layout, the rate of surrounding airflow, and the difference between the junction and ambient temperatures. The maximum power dissipation can be calculated using the following formula :P D(MAX) = (T J(MAX) - T A ) / θJAwhere T J(MAX) is the maximum junction temperature, T A is the ambient temperature, and θJA is the junction-to-ambient thermal resistance.For continuous operation, the maximum operating junction temperature indicated under Recommended Operating Conditions is 125°C. The junction-to-ambient thermal resistance, θJA , is highly package dependent. For a WDFN-8L 2x2 package, the thermal resistance, θJA , is 45.5°C/W on a standard JEDEC 51-7 high effective-thermal-conductivity four-layer test board. The maximum power dissipation at T A = 25°C can be calculated as below :P D(MAX) = (125°C - 25°C) / (45.5°C/W) = 2.19W for a WDFN-8L 2x2 package.The maximum power dissipation depends on the operating ambient temperature for the fixed T J(MAX) and the thermal resistance, θJA . The derating curves in Figure 1 allows the designer to see the effect of rising ambient temperature on the maximum power dissipation. Figure 1. Derating Curve of Maximum PowerDissipationLayout Consideration④ PCB layout is very important for designing e-markedIC (RT1710S) circuits.④ Connect VCON1/VCON2 pins with bypass capacitor,and as near the pins as possible.④ The exposed pad of the chip should be connected toa large ground plane for thermal consideration.④ Keep the CC1 traces away from those sensing pins(D+,D-,SSTX+,SSTX-,SSRX+,SSRX-,SBU).connected to a large ground plane for thermal consideration.Keep the CC1 traces away from those sensing pins(D+,D-,SSTX+,SSTX-,SSRX+,SSRX-,SBU)with bypass capacitor,and as near the pins as possible.Figure 2. PCB Layout Guide0.00.40.81.21.62.02.42.83.23.64.0255075100125Ambient Temperature (°C)M a x i m u m P o w e r D i s s i p a t i o n (W )Outline DimensionW-Type 8L DFN 2x2 PackageFootprint InformationRichtek Technology Corporation14F, No. 8, Tai Yuen 1st Street, Chupei CityHsinchu, Taiwan, R.O.C.Tel: (8863)5526789Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.。
常用三极管参数技术手册
Tj (℃) 125 150 125 125 125 150 125 150 150 150 150 150 150 150 150 150 150 150 150 150 150 150 150 150 150 150 150 150 125 125 150 150 125 125 150 150 125 150 150
电气参数Ta=25℃ VCE VCE (最大值) fT(MHz) IC (sat) (sat) (A) (V) (V) IC(A) IB(A) 10m 0.4 ／ 20m 2m ≥300 500m 0.4 1.2 500m 50m 200 1m 0.7 ／ 10m 1m 300 5m 1.5 ／ 50m 5m ≥50 5m 1.5 ／ 50m 5m ≥50 5m 1.2 ／ 50m 5m ≥50 5m 1.2 ／ 50m 5m ≥50 1m 0.3 ／ 10m 1m ≥400 ≥150 150 150 180 ≥80 200 ≥600 550 300 ≥50 ≥50 ≥75 120 ≥300 120 ≥50 120 ≥50 50 ≥30 ≥20 ≥80 ≥50 ≥50 ≥50 ≥50 100 550 ≥50 120
(最大值) VCBO VCB (A) (V) 0.1u 20 0.1u 20 1.0u 10 ／ ／ ／ ／ 2u 12FE 20-100 85-340 40-200 30-220 30-220 30-220 30-220 40-180 VCE (V) 10 10 6 10 10 10 10 6
2SC1360A 2SC1383 2SC1417 2SC1473 2SC1473A 2SC1573 2SC1573A 2SC1674 2SC1675 2SC1684 2SC1685 2SC1740 2SC1815 2SC1846 2SC1906 2SC1923 2SC1959 2SC2001 2SC2060 2SC2068 2SC2120 2SC2216 2SC2229 2SC2230 2SC2230A 2SC2236 2SC2271 KSC2330 KSC2331 2SC2383 2SC2458 2SC2482 2SC2568 2SC2611 2SC2621 2SC2655 2SC2668 2SC2688 2SC2710
CY7C1061AV33-10ZXI中文资料
Logic Block Diagram
Functional Description
The CY7C1061AV33 is a high performance CMOS Static RAM organized as 1,048,576 words by 16 bits.
Commercial/Industrial
50
Pin Configurations [1, 2]
60-ball FBGA Top View
1
2
3
4
5
NC NC
NC
6
NC NC NC
BLE OE A0 A1 A2 CE2
A
IO 8 BHE A3 A4 CE1 IO 0
B
IO 9 IO 10 A5
A6 IO 1 IO 2
To write to the device, enable the chip (CE1 LOW and CE2 HIGH) while forcing the Write Enable (WE) input LOW. If Byte Low Enable (BLE) is LOW, then data from IO pins (IO0 through IO7), is written into the location specified on the address pins (A0 through A19). If Byte High Enable (BHE) is LOW, then data from IO pins (IO8 through IO15) is written into the location specified on the address pins (A0 through A19).
CY7C68013A-100AXC中文资料
元器件交易网
CY7C68013A/CY7C68014A CY7C68015A/CY7C68016A
1.2 Features (CY7C68015A/16A only)
an easy and glueless interface to popular interfaces such as ATA, UTOPIA, EPP, PCMCIA, and most DSP/processors. The FX2LP draws considerably less current than the FX2 (CY7C68013), has double the on-chip code/data RAM and is fit, form and function compatible with the 56-, 100-, and 128pin FX2. Four packages are defined for the family: 56 SSOP, 56 QFN, 100 TQFP, and 128 TQFP.
• CY7C68016A: Ideal for battery powered applications — Suspend current: 100 µA (typ) • CY7C68015A: Ideal for non-battery powered applications — Suspend current: 300 µA (typ) • Available in lead-free 56-pin QFN package (26 GPIOs) — 2 more GPIOs than CY7C68013A/14A enabling additional features in same footprint Cypress Semiconductor Corporation’s (Cypress’s) EZ-USB FX2LP (CY7C68013A/14A) is a low-power version of the EZ-USB FX2 (CY7C68013), which is a highly integrated, low-power USB 2.0 microcontroller. By integrating the USB 2.0 transceiver, serial interface engine (SIE), enhanced 8051 microcontroller, and a programmable peripheral interface in a single chip, Cypress has created a very cost-effective solution that provides superior time-to-market advantages with low power to enable bus powered applications. The ingenious architecture of FX2LP results in data transfer rates of over 53 Mbytes per second, the maximum-allowable USB 2.0 bandwidth, while still using a low-cost 8051 microcontroller in a package as small as a 56 QFN. Because it incorporates the USB 2.0 transceiver, the FX2LP is more economical, providing a smaller footprint solution than USB 2.0 SIE or external transceiver implementations. With EZ-USB FX2LP, the Cypress Smart SIE handles most of the USB 1.1 and 2.0 protocol in hardware, freeing the embedded microcontroller for application-specific functions and decreasing development time to ensure USB compatibility. The General Programmable Interface (GPIF) and Master/Slave Endpoint FIFO (8- or 16-bit data bus) provides
CY7C1515AV18资料
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元器件交易网
Logic Block Diagram (CY7C1513AV18)
CY7C1511AV18, CY7C1526AV18 CY7C1513AV18, CY7C1515AV18
18 D[17:0]
A(19:0) 20
■ Variable drive HSTL output buffers
■ JTAG 1149.1 compatible test access port
■ Delay Lock Loop (DLL) for accurate data placement
Configurations
CY7C1511AV18 – 8M x 8 CY7C1526AV18 – 8M x 9 CY7C1513AV18 – 4M x 18 CY7C1515AV18 – 2M x 36
Address Register
21
A(20:0)
2M x 8 Array 2M x 8 Array 2M x 8 Array 2M x 8 Array
Read Data Reg. 32 16
16
Control Logic
RPS
C C
Reg.
Reg. 8 8
Reg.
8
8
8
CQ CQ Q[7:0]
Logic Block Diagram (CY7C1526AV18)
Address Register
21
A(20:0)
2M x 9 Array 2M x 9 Array 2M x 9 Array 2M x 9 Array
Read Data Reg. 36 18
SCI Bias Resistor Transistors数据手册说明书
MUN5312DW1,NSBC124EPDXV6,NSBC124EPDP6 Complementary Bias Resistor TransistorsR1 = 22 k W, R2 = 22 k WNPN and PNP Transistors with Monolithic Bias Resistor NetworkThis series of digital transistors is designed to replace a single device and its external resistor bias network. The Bias Resistor Transistor (BRT) contains a single transistor with a monolithic bias network consisting of two resistors; a series base resistor and a base-emitter resistor. The BRT eliminates these individual components by integrating them into a single device. The use of a BRT can reduce both system cost and board space.Features•Simplifies Circuit Design•Reduces Board Space•Reduces Component Count•S and NSV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements;AEC-Q101 Qualified and PPAP Capable*•These Devices are Pb-Free, Halogen Free/BFR Free and are RoHS CompliantMAXIMUM RATINGS(T A = 25°C both polarities Q1 (PNP) & Q2 (NPN), unless otherwise noted) Rating Symbol Max Unit Collector-Base Voltage V CBO50Vdc Collector-Emitter Voltage V CEO50Vdc Collector Current − Continuous I C100mAdc Input Forward Voltage V IN(fwd)40Vdc Input Reverse Voltage V IN(rev)10Vdc Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected.ORDERING INFORMATIONDevice Package Shipping†MUN5312DW1T1G,SMUN5312DW1T1G*SOT−3633,000 / Tape & Reel NSVMUN5312DW1T3G*SOT−36310,000 / Tape & ReelMUN5312DW1T2G,NSVMUN5312DW1T2G*SOT−3633,000 / Tape & ReelNSBC124EPDXV6T1G,NSVBC124EPDXV6T1G*SOT−5634,000 / Tape & Reel NSBC124EPDXV6T5G SOT−5638,000 / Tape & Reel NSBC124EPDP6T5G SOT−9638,000 / Tape & Reel†For information on tape and reel specifications, including part orientation andtape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.MARKING DIAGRAMSPIN CONNECTIONS12/R=Specific Device CodeM=Date Code*G=Pb-Free Package (Note: Microdot may be in either location) *Date Code orientation may vary depending upon manufacturing location.SOT−363CASE 419B−02SOT−563CASE 463A(1)(2)(3)(6)(5)(4)SOT−963CASE 527ADM1R12 M GG1612 M G1THERMAL CHARACTERISTICSCharacteristic Symbol Max Unit MUN5312DW1 (SOT−363) ONE JUNCTION HEATEDTotal Device DissipationT A = 25°C(Note1)(Note2)Derate above 25°C(Note1)(Note2)P D1872561.52.0mWmW/°CThermal Resistance,(Note1) Junction to Ambient(Note2)R q JA670490°C/WMUN5312DW1 (SOT−363) BOTH JUNCTION HEATED (Note3)Total Device DissipationT A = 25°C(Note1)(Note2)Derate above 25°C(Note1)(Note2)P D2503852.03.0mWmW/°CThermal Resistance,Junction to Ambient(Note1)(Note2)R q JA493325°C/WThermal Resistance, Junction to Lead(Note1)(Note2)R q JL188208°C/WJunction and Storage Temperature Range T J, T stg−55 to +150°C NSBC124EPDXV6 (SOT−563) ONE JUNCTION HEATEDTotal Device DissipationT A = 25°C(Note1)Derate above 25°C(Note1)P D3572.9mWmW/°CThermal Resistance,Junction to Ambient(Note1)R q JA350°C/WNSBC124EPDXV6 (SOT−563) BOTH JUNCTION HEATED (Note3)Total Device DissipationT A = 25°C(Note1)Derate above 25°C(Note1)P D5004.0mWmW/°CThermal Resistance,Junction to Ambient(Note1)R q JA250°C/WJunction and Storage Temperature Range T J, T stg−55 to +150°C NSBC124EPDP6 (SOT−963) ONE JUNCTION HEATEDTotal Device DissipationT A = 25°C(Note4)(Note5)Derate above 25°C(Note4)(Note5)P D2312691.92.2MWmW/°CThermal Resistance,Junction to Ambient(Note4)(Note5)R q JA540464°C/WNSBC124EPDP6 (SOT−963) BOTH JUNCTION HEATED (Note3)Total Device DissipationT A = 25°C(Note4)(Note5)Derate above 25°C(Note4)(Note5)P D3394082.73.3MWmW/°CThermal Resistance,Junction to Ambient(Note4)(Note5)R q JA369306°C/WJunction and Storage Temperature Range T J, T stg−55 to +150°C1.FR−4 @ Minimum Pad.2.FR−*****×1.0 Inch Pad.3.Both junction heated values assume total power is sum of two equally powered channels.4.FR−4 @ 100mm2, 1 oz. copper traces, still air.5.FR−4 @ 500mm2, 1 oz. copper traces, still air.ELECTRICAL CHARACTERISTICS (T A =25°C both polarities Q 1 (PNP) & Q 2 (NPN), unless otherwise noted)CharacteristicSymbolMinTypMaxUnitOFF CHARACTERISTICS Collector-Base Cutoff Current (V CB =50V, I E =0)I CBO −−100nAdcCollector-Emitter Cutoff Current (V CE =50V, I B =0)I CEO −−500nAdcEmitter-Base Cutoff Current (V EB =6.0V, I C =0)I EBO −−0.2mAdcCollector-Base Breakdown Voltage (I C =10m A, I E =0)V (BR)CBO 50−−VdcCollector-Emitter Breakdown Voltage (Note 6)(I C =2.0mA, I B =0)V (BR)CEO50−−VdcON CHARACTERISTICS DC Current Gain (Note 6)(I C =5.0mA, V CE =10V)h FE 60100−Collector-Emitter Saturation Voltage (Note 6)(I C =10mA, I B =0.3mA)V CE(sat)−−0.25VInput Voltage (Off)(V CE =5.0V, I C =100m A) (NPN)(V CE =5.0V, I C =100m A) (PNP)V i(off)−− 1.21.2−−VdcInput Voltage (On)(V CE =0.2V, I C =5.0mA) (NPN)(V CE =0.2V, I C =5.0mA) (PNP)V i(on)−− 1.92.0−−VdcOutput Voltage (On)(V CC =5.0V, V B =2.5V, R L =1.0k W )V OL −−0.2VdcOutput Voltage (Off)(V CC =5.0V, V B =0.5V, R L =1.0k W )V OH 4.9−−VdcInput Resistor R115.42228.6k WResistor RatioR 1/R 20.81.01.2Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions.6.Pulsed Condition: Pulse Width =300ms, Duty Cycle ≤2%.Figure 1. Derating CurveAMBIENT TEMPERATURE (°C)P D , P O W E R D I S S I P A T I O N (m W )(1) SOT−363; 1.0×1.0 Inch Pad (2) SOT−563; Minimum Pad(3) SOT−963; 100mm 2, 1 oz. Copper TraceFigure 2. V CE(sat) vs. I CFigure 3. DC Current GainFigure 4. Output Capacitance Figure 5. Output Current vs. Input VoltageFigure 6. Input Voltage vs. Output Current1.60.80V R , REVERSE VOLTAGE (V)0.41.22.02.42.83.2C o b , O U T P U T C A P A C I T A N C E (p F )0.010.001I C , COLLECTOR CURRENT (mA)V C E (s a t ), C O L L E C T O R -E M I T T E R V O L T A G E (V )h F E , D C C U R R E N T G A I N10001001I C , COLLECTOR CURRENT (mA)10I C , C O L L E C T O R C U R R E N T (m A )1001010.10.010.001V in , INPUT VOLTAGE (V)V i n , I N P U T V O L T A G E (V )I C , COLLECTOR CURRENT (mA)1010.1100C o b , O U T P U T C A P A C I T A N C E (p F )Figure 7. V CE(sat) vs. I CFigure 8. DC Current GainFigure 9. Output Capacitance Figure 10. Output Current vs. Input VoltageFigure 11. Input Voltage vs. Output Current10320V R , REVERSE VOLTAGE (V)456789 0.001I C , COLLECTOR CURRENT (mA) 0.11V C E (s a t ), C O L L E C T O R -E M I T T E R V O L T A G E (V ) 0.01h F E , D C C U R R E N T G A I NI C , COLLECTOR CURRENT (mA)1I C , C O L L E C T O R C U R R E N T (m A )100101 0.1 0.01 0.001V in , INPUT VOLTAGE (VOLTS)V i n , I N P U T V O L T A G E (V )I C , COLLECTOR CURRENT (mA)1Figure 12. V CE(sat) vs. I CI C , COLLECTOR CURRENT (mA)10010.1Figure 13. DC Current GainFigure 14. Output CapacitanceI C , COLLECTOR CURRENT (mA)10001001I C , COLLECTOR CURRENT (mA)Figure 15. Output Current vs. Input Voltage1001010.10.01V in , INPUT VOLTAGE (V)Figure 16. Input Voltage vs. Output Current0.41.20V R , REVERSE VOLTAGE (V)V C E (s a t ), C O L L E C T O R −E M I T T E R V O L T A G E (V )h F E , D C C U R R E N T G A I N 0.81.62.02.4C o b , O U T P U T C A P A C I T A N C E (p F )I C , C O L L E C T O R C U R R E N T (m A )V i n , I N P U T V O L T A G E (V )1010Figure 17. V CE(sat) vs. I CFigure 18. DC Current GainI C , COLLECTOR CURRENT (mA)I C , COLLECTOR CURRENT (mA)0.010.11Figure 19. Output CapacitanceFigure 20. Output Current vs. Input VoltageV R , REVERSE VOLTAGE (V)V in , INPUT VOLTAGE (V)Figure 21. Input Voltage vs. Output CurrentI C , COLLECTOR CURRENT (mA)V C E (s a t ), C O L L E C T O R −E M I T T E R V O L T A G E (V )h F E , D C C U R R E N T G A I NC o b , O U T P U T C A P A C I T A N C E (p F )I C , C O L L E C T O R C U R R E N T (m A )V i n , I N P U T V O L T A G E (V )SC−88/SC70−6/SOT−363CASE 419B−02ISSUE YNOTES:1.DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.2.CONTROLLING DIMENSION: MILLIMETERS.3.DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH,PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRU-SIONS, OR GATE BURRS SHALL NOT EXCEED 0.20 PER END.4.DIMENSIONS D AND E1 AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY AND DATUM H.5.DATUMS A AND B ARE DETERMINED AT DATUM H.6.DIMENSIONS b AND c APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.08 AND 0.15 FROM THE TIP .7.DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION.ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 TOTAL IN EXCESS OF DIMENSION b AT MAXIMUM MATERIAL CONDI-TION. THE DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OF THE FOOT.DIM MIN NOM MAX MILLIMETERS A −−−−−− 1.10A10.00−−−0.10dddb 0.150.200.25C 0.080.150.22D 1.80 2.00 2.20−−−−−−0.0430.000−−−0.0040.0060.0080.0100.0030.0060.0090.0700.0780.086MIN NOM MAX INCHES0.100.004E1 1.15 1.25 1.35e 0.65 BSC L 0.260.360.462.00 2.10 2.200.0450.0490.0530.026 BSC0.0100.0140.0180.0780.0820.086*For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.SOLDERING FOOTPRINT*DIMENSIONS: MILLIMETERS0.306XRECOMMENDEDSIDE VIEWEND VIEWPLANEDETAIL AE A20.700.90 1.000.0270.0350.039L20.15 BSC 0.006 BSC aaa 0.150.006bbb 0.300.012ccc 0.100.0046XH EDIMMIN NOM MAX MILLIMETERS A 0.500.550.60b 0.170.220.27C D 1.50 1.60 1.70E 1.10 1.20 1.30e 0.5 BSC L 0.100.200.301.50 1.60 1.700.0200.0210.0230.0070.0090.0110.0590.0620.0660.0430.0470.0510.02 BSC0.0040.0080.0120.0590.0620.066MIN NOM MAX INCHESSOT−563, 6 LEADCASE 463A ISSUE GNOTES:1.DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.2.CONTROLLING DIMENSION: MILLIMETERS3.MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL.ǒmm inchesǓSCALE 20:1*For additional information on our Pb−Free strategy and solderingdetails, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.SOLDERING FOOTPRINT*0.080.120.180.0030.0050.007SOT−963CASE 527AD ISSUE EDIM MIN NOM MAX MILLIMETERS A 0.340.370.40b 0.100.150.20C 0.070.120.17D 0.95 1.00 1.05E 0.750.800.85e 0.35 BSC 0.95 1.00 1.05H E ANOTES:1.DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.2.CONTROLLING DIMENSION: MILLIMETERS3.MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH THICKNESS. MINIMUM LEADTHICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL.4.DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS.TOP VIEW SIDE VIEWDIMENSIONS: MILLIMETERSRECOMMENDEDMOUNTING FOOTPRINT*L 0.19 REF L20.050.100.156X *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent PUBLICATION ORDERING INFORMATION。
C10100无氧铜对应国内那个材料
美国 C10100 日本 C1011C10100无氧铜纯度高，导电、导热性极好，无“氢病”或极少“氢病”；加工性能和焊接、耐蚀、耐蚀性均好。
OF-CU无氧铜用于电真空器件和仪器、仪表用。
执行标准：GB/T 5231-2001化学成份：抗拉强度：（σbN/mm²）≥275注：棒材的纵向室温拉伸力学性能试样尺寸：直径16～120C10100无氧铜纯度达到99.95%，氧含量不大于0.003%，杂质总含量不大于0.05%。
分子式就是Cu。
C10100无氧铜主要特征是该标准物质中氧含量的定值不大于10ppm，实施例的定值为3.0±0.7ppm我公司主营铜、镍合金、板、棒、锻件、丝材、无缝管、焊管、法兰、环件及其配件。
公司主要生产销售铜合金牌号：【上海同铸①③⑥0①⑦④⑨⑨①⑤】纯铜：T1 T2 T3无氧铜：TU0 TU1 TU2磷脱氧铜：TP1 TP2 TAg0.1黄铜：H96 H90 H85 H80 H70 H68 H65 H63 H62 H59镍黄铜：HNi65-5 HNi56-3铅黄铜：HPb89-2 HPb66-0.5 HPb63-3 HPb63-0.1 HPb62-0.8 HPb62-3 HPb62-2 HPb61-1 HPb60-2 HPb59-3 HPb59-1加砷黄铜：HAl77-2 HSn70-1 H85A H70A H68A锡黄铜：HSn90-1 HSn62-1 HSn60-1铝黄铜：HAl67-2.5 HAl61-4-3-1 HAl60-1-1 HAl59-3-2 HAl66-6-3-2锰黄铜：HMn62-3-3-7 HMn58-2 HMn57-3-1 HMn55-3-1铁黄铜：HFe59-1-1 HFe58-1-1硅黄铜：HSi80-3锡青铜：QSn1.5-0.2 QSn4-0.3 QSn4-3 QSn4-4-2.5 QSn4-4-4 QSn6.5-0.1 QSn6.5-0.4 QSn7-0.2 QSn8-0.3铝青铜：QAl5 QAl7 QAl9-2 QAl9-4 QAl10-3-1.5 QAl10-4-4 QAl11-6-6 QAl9-5-1-1 QAl10-5-5铍青铜：QBe2 QBe1.9 QBe1.9-0.1 QBe1.7 QBe0.6-2.5 QBe0.4-1.8 QBe0.3-1.5硅青铜：QSi3-1 QSi1-3 QSi3.5-3-1.5锰青铜：QMn1.5 QMn2 QMn5锆青铜：QZr0.2 QZr0.4铬青铜：QCr1 QCr0.5 QCr0.5-0.2-0.1 QCr0.6-0.4-0.05镉青铜：QCd1镁青铜：QMg0.8铁青铜：QFe2.5碲青铜：QFe0.5白铜：B0.6 B5 B19 B25 B30铁白铜：BFe5-1.5-0.5 BFe10-1-1 BFe30-1-1锰白铜：BMn3-12 BMn40-1.5 BMn43-0.5锌白铜：BZn18-18 BZn18-26 BZn15-20 BZn15-21-1.8 BZn15-24-1.5铝白铜：BAl3-3 BAl6-1.5铸造黄铜锭：ZHD68 ZHD62铸造铝黄铜锭：ZHAlD67-5-2-2 ZHAlD63-6-3-3 ZHAlD62-4-3-3 ZHAlD67-2.5 ZHAlD61-2-2-1铸造锰黄铜锭：ZHMnD58-2-2 ZHMnD58-2 ZHMnD57-3-1铸造铅黄铜锭：ZHPbD65-2 ZHPbD59-1 ZHPbD60-2铸造硅黄铜锭：ZHSiD80-3 ZHSSiD80-3-3锰铜康铜：6J12 6J13 6J8 6J40。
西子奥的斯安全回路常用线
P2H-4—P2H-5
张紧轮、地坑急停
P2H-1—P2H-4
厅门锁
OH—CONA553
H2-1—H2-9
厅门锁
T1-6—T1-7
轿门锁
M1-1—M1-2
限速器
M1-9—M1-10
盘车轮
H1-1—H1-2
上下极限、缓冲器、张紧轮、地坑急停
H1-2—H1-3
下换速
H1-3—H1-4
上换速
T2-9—T2-12
安全钳
T1-3—T1-4
轿顶安全、安全钳
MI-3—M1-4
热敏电阻保护开关
OH—CON5403(21VF)
C01—C02
相序、盘车轮、安全钳、限速器
CO2—C03
上下极限、缓冲器、涨绳轮、地坑急停
C03—பைடு நூலகம்04
下换速
CO4—CO5
上换速
C05—CO6
安全窗
CO6—C07
厅门
CO7—C08
轿门
下限位
H1-5---H1-6
下换速
H1-5---H1-7
上换速
消防13--15
控制信号
消防18--19
无源反馈信号
型号ACD2__MR
TB1-7—TB1-8
盘车轮
102CM-1—102CM-2
轿顶急停轿、轿顶安全窗、安全钳
P3M-1—P3M-3
限速器
P2H-2—P2H-5
上下极限、缓冲器
102CM-4—102CM-5
西子奥的斯安全回路常用线
型号OH-CON5000—GEN2
CO1—CO2
相序、盘车轮、安全窗、轿顶急停、安全钳
CO2---CO3
cm1061ds芯片引脚介绍
cm1061ds芯片引脚介绍
CM1061DS芯片是一款音频处理芯片。
它具备14个引脚，以下是每个引脚的功能介绍：
1. XTAL1：晶体振荡器输入。
用于连接外部晶体振荡器。
2. XTAL2：晶体振荡器输出。
用于连接外部晶体振荡器。
3. NC：无连接引脚，不连接任何功能。
4. SDIN：串行数据输入引脚。
用于接收外部串行音频数据。
5. SDOUT：串行数据输出引脚。
用于将内部处理后的音频数据输出。
6. SCLK：串行时钟引脚。
用于同步数据传输。
7. NC：无连接引脚，不连接任何功能。
8. IO1：数字输入/输出引脚。
可用于连接外部控制信号或数据输入/输出。
9. GND：地引脚。
连接芯片的地端。
10. VDD：供电引脚。
连接芯片的正电源。
11. NC：无连接引脚，不连接任何功能。
12. NC：无连接引脚，不连接任何功能。
13. NC：无连接引脚，不连接任何功能。
14. IO2：数字输入/输出引脚。
可用于连接外部控制信号或数据输入/输出。
以上是CM1061DS芯片的引脚介绍，每个引脚都有特定的功能和用途，根据具体应用需要进行连接和配置。
USB2．0控制器CY7C68013在lon总线技术中的应用
USB2．0控制器CY7C68013在lon总线技术中的应用
徐进;朱剑雄
【期刊名称】《湖北农机化》
【年(卷),期】2012(000)003
【摘要】针对工业现场对高性能的便携式（主要针对移动系统）数据通信的要求，研制了LON总线的USB2．0接口卡。
由于采用USB2．0接口，能够克服以往使用Rs-232串口与便携设备通信实时性不够的弱点。
U182．0协议提供480Mb／s的传输速度，向下完全兼容流行的USB1．1协议。
接口卡主要由Toshiba公司生产的TMPN3150与Cypress公司推出的USB2．0控制器CY7C68013组成。
3150完成与LON总线的通信而CY7C68013则具有USB2．0的完整解决方案，两芯片的通信采用并口通信方式。
【总页数】3页(P58-60)
【作者】徐进;朱剑雄
【作者单位】湖北省黄冈市质量技术监督局;湖北工业大学机械工程学院
【正文语种】中文
【中图分类】TP303
【相关文献】
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B2.0控制器CY7C68013特点与应用 [J], 扈啸;张玘;张连超
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16-Mbit (1M x 16) Static RAMCY7C1061BV33Features•High speed —t AA = 10 ns •Low active power —990 mW (max.)•Operating voltages of 3.3 ± 0.3V •2.0V data retention•Automatic power-down when deselected •TTL-compatible inputs and outputs•Available in Pb-free and non Pb-free 54-pin TSOP II packageFunctional DescriptionThe CY7C1061BV33 is a high-performance CMOS Static RAM organized as 1,048,576 words by 16 bits.Writing to the device is accomplished by enabling the chip (CELOW) while forcing the Write Enable (WE) input LOW. If ByteLow Enable (BLE) is LOW, then data from I/O pins (I/O 0through I/O 7), is written into the location specified on the address pins (A 0 through A 19). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O 8 through I/O 15) is written into the location specified on the address pins (A 0 through A 19).Reading from the device is accomplished by enabling the chip by taking CE LOW while forcing the Output Enable (OE) LOW and the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O 0 to I/O 7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O 8 to I/O 15. See the truth table at the back of this data sheet for a complete description of Read and Write modes.The input/output pins (I/O 0 through I/O 15) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a Write operation (CE LOW and WE LOW).The CY7C1061BV33 is available in a 54-pin TSOP II package with center power and ground (revolutionary) pinout.Logic Block Diagram 1516A 1A 2A 3A 4A 5A 6A 7A 8COLUMN DECODERR O W D E C O D E RS E N S E A M P SINPUT BUFFER1M x 16ARRAYA 0A 12A 14A 13A A A 17A 18A 10A 11I/O 0–I/O 7OE I/O 8–I/O 15CE WE BLEBHE A 9A 19WE12345678910111431323635343337403938121341434216152930A 5A 6A 7A 8A 0A 1OE V SS A 17I/O 15A 2CE I/O 2I/O 0I/O 1BHE A 3A 418172019I/O 32728252622212324I/O 6I/O 4I/O 5I/O 7A 16A 15BLE V CC I/O 14I/O 13I/O 12I/O 10I/O 9I/O 8A 14A 13A 12A 11A 9A 104446454750494851535254V SS V CC A 19A 18V CC V CC V SS V SSNC V CC I/O 11V SS DNU/V CCDNU/V SS 54-pin TSOP II (Top View)Notes:1.DNU/V CC Pin (#16) has to be left floating or connected to V CC and DNU/V SS Pin (#40) has to be left floating or connected to V SS to ensure proper application.2.NC – No Connect Pins are not connected to the diePin Configurations [1, 2]CY7C1061BV33Maximum Ratings(Above which the useful life may be impaired. For user guide-lines, not tested.)Storage Temperature .................................–65°C to +150°C Ambient Temperature withPower Applied.............................................–55°C to +125°C Supply Voltage on V CC to Relative GND[3]–0.5V to +4.6VDC Voltage Applied to Outputsin High-Z State[3]....................................–0.5V to V CC + 0.5V DC Input Voltage[3]................................–0.5V to V CC + 0.5V Current into Outputs (LOW).........................................20 mASelection Guide–10–12Unit Maximum Access Time1012ns Maximum Operating Current Commercial275260mAIndustrial275260Maximum CMOS Standby Current Commercial/Industrial5050mAOperating RangeRange Ambient Temperature V CCCommercial0°C to +70°C 3.3V ± 0.3VIndustrial–40°C to +85°CDC Electrical Characteristics Over the Operating RangeParameter Description Test Conditions–10–12Unit Min.Max.Min.Max.V OH Output HIGH Voltage V CC = Min., I OH = –4.0 mA 2.4 2.4V V OL Output LOW Voltage V CC = Min., I OL = 8.0 mA0.40.4V V IH Input HIGH Voltage 2.0V CC + 0.3 2.0V CC + 0.3V V IL Input LOW Voltage[3]–0.30.8–0.30.8V I IX Input Leakage Current GND < V I < V CC–1+1–1+1µA I OZ Output Leakage Current GND < V OUT < V CC, Output Disabled–1+1–1+1µAI CC V CC OperatingSupply Current V CC = Max.,f = f MAX = 1/t RCCommercial275260mAIndustrial275260mAI SB1Automatic CEPower-down Current—TTL Inputs Max. V CC, CE > V IHV IN > V IH or V IN < V IL, f = f MAX7070mAI SB2Automatic CEPower-down Current—CMOS Inputs Max. V CC,CE > V CC – 0.3V,V IN > V CC – 0.3V,or V IN < 0.3V, f = 0Commercial/Industrial5050mACapacitance[4]Parameter Description Test Conditions Max.Unit C IN Input Capacitance T A = 25°C, f = 1 MHz, V CC = 3.3V6pF C OUT I/O Capacitance8pFThermal Resistance[4]Parameter Description Test Conditions54-pin TSOP-II UnitΘJA Thermal Resistance (Junction to Ambient)Test conditions follow standard testmethods and procedures formeasuring thermal impedance, perEIA/JESD51.49.95°C/WΘJC Thermal Resistance (Junction to Case) 3.34°C/W Notes:3.V IL (min.) = –2.0V and V IH(max) = V CC + 0.5V for pulse durations of less than 20 ns.4.Tested initially and after any design or process changes that may affect these parameters.CY7C1061BV33AC Test Loads and Waveforms [5]AC Switching Characteristics Over the Operating Range [6]Parameter Description–10–12UnitMin.Max.Min.Max.Read Cycle t power V CC (typical) to the first access [7]11ms t RC Read Cycle Time 1012ns t AA Address to Data Valid1012ns t OHA Data Hold from Address Change 33ns t ACE CE LOW to Data Valid 1012ns t DOE OE LOW to Data Valid 56ns t LZOE OE LOW to Low-Z 11ns t HZOE OE HIGH to High-Z [8]56ns t LZCE CE LOW to Low-Z [8]33ns t HZCE CE HIGH to High-Z [8]56ns t PU CE LOW to Power-Up [9]0ns t PD CE HIGH to Power-Down [9]1012ns t DBE Byte Enable to Data Valid 56ns t LZBE Byte Enable to Low-Z 11ns t HZBEByte Disable to High-Z56nsNotes:5.Valid SRAM operation does not occur until the power supplies have reached the minimum operating V DD (3.0V). As soon as 1ms (T power ) after reaching the minimum operating V DD , normal SRAM operation can begin including reduction in V DD to the data retention (V CCDR , 2.0V) voltage.6.Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified I OL /I OH and specified transmission line loads. T est conditions for the Read cycle use output loading shown in part a) of the AC test loads, unless specified otherwise.7.This part has a voltage regulator which steps down the voltage from 3V to 2V internally. t power time has to be provided initially before a Read/Write operation is started.8.t HZOE , t HZCE , t HZWE , t HZBE and t LZOE , t LZCE , t \LZWE , t LZBE are specified with a load capacitance of 5 pF as in (b) of AC T est Loads. Transition is measured ±200 mV from steady-state voltage.9.These parameters are guaranteed by design and are not tested.10.The internal Write time of the memory is defined by the overlap of CE LOW and WE LOW. Chip enables must be active and WE and byte enables must be LOW toinitiate a Write, and the transition of any of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the Write.11.The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of t HZWE and t SD .90%10%3.3V GND 90%10%ALL INPUT PULSES3.3V OUTPUT5 pF*INCLUDING JIG AND SCOPE(a)(b)R1 317ΩR2351ΩRise time > 1V/nsFall time: > 1V/ns(c)OUTPUT50ΩZ 0= 50ΩV TH = 1.5V30 pF** Capacitive Load consists of all com-ponents of the test environment.CY7C1061BV33Write Cycle [10, 11]t WC Write Cycle Time 1012ns t SCE CE LOW to Write End 78ns t AW Address Set-up to Write End 77ns t SA Address Set-up to Write Start 00ns t PWE WE Pulse Width 78ns t SD Data Set-up to Write End 5.56ns t HD Data Hold from Write End 00ns t LZWE WE HIGH to Low-Z [8]33ns t HZWE WE LOW to High-Z [8]56ns t BW Byte Enable to End of Write 78ns t HAAddress Hold from Write End00nsAC Switching Characteristics Over the Operating Range [6] (continued)Parameter Description–10–12Unit Min.Max.Min.Max.Data Retention Waveform3.0V 3.0V t CDRV DR >2VDATA RETENTION MODEt RCEV CC Switching WaveformsRead Cycle No. 1[12, 13]Notes:12.Device is continuously selected. OE, CE, BHE and/or BHE = V IL . 13.WE is HIGH for Read cycle.PREVIOUS DATA VALIDDATA VALIDt RCt AAt OHAADDRESSDATA OUTCY7C1061BV33Read Cycle No. 2 (OE Controlled)[13, 14]Write Cycle No. 1 (CE Controlled)[15, 16]Notes:14.Address valid prior to or coincident with CE transition LOW.15.Data I/O is high-impedance if OE or BHE and/or BLE = V IH .16.If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.Switching Waveforms (continued)50%50%DATA VALIDt RCt ACEt DOE t LZOE t LZCE t PUHIGH IMPEDANCEt HZOEt HZBEt PDHIGH OE CEICC IMPEDANCEADDRESSDATA OUT V CC SUPPLY t DBE t LZBEt HZCE BHE,BLECURRENTI CC I SBt HDt SDt SCEt SA t HAt AWt PWEt WCBWDATAI/OADDRESSCEWEBHE,BLEtCY7C1061BV33Write Cycle No. 2 (BLE or BHE Controlled)Write Cycle No. 3 (WE Controlled, OE LOW)[15, 16]Switching Waveforms (continued)t HDt SDt BWt SA t HAt AWt PWEt WCt SCEDATAI/OADDRESSBHE,BLEWECEt HDt SDt SCEt HAt AWt PWEt WCt BWDATA I/OADDRESSCEWEBHE,BLEt SAt LZWEt HZWECY7C1061BV33 Truth TableCE OE WE BLE BHE I/O0–I/O7I/O8–I/O15Mode PowerH X X X X High-Z High-Z Power-down Standby (I SB)L L H L L Data Out Data Out Read All Bits Active (I CC) L L H L H Data Out High-Z Read Lower Bits Only Active (I CC) L L H H L High-Z Data Out Read Upper Bits Only Active (I CC) L X L L L Data In Data In Write All Bits Active (I CC) L X L L H Data In High-Z Write Lower Bits Only Active (I CC) L X L H L High-Z Data In Write Upper Bits Only Active (I CC) L H H X X High-Z High-Z Selected, Outputs Disabled Active (I CC) Ordering InformationSpeed(ns)Ordering Code PackageName Package Type Operating Range10CY7C1061BV33-10ZC51-8516054-pin TSOP II Commercial CY7C1061BV33-10ZI Industrial CY7C1061BV33-10ZXC54-pin TSOP II (Pb-free)Commercial CY7C1061BV33-10ZXI Industrial 12CY7C1061BV33-12ZC54-pin TSOP II Commercial CY7C1061BV33-12ZI Industrial CY7C1061BV33-12ZXC54-pin TSOP II (Pb-free)Commercial CY7C1061BV33-12ZXI IndustrialCY7C1061BV33All products and company names mentioned in this document may be the trademarks of their respective holders.Package Diagram51-85160-**54-pin TSOP II (51-85160)CY7C1061BV33 Document History PageDocument Title: CY7C1061BV33 16-Mbit (1M x 16) Static RAMDocument Number: 38-05693REV.ECN NO.Issue Date Orig. ofChange Description of Change**283950See ECN RKF New data sheet*A309453See ECN RKF Final data sheet*B492137See ECN NXR Removed 8 ns speed binChanged the description of I IX from Input Load Current to Input LeakageCurrent in DC Electrical Characteristics tableUpdated the Ordering Information Table。