cc430 c code

//***************************************************************************** *// C430F613x Demo - ADC12_A, Sample A0, Set P1.0 if A0 > 0.5*AVcc//// Description: A single sample is made on A0 with reference to A Vcc.// Software sets ADC12SC to start sample and conversion - ADC12SC// automatically cleared at EOC. ADC12 internal oscillator times sample (16x)// and conversion. In mainloop CC430 waits in LPM0 to save power until ADC12// conversion complete, ADC12_ISR will force exit from LPM0 in Mainloop on// reti. If A0 > 0.5*A Vcc, P1.0 set, else reset.//// CC430F6137// -----------------// /|\| |// | | |// --|RST |// | |// Vin -->|P2.0/A0 P1.0|--> LED//// M Morales// Texas Instruments Inc.// April 2009// Built with CCE Version: 3.2.2 and IAR Embedded Workbench Version: 4.2//***************************************************************************** *#include "cc430x613x.h"void main(void){WDTCTL = WDTPW + WDTHOLD; // Stop WDTADC12CTL0 = ADC12SHT02 + ADC12ON; // Sampling time, ADC12 onADC12CTL1 = ADC12SHP; // Use sampling timerADC12IE = 0x01; // Enable interruptADC12CTL0 |= ADC12ENC;P2SEL |= BIT0; // P2.0 ADC option selectP1DIR |= BIT0; // P1.0 outputwhile (1){ADC12CTL0 |= ADC12SC; // Start sampling/conversion__bis_SR_register(LPM0_bits + GIE); // LPM0, ADC12_ISR will force exit__no_operation(); // For debugger}}#pragma vector = ADC12_VECTOR__interrupt void ADC12_ISR(void){switch(__even_in_range(ADC12IV,34)){case 0: break; // Vector 0: No interruptcase 2: break; // Vector 2: ADC overflowcase 4: break; // Vector 4: ADC timing overflowcase 6: // V ector 6: ADC12IFG0if (ADC12MEM0 >= 0x7ff) // ADC12MEM = A0 > 0.5A Vcc?P1OUT |= BIT0; // P1.0 = 1elseP1OUT &= ~BIT0; // P1.0 = 0__bic_SR_register_on_exit(LPM0_bits); // Exit active CPUcase 8: break; // Vector 8: ADC12IFG1case 10: break; // Vector 10: ADC12IFG2case 12: break; // Vector 12: ADC12IFG3case 14: break; // Vector 14: ADC12IFG4case 16: break; // Vector 16: ADC12IFG5case 18: break; // Vector 18: ADC12IFG6case 20: break; // Vector 20: ADC12IFG7case 22: break; // Vector 22: ADC12IFG8case 24: break; // Vector 24: ADC12IFG9case 26: break; // Vector 26: ADC12IFG10case 28: break; // Vector 28: ADC12IFG11case 30: break; // Vector 30: ADC12IFG12case 32: break; // Vector 32: ADC12IFG13case 34: break; // Vector 34: ADC12IFG14default: break;}}//***************************************************************************** *// CC430x613x Demo - COMPB output Toggle in LPM4; internal 2.0V reference//// Description: Use CompB and internal reference to determine if input'Vcompare'// is high of low. When Vcompare exceeds 2.0V CBOUT goes high and when// Vcompare is less than 2.0V then CBOUT goes low.// Connect P1.6/CBOUT to P1.0 externally to see the LED toggle accordingly.//// CC430x613x// ------------------// /|\| |// | | |// --|RST P2.0/CB0|<--Vcompare// | |// | P1.6/CBOUT|----> 'high'(Vcompare>2.0V); 'low'(Vcompare<2.0V)// | | |// | P1.0 |__| LED 'ON'(Vcompare>2.0V); 'OFF'(Vcompare<2.0V) // | |//// M Morales// Texas Instruments Inc.// April 2009// Built with CCE Version: 3.2.2 and IAR Embedded Workbench Version: 4.11B//***************************************************************************** *#include "cc430x613x.h"void main(void){WDTCTL = WDTPW + WDTHOLD; // Stop WDTP1DIR |= BIT6; // P1.6 output directionP1SEL |= BIT6; // Select CBOUT function on P1.6/CBOUTPMAPPWD = 0x02D52; // Get write-access to port mapping regs P1MAP6 = PM_CBOUT0; // Map CBOUT output to P1.6 PMAPPWD = 0; // Lock port mapping registersP2SEL |= BIT0; // Select CB0 input for P2.0// Setup ComparatorBCBCTL0 |= CBIPEN + CBIPSEL_0; // Enable V+, input channel CB0CBCTL1 |= CBPWRMD_1; // normal power modeCBCTL2 |= CBRSEL; // VREF is applied to -terminalCBCTL2 |= CBRS_3+CBREFL_2; // R-ladder off; bandgap ref voltage (1.2V)// supplied ref amplifier to get Vcref=2.0V (CBREFL_2)CBCTL3 |= BIT0; // Input Buffer Disable @P6.0/CB0 CBCTL1 |= CBON; // Turn On ComparatorB__delay_cycles(75);__bis_SR_register(LPM4_bits); // Enter LPM4__no_operation(); // For debug}//***************************************************************************** *// CC430F613x Demo - Reset on Invalid Address fetch, Toggle P1.0//// Description: This program demonstrates how a reset is executed if the CPU// tries to fetch instructions from within the module register memory address// range (0x0100 --0x0FEF) or from within unused address ranges. Toggle P1.0// by xor'ing P1.0 inside of a software loop that ends with TAR loaded with// 3FFFh - op-code for "jmp $". This simulates a code error. The CC430F6137// will force a reset because it will not allow a fetch from within the address// range of the peripheral memory, as is seen by return to the mainloop and// LED flash.// ACLK = n/a, MCLK = SMCLK = default DCO ~1.045MHz//// CC430F6137// -----------------// /|\| |// | | |// --|RST |// | |// | P1.0|-->LED//// M Morales// Texas Instruments Inc.// April 2009// Built with CCE Version: 3.2.2 and IAR Embedded Workbench Version: 4.11B//***************************************************************************** *#include "cc430x613x.h"void main(void){WDTCTL = WDTPW + WDTHOLD; // Stop watchdog timer - SET BREAKPOINT HEREP1DIR |= 0x01; // Set P1.0 to output directionTA0R = 0x3FFF; // Valid opcode (for "jmp $")while(1){P1OUT ^= 0x01; // Toggle P1.0 using exclusive-OR__delay_cycles(50000); // Delay loop// C code to directly call an address location((void (*)())0x350)(); // Invalid fetch ("call #0350h")/* 0x350 is address of TA0R register and is within the module register memoryaddress range (0x0100 --0x0FEF) */}}//***************************************************************************** *// CC430x613x Demo - DMA0, Repeated Block to-from RAM, Software Trigger//// Description: A 16 word block from 1C00-1C1Fh is transfered to 1C20h-1C3fh// using DMA0 in a burst block using software DMAREQ trigger.// After each transfer, source, destination and DMA size are// reset to inital software setting because DMA transfer mode 5 is used.// P1.0 is toggled durring DMA transfer only for demonstration purposes.// ** RAM location 0x1C00 - 0x1C3F used - make sure no compiler conflict **//// Use the memory view to see memory the valid memory transfers.//// ACLK = REFO = 32kHz, MCLK = SMCLK = default DCO 1048576Hz//// CC430x613x// -----------------// /|\| XIN|-// | | | 32kHz// --|RST XOUT|-// | |// | P1.0|-->LED//// M. Morales// Texas Instruments Inc.// April 2009// Built with CCE v3.1 Build 3.2.3.6.4 & IAR Embedded Workbench Version: 4.11B//***************************************************************************** *#include "cc430x613x.h"void main(void){WDTCTL = WDTPW+WDTHOLD; // Stop WDTP1DIR |= 0x01; // P1.0 output/* Initialize DMA */__data16_write_addr((unsigned short) &DMA0SA,(unsigned long) 0x1C00);// Source block address__data16_write_addr((unsigned short) &DMA0DA,(unsigned long) 0x1C20);// Destination single addressDMA0SZ = 16; // Block sizeDMA0CTL = DMADT_5+DMASRCINCR_3+DMADSTINCR_3; // Rpt, incDMA0CTL |= DMAEN; // Enable DMA0while(1){P1OUT |= 0x01; // P1.0 = 1, LED onDMA0CTL |= DMAREQ; // Trigger block transfer__delay_cycles(64); // Provide sufficient time for DMA xfer__no_operation(); // Set breakpoint hereP1OUT &= ~0x01; // P1.0 = 0, LED off}}//***************************************************************************** *// CC430x613x Demo - Single-Byte Flash In-System Programming, Copy SegC to SegD//// Description: This program first erases flash seg C, then it increments all// values in seg C, then it erases seg D, then copies seg C to seg D. Starting// addresses of segments defined in this code: Seg C-0x1880, Seg D-0x1800.// RESET the device to re-execute code. This is implemented to prevent// stressing of Flash unintentionally.// ACLK = REFO = 32kHz, MCLK = SMCLK = default DCO 1048576Hz//// CC430x613x// -----------------// /|\| XIN|-// | | |// --|RST XOUT|-// | |//// M. Morales// Texas Instruments Inc.// April 2009// Built with CCE v3.1 Build 3.2.3.6.4 and IAR Embedded Workbench v4.11B//***************************************************************************** *#include "cc430x613x.h"char value; // 8-bit value to write to seg C// Function prototypesvoid write_SegC(char value);void copy_C2D(void);void main(void){WDTCTL = WDTPW+WDTHOLD; // Stop WDTvalue = 0; // initialize valuewrite_SegC(value); // Write segment C, increment valuecopy_C2D(); // Copy segment C to Dwhile(1); // Loop forever, SET BREAKPOINT HERE }//------------------------------------------------------------------------------// Input = value, holds value to write to Seg C//------------------------------------------------------------------------------void write_SegC(char value){unsigned int i;char * Flash_ptr; // Initialize Flash pointerFlash_ptr = (char *) 0x1880;__disable_interrupt(); // 5xx Workaround: Disable global// interrupt while erasing. Re-Enable// GIE if neededFCTL3 = FWKEY; // Clear Lock bitFCTL1 = FWKEY+ERASE; // Set Erase bit*Flash_ptr = 0; // Dummy write to erase Flash seg FCTL1 = FWKEY+WRT; // Set WRT bit for write operationfor (i = 0; i < 128; i++){*Flash_ptr++ = value++; // Write value to flash}FCTL1 = FWKEY; // Clear WRT bitFCTL3 = FWKEY+LOCK; // Set LOCK bit}//------------------------------------------------------------------------------// Copy Seg C to Seg D//------------------------------------------------------------------------------void copy_C2D(void){unsigned int i;char *Flash_ptrC;char *Flash_ptrD;Flash_ptrC = (char *) 0x1880; // Initialize Flash segment C ptrFlash_ptrD = (char *) 0x1800; // Initialize Flash segment D ptr__disable_interrupt(); // 5xx Workaround: Disable global// interrupt while erasing. Re-Enable// GIE if neededFCTL3 = FWKEY; // Clear Lock bitFCTL1 = FWKEY+ERASE; // Set Erase bit*Flash_ptrD = 0; // Dummy write to erase Flash seg D FCTL1 = FWKEY+WRT; // Set WRT bit for write operationfor (i = 0; i < 128; i++){*Flash_ptrD++ = *Flash_ptrC++; // copy value segment C to seg D}FCTL1 = FWKEY; // Clear WRT bitFCTL3 = FWKEY+LOCK; // Set LOCK bit}//***************************************************************************** *// CC430x613x Demo - LCD display a single character//// Description: Cycle through several characters in a single position on the// LCDBA from Softbaugh. Put "0123456" on SBLCDA4 LCD.// ACLK = REF0 = 32Khz, MCLK = SMCLK = DCO = Default//// MSP430x631x// -----------------// /|\| |// | | |// --|RST |// | | SBLCDA4// | S4 | -----------------// | - |--> | + 5 4 3 2 1 0 |// | S5 | -----------------// | COM0|-----||||// | COM1|------|||// | COM2|-------||// | COM3|--------|// | |////// Texas Instruments Inc.// Built with CCE Version: 3.2.2.1.4//***************************************************************************** *#include "cc430x613x.h"// LCD Segments#define LCD_A BIT0#define LCD_B BIT1#define LCD_C BIT2#define LCD_D BIT3#define LCD_E BIT6#define LCD_F BIT4#define LCD_G BIT5#define LCD_H BIT7// LCD Segment Mappingconst unsigned char LCD_Char_Map[] ={LCD_A+LCD_B+LCD_C+LCD_D+LCD_E+LCD_F, // '0' or 'O'LCD_B+LCD_C, // '1' or 'I'LCD_A+LCD_B+LCD_D+LCD_E+LCD_G, // '2' or 'Z'LCD_A+LCD_B+LCD_C+LCD_D+LCD_G, // '3'LCD_B+LCD_C+LCD_F+LCD_G, // '4' or 'y'LCD_A+LCD_C+LCD_D+LCD_F+LCD_G, // '5' or 'S'LCD_A+LCD_C+LCD_D+LCD_E+LCD_F+LCD_G, // '6' or 'b'LCD_A+LCD_B+LCD_C, // '7'LCD_A+LCD_B+LCD_C+LCD_D+LCD_E+LCD_F+LCD_G, // '8' or 'B'LCD_A+LCD_B+LCD_C+LCD_D+LCD_F+LCD_G, // '9' or 'g'};void main(void){ volatile unsigned char i;P5SEL |= (BIT5 | BIT6 | BIT7);P5DIR |= (BIT5 | BIT6 | BIT7);//***************************************************************************** **// Configure LCD_B//LCD_FREQ = ACLK/32/4, LCD Mux 4, turn on LCDLCDBCTL0 = (LCDDIV0 + LCDDIV1 + LCDDIV2 + LCDDIV3 + LCDDIV4)| LCDPRE0 | LCD4MUX | LCDON | LCDSON;LCDBVCTL = LCDCPEN | VLCD_3_44;//LCDBCTL0 |= LCDON + LCDSON;REFCTL0 &= ~REFMSTR;//Charge pump generated internally at 3.44V, external bias (V2-V4) generation//Internal reference for charge pumpLCDBPCTL0 = 0x0030; //Select LCD Segments 4-5 LCDBPCTL1 = 0x0000; //while(1){for(i=6;i>0;i--){LCDM3 &= ~LCD_Char_Map[8]; // Clear LCDLCDM3 |= LCD_Char_Map[i-1]; // Display Character__delay_cycles(500000);}}}//***************************************************************************** *// CC430x613x Demo - Enters LPM3 (ACLK = LFXT1)//// Description: Configure ACLK = LFXT1 and enters LPM3. Measure current.// Note: SVS(H,L) & SVM(H,L) are disabled// ACLK = LFXT1 = 32kHz, MCLK = SMCLK = default DCO//// CC430x613x// -----------------// /|\ | XIN|-// | | | 32kHz// ---|RST XOUT|-// | |//// M. Morales// Texas Instruments Inc.// April 2009// Built with CCE Version: 3.2.2 and IAR Embedded Workbench Version: 4.11B//***************************************************************************** *#include "cc430x613x.h"void main(void){WDTCTL = WDTPW+WDTHOLD; // Stop WDTP5SEL |= BIT0 + BIT1; // Select XT1UCSCTL6 |= XCAP_3; // Internal load cap// Loop until XT1,XT2 & DCO stabilizesdo{UCSCTL7 &= ~(XT1LFOFFG + DCOFFG);// Clear LFXT1,DCO fault flags SFRIFG1 &= ~OFIFG; // Clear fault flags}while (SFRIFG1 & OFIFG); // Test oscillator fault flagUCSCTL6 &= ~(XT1DRIVE_3); // Xtal is now stable, reduce drive// strengthP1OUT = 0x00; P2OUT = 0x00; P3OUT = 0x00; P4OUT = 0x00; P5OUT = 0x00;P1DIR = 0xFF; P2DIR = 0xFF; P3DIR = 0xFF; P4DIR = 0xFF; P5DIR = 0xFC;PJOUT = 0x00;PJDIR = 0xFF;// Turn off SVSH, SVSMPMMCTL0_H = 0xA5;SVSMHCTL = 0;SVSMLCTL = 0;PMMCTL0_H = 0x00;__bis_SR_register(LPM3_bits); // Enter LPM3__no_operation(); // For debugger}//***************************************************************************** *// CC430F613x Demo - LFXT1 Oscillator Fault Detection//// Description: System runs normally in LPM3 with with basic timer clocked by// 32kHz ACLK with a 1 second interrupt. If an LFXT1 oscillator fault occurs,// NMI is requested forcing exit from LPM3. P1.0 is toggled rapidly by// software as long as LFXT1 oscillator fault is present. Assuumed only// LFXT1 as NMI source - code does not check for other NMI sources.// ACLK = LFXT1 = 32768Hz, MCLK = SMCLK = default DCO = 32 x ACLK = 1048576Hz // //* An external watch crystal between XIN & XOUT is required for ACLK *//////// CC430F6137// -----------------// /|\ | XIN|-// | | | 32kHz// ---|RST XOUT|-// | |// | P1.0|-->LED//// M. Morales// Texas Instruments Inc.// April 2009// Built with CCE Version: 3.2.2 and IAR Embedded Workbench Version: 4.11B//***************************************************************************** *#include "cc430x613x.h"volatile unsigned int i;void main(void){WDTCTL = WDTPW + WDTHOLD; // Stop WDT// Set up XT1P5SEL |= BIT0 + BIT1; // Analog function for XT1 PinsUCSCTL6 |= XCAP_3; // Internal load capP1DIR |= BIT0; // P1.0 outputRTCCTL01 = RTCTEV_3;RTCPS0CTL = RT0PSDIV_7; // Set RTPS0 to /256RTCPS1CTL = RT1IP_6 + RT1PSIE + RT1SSEL_3;// Set RT1IP to /4, enable// RT1PS interrupt and select// RTOPS output as clockSFRIE1 = OFIE; // Enable osc fault interrupt__bis_SR_register(LPM3_bits + GIE); // Enter LPM3, enable interrupts__no_operation(); // For debugger}// RTC Interrupt Service Routine#pragma vector=RTC_VECTOR__interrupt void RTC_ISR(void){P1OUT ^= 0x01; // Toggle P1.0RTCCTL01 &= ~RTCTEVIFG;RTCPS1CTL &= ~RT1PSIFG;}#pragma vector=UNMI_VECTOR__interrupt void UNMI_ISR(void){do{UCSCTL7 &= ~(XT1LFOFFG + DCOFFG); // Clear XT1 & DCO fault flagsSFRIFG1 &= ~OFIFG; // Clear OSC Fault flagfor (i = 0xFFFF; i > 0; i--); // Time for flag to setP1OUT ^= BIT0; // Toggle P1.0 using exclusive-OR}while ( (SFRIFG1 & OFIFG) );}//****************************************************************************// // Function Library for setting the PMM//// This file is used in conjunction with PMM.c to set the core// voltage level of a device. To set a core voltage level, call// SetVCore(level). See RF project(s) for example usage.//// Original programm Stefan Schauer// Rev 1.1: changed VCoreUp to fit with recommended flow (09/04/2008)////****************************************************************************// #include "cc430x613x.h"#include "PMM.h"//****************************************************************************// // Set VCore level// SetVCore level is called from the user API//****************************************************************************// void SetVCore (unsigned char level) // Note: change level by one step only{unsigned char actLevel;do {actLevel = PMMCTL0_L & PMMCOREV_3;if (actLevel < level)SetVCoreUp(++actLevel); // Set VCore (step by step)if (actLevel > level)SetVCoreDown(--actLevel); // Set VCore (step by step)}while (actLevel != level);}//****************************************************************************// // Set VCore up//****************************************************************************// void SetVCoreUp (unsigned char level) // Note: change level by one step only{PMMCTL0_H = 0xA5; // Open PMM module registers for write accessSVSMHCTL = SVSHE + SVSHRVL0 * level + SVMHE + SVSMHRRL0 * level; // Set SVS/M high side to new levelSVSMLCTL = SVSLE + SVMLE + SVSMLRRL0 * level; // Set SVM new Levelwhile ((PMMIFG & SVSMLDL YIFG) == 0); // Wait till SVM is settled (Delay) PMMCTL0_L = PMMCOREV0 * level; // Set VCore to xPMMIFG &= ~(SVMLVLRIFG + SVMLIFG); // Clear already set flagsif ((PMMIFG & SVMLIFG))while ((PMMIFG & SVMLVLRIFG) == 0); // Wait till level is reachedSVSMLCTL = SVSLE + SVSLRVL0 * level + SVMLE + SVSMLRRL0 * level; // Set SVS/M Low side to new levelPMMCTL0_H = 0x00; // Lock PMM module registers for write access}//****************************************************************************// // Set VCore down//****************************************************************************// void SetVCoreDown (unsigned char level){PMMCTL0_H = 0xA5; // Open PMM module registers for write accessSVSMLCTL = SVSLE + SVSLRVL0 * level + SVMLE + SVSMLRRL0 * level; // Set SVS/M Low side to new levelwhile ((PMMIFG & SVSMLDL YIFG) == 0); // Wait till SVM is settled (Delay) PMMCTL0_L = (level * PMMCOREV0); // Set VCore to 1.85 V for Max Speed.PMMCTL0_H = 0x00; // Lock PMM module registers for write access}//****************************************************************************////***************************************************************************** *// CC430x613x Demo - Port Mapping Port2; Single runtime configuration//// Description: Port2 is port mapped to output TimerA digital signals. TACCR1-3// generate different PWM DutyCycles. TACCR0 generates a square wave of// freq ACLK/2^10 ~32Hz.// MCLK = SMCLK = default DCO; ACLK = REFO~32kHz;//// CC430x613x// ------------------// /|\| |// | | |// --|RST |// | P2.0(TA0CCR0)|--> ACLK/2^10 ~ 32Hz// | P2.2(TA0CCR1)|--> 25%// | P2.4(TA0CCR2)|--> 50%// | P2.6(TA0CCR3)|--> 75%// | P2.7(PM_None)|--> DVSS//// M Morales// Texas Instruments Inc.// April 2009// Built with CCE Version: 3.2.2 and IAR Embedded Workbench Version: 4.11B//***************************************************************************** *#include "cc430x613x.h"// Function Definitionvoid Port_Mapping(void);void main(void){WDTCTL = WDTPW + WDTHOLD; // Stop WDTPMAPPWD = 0x02D52; // Get write-access to port mapping regs P2MAP0 = PM_TA0CCR0A; // Map CBOUT output to P1.6P2MAP2 = PM_TA0CCR1A;P2MAP4 = PM_TA0CCR2A;P2MAP6 = PM_TA0CCR3A;P2MAP7 = PM_NONE;PMAPPWD = 0; // Lock port mapping registers// Setup Port PinsP2DIR |= BIT0+BIT2+BIT4+BIT6+BIT7; // P2.0,2,4,6,7 outputP2SEL |= BIT0+BIT2+BIT4+BIT6+BIT7; // P2.0,2,4,6,7 Port Map functions// Setup TB0TA0CCTL0 = OUTMOD_4; // CCR1 toggle/setTA0CCR0 = 256; // PWM Period/2TA0CCTL1 = OUTMOD_6; // CCR1 toggle/setTA0CCR1 = 192; // CCR1 PWM duty cycleTA0CCTL2 = OUTMOD_6; // CCR2 toggle/setTA0CCR2 = 128; // CCR2 PWM duty cycleTA0CCTL3 = OUTMOD_6; // CCR3 toggle/setTA0CCR3 = 64; // CCR3 PWM duty cycleTA0CTL = TASSEL__ACLK + MC_3; // ACLK, up-down mode__bis_SR_register(LPM3_bits); // Enter LPM3__no_operation(); // For debugger}//***************************************************************************** *// CC430F613x Demo - RTC in Counter Mode toggles P1.0 every 1s//// This program demonstrates RTC in counter mode configured to source from ACLK// to toggle P1.0 LED every 1s.//// CC430F6137// -----------------// /|\ | |// | | |// ---|RST |// | |// | P1.0|-->LED//// M Morales// Texas Instruments Inc.// April 2009// Built with CCE Version: 3.2.2 and IAR Embedded Workbench Version: 4.11B//***************************************************************************** *#include "cc430x613x.h"void main(void){WDTCTL = WDTPW+WDTHOLD;P1OUT |= 0x01;P1DIR |= 0x01;// Setup RTC TimerRTCCTL01 = RTCTEVIE + RTCSSEL_2 + RTCTEV_0; // Counter Mode, RTC1PS, 8-bit ovf// overflow interrupt enableRTCPS0CTL = RT0PSDIV_2; // ACLK, /8, start timerRTCPS1CTL = RT1SSEL_2 + RT1PSDIV_3; // out from RT0PS, /16, start timer__bis_SR_register(LPM3_bits + GIE);}#pragma vector=RTC_VECTOR__interrupt void RTC_ISR(void){switch(__even_in_range(RTCIV,16)){case 0: break; // No interruptscase 2: break; // RTCRDYIFGcase 4: // RTCEVIFGP1OUT ^= 0x01;break;case 6: break; // RTCAIFGcase 8: break; // RT0PSIFGcase 10: break; // RT1PSIFGcase 12: break; // Reservedcase 14: break; // Reservedcase 16: break; // Reserveddefault: break;}}//***************************************************************************** *// CC430F613x Demo - Timer_A3, Toggle P1.0, CCR0 Up Mode ISR, 32kHz ACLK//// Description: Toggle P1.0 using software and the TA_1 ISR. Timer1_A is// configured for up mode, thus the timer overflows when TAR counts// to CCR0. In this example, CCR0 is loaded with 1000-1.// Toggle rate = 32768/(2*1000) = 16.384// ACLK = TACLK = 32768Hz, MCLK = SMCLK = default DCO ~1.045MHz//// CC430F6137// ---------------// /|\| |// | | |// --|RST |// | |// | P1.0|-->LED//// M Morales// Texas Instruments Inc.// April 2009// Built with CCE Version: 3.2.2 and IAR Embedded Workbench Version: 4.11B//***************************************************************************** *#include "cc430x613x.h"void main(void){WDTCTL = WDTPW + WDTHOLD; // Stop WDTP1DIR |= 0x01; // P1.0 outputTA1CCTL0 = CCIE; // CCR0 interrupt enabledTA1CCR0 = 1000-1;TA1CTL = TASSEL_1 + MC_1 + TACLR; // ACLK, upmode, clear TAR__bis_SR_register(LPM3_bits + GIE); // Enter LPM3, enable interrupts__no_operation(); // For debugger}// Timer A0 interrupt service routine#pragma vector=TIMER1_A0_VECTOR__interrupt void TIMER1_A0_ISR(void){P1OUT ^= 0x01; // Toggle P1.0}//***************************************************************************** *// CC430F613x Demo - FLL+, Runs Internal DCO at 2.45MHz with LFXT1 as Ref//// Description: This program demonstrates setting the internal DCO to run at// 2.45MHz with auto-calibration by the FLL+ circuitry. It uses LFXT1 as FLL// reference.// ACLK = LFXT1 = 32768Hz, MCLK = SMCLK = DCO = (74+1) x REFO = 2457600Hz//// CC430F6137// -----------------// /|\ | XIN|-// | | | 32kHz// ---|RST XOUT|-// | |// | P2.2 |--> MCLK = 2.45MHz// | |// | P2.0 |--> ACLK = 32kHz// | |//// M Morales// Texas Instruments Inc.// April 2009// Built with CCE v3.1 Build 3.2.3.6.4 & IAR Embedded Workbench Version: 4.11B//***************************************************************************** *#include "cc430x613x.h"void main(void){WDTCTL = WDTPW + WDTHOLD; // Stop watchdog timerP1DIR |= BIT0; // P1.0 outputPMAPPWD = 0x02D52; // Get write-access to port mapping regs P2MAP0 = PM_ACLK; // Map ACLK output to P2.0P2MAP2 = PM_MCLK; // Map MCLK output to P2.2 PMAPPWD = 0; // Lock port mapping registersP2DIR |= BIT0 + BIT2; // ACLK, MCLK, SMCLK set out to pinsP2SEL |= BIT0 + BIT2; // P2.0,2 for debugging purposes.// Initialize LFXT1P5SEL |= 0x03; // Select XT1UCSCTL6 |= XCAP_3; // Internal load cap// Loop until XT1 fault flag is cleareddo{UCSCTL7 &= ~XT1LFOFFG; // Clear XT1 fault flags}while (UCSCTL7&XT1LFOFFG); // Test XT1 fault flag// Initialize DCO to 2.45MHz__bis_SR_register(SCG0); // Disable the FLL control loopUCSCTL0 = 0x0000; // Set lowest possible DCOx, MODx UCSCTL1 = DCORSEL_3; // Set RSELx for DCO = 4.9 MHz UCSCTL2 = FLLD_1 + 74; // Set DCO Multiplier for 2.45MHz// (N + 1) * FLLRef = Fdco// (74 + 1) * 32768 = 2.45MHz// Set FLL Div = fDCOCLK/2__bic_SR_register(SCG0); // Enable the FLL control loop// Worst-case settling time for the DCO when the DCO range bits have been// changed is n x 32 x 32 x f_MCLK / f_FLL_reference. See UCS chapter in 5xx// UG for optimization.// 32 x 32 x 2.45 MHz / 32,768 Hz = 76563 = MCLK cycles for DCO to settle__delay_cycles(76563);// Loop until XT1,XT2 & DCO fault flag is cleareddo{UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + XT1HFOFFG + DCOFFG);// Clear XT2,XT1,DCO fault flags SFRIFG1 &= ~OFIFG; // Clear fault flags}while (SFRIFG1&OFIFG); // Test oscillator fault flagwhile(1){P1OUT ^= BIT0; // Toggle P1.0__delay_cycles(600000); // Delay}}//***************************************************************************** *// CC430F613x Demo - USCI_A0, 115200 UART Echo ISR, DCO SMCLK//// Description: Echo a received character, RX ISR used. Normal mode is LPM0.// USCI_A0 RX interrupt triggers TX Echo.// Baud rate divider with 1048576hz = 1048576/115200 = ~9.1 (009h|01h)// ACLK = REFO = ~32768Hz, MCLK = SMCLK = default DCO = 32 x ACLK = 1048576Hz // See User Guide for baud rate divider table//// CC430F6137// -----------------// /|\| |// | | |// --|RST |// | |// | P2.7/UCA0TXD|------------>// | | 115200 - 8N1// | P2.6/UCA0RXD|<------------//// M Morales// Texas Instruments Inc.// April 2009// Built with CCE Version: 3.2.2 and IAR Embedded Workbench Version: 4.11B。