EDA复习

1EDA总结cy考试题型：简答+编程（会从讲过的程序和书上的程序中出，不过，会有改动，可作参考）一．概念：1.EDA技术含义、特点p12.PLD可编程逻辑器件优点p20FPGA/CPLD p43.EDA软件开发工具p5 EDA软件系统的构成p64.EDA的工程设计流程p95.数字系统的设计步骤p176.VHDL的优点p1137.VHDL程序的基本结构：库、程序包使用说明/实体描述/结构体描述8.常用库：IEEE 默认关闭的STD 默认打开的WORK 当前工作库9.程序包p11910.VHDL文字规则p12611.VHDL数据对象p12812.IN 输入OUT 输出INOUT 双向BUFFER 缓冲13.敏感参量表与wait语句不共存，有wait语句则只能PROCESS IS14.进程里，多个赋值源给同一个信号赋值，只取最后一个15.同步复位：时钟信号后异步复位：时钟信号前16.变量赋值目标：=赋值源；信号赋值目标：=赋值源；17.IF条件语句p146CASE选择语句p148LOOP循环语句（WHILE/FOR)p151NEXT和EXIT语句p152WAIT语句（WAIT UNTIL）p154进程语句（PROCESS)p167条件信号赋值语句（WHEN...ELSE)p174选择信号赋值语句（WITH...SELECT)p175元件例化语句p177生成语句p17818.过程：过程首（不是必须的）+过程体（可以独立存在和使用）二．课上练习程序+实验程序：（1）与门LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL; ENTITY MYAND2 ISPORT(A,B:IN STD_LOGIC;Y:OUT STD_LOGIC);END ENTITY MYAND2; ARCHITECTURE ART OF MYAND2 IS BEGINY<=A AND B;END ARCHITECTURE ART;（2）4选1数据选择器a)IF ELSE语句LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL; ENTITY MUX41 ISPORT(A,B,C,D:IN STD_LOGIC;S1,S0:IN STD_LOGIC;Y:OUT STD_LOGIC);END ENTITY MUX41; ARCHITECTURE ART OF MUX41 IS BEGINPROCESS(S1,S0,A,B,C,D)BEGINIF S1='0' AND S0='0' THENY<=A;ELSIF S1='0' AND S0='1' THENY<=B;ELSIF S1='1' AND S0='0' THENY<=C;ELSE Y<=D;END IF;END PROCESS;END ARCHITECTURE ART;b)WHEN ELSE语句LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; ENTITY MUX41 ISPORT(S1，S0：IN STD_LOGIC;A,B,C,D:IN STD_LOGIC;Y:OUT STD_LOGIC);END ENTITY MUX41;ARCHITTECTURE ART OF MUX41 ISBEGINY<=D WHEN S1=‘1’AND S0= ‘1’ELSEC WHEN S1= ‘1’AND S0= ‘0’ELSEB WHEN S1= ‘0’AND S0= ‘1’ELSEA WHEN S1= ‘0’AND S0= ‘0’ELSE‘X’;END ARCHITECTURE ART;C)CASE语句LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY MUX41 ISPORT(S1，S2：IN STD_LOGIC;A,B,C,D:IN STD_LOGIC;Z:OUT STD_LOGIC);END ENTITY MUX41;ARCHITECTURE ART OF MUX41 ISSIGNAL S:STD_LOGIC_VECTOR(1 DOWNTO 0); BEGINS<=S1&S2;PROCESS(S,A,B,C,D) ISBEGINCASE S ISWHEN “00”=> Z<=A;WHEN “01”=> Z<=B;WHEN “10”=> Z<=C;WHEN “11”=> Z<=D;END CASE;END PROCESS;END ARCHITECTURE ART;（3）2线-4线译码器(IF...ELSE)LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY DECODER ISPORT(A:IN STD_LOGIC_VECTOR(1 DOWNTO 0);Y:OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); END ENTITY DECODER;ARCHITECTURE ART OF DECODER ISBEGINPROCESS(A) ISBEGINIF A=”00”THENY<=”1110”;ELSIF A=”01”THENY<=”1101”;ELSIF A=”10”THENY<=”1011”;ELSE Y<=”0111”;END IF;END PROCESS;END ARCHITECTURE ART;（4）半加器(CASE...WHEN)LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY H_ADDER ISPORT(A,B:IN STD_LOGIC;CO,SO:OUT STD_LOGIC);END ENTITY H_ADDER;ARCHITECTURE ART OF H_ADDER IS SIGNAL S:STD_LOGIC_VECTOR(1 DOWNTO 0); SIGNAL Y:STD_LOGIC_VECTOR(1 DOWNTO 0); BEGINS=A&B;PROCESS(S) ISBEGINCASE S ISWHEN “00”=> Y<=“00”;WHEN “01”=> Y<=“01”;WHEN “10”=> Y<=“01”;WHEN “11”=> Y<=“10”;WHEN OTHERS => NULL;END CASE;END PROCESS;CO<=Y(0);SO<=Y(1);END ARCHITECTURE ART;（5）3-8译码器(CASE...WHEN)LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY DECODER38 ISPORT(S1，S2，S3:IN STD_LOGIC;A2，A1，A0：IN STD_LOGIC;Y:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); END ENTITY DECODER38;ARCHITECTURE ART OF DECODER38 ISSIGNAL S:STD_LOGIC_VECTOR(2 DOWNTO 0); SIGNAL D:STD_LOGIC_VEDTOR(2 DOWNTO 0); BEGINS<=S1&S2&S3;D<=A2&A1&A0;PROCESS(S,D) ISBEGINIF S= “100”THENCASE D ISWHEN “000”=> Y<= “0000 0001”;WHEN “001”=> Y<= “0000 0010”;WHEN “010”=> Y<= “0000 0100”;WHEN “011”=> Y<= “0000 1000”;WHEN “100”=> Y<= “0001 0000”;WHEN “101”=> Y<= “0010 0000”;WHEN “110”=> Y<= “0100 0000”;WHEN “111”=> Y<= “1000 0000”;WHEN OTHERS=>NULL;END CASE;END IF;END PROCESS;END ARCHITECTURE ART;（6）4线-2线优先编码器(WHEN...ELSE)LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;ENTITY ENCODER ISPORT(A,B,C,D:IN STD_LOGIC;Y0，Y1：OUT STD_LOGIC);END ENTITY ENCODER;ARCHITECTURE ART OF ENCODER ISSIGNAL SY:STD_LOGIC_VECTOR(1 DOWNTO 0); BEGINSY(1 DOWNTO 0)<= “11”WHEN D= ‘1’ELSE“10”WHEN C= ‘1’ELSE“01”WHEN B= ‘1’ELSE“00”WHEN A= ‘1’ELSE“XX”;Y0<=SY(0);Y1<=SY(1);END ARCHITECTURE ART;a)CASE WHENLIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY ADDER ISPORT(A,B,C:IN STD_LOGIC;S0,C0:OUT STD_LOGIC);END ENTITY ADDER;ARCHITECTURE ART OF ADDER ISSIGNAL X:STD_LOGIC_VECTOR(2 DOWNTO 0); BEGINX<=A&B&C;PROCESS(X)ISBEGINCASE X ISWHEN"000"=>S0<='0';C0<='0'; WHEN"001"=>S0<='1';C0<='0'; WHEN"010"=>S0<='1';C0<='0'; WHEN"011"=>S0<='0';C0<='1'; WHEN"100"=>S0<='1';C0<='0'; WHEN"101"=>S0<='0';C0<='1'; WHEN"110"=>S0<='0';C0<='1'; WHEN"111"=>S0<='1';C0<='1';END CASE;END PROCESS;END ARCHITECTURE ART;b)IF ELSELIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY ADDER ISPORT(A,B,C:IN STD_LOGIC;S0,C0:OUT STD_LOGIC);END ENTITY ADDER;ARCHITECTURE ART OF ADDER ISSIGNAL X:STD_LOGIC_VECTOR(2 DOWNTO 0); BEGINX<=A&B&C;PROCESS(X)ISBEGINIF X="000"THEN S0<='0';C0<='0';ELSIF X="001"THEN S0<='1';C0<='0';ELSIF X="010"THEN S0<='1';C0<='0';ELSIF X="011"THEN S0<='0';C0<='1';ELSIF X="100"THEN S0<='1';C0<='0';ELSIF X="101"THEN S0<='0';C0<='1';ELSIF X="110"THEN S0<='0';C0<='1';ELSIF X="111"THEN S0<='1';C0<='1';ELSE NULL;END IF;END PROCESS;END ARCHITECTURE ART;c）WHEN ELSELIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY ADDER ISPORT(A,B,C:IN STD_LOGIC;S0,C0:OUT STD_LOGIC);END ENTITY ADDER;ARCHITECTURE ART OF ADDER ISSIGNAL SY:STD_LOGIC_VECTOR(1 DOWNTO 0); SIGNAL X:STD_LOGIC_VECTOR(2 DOWNTO 0); BEGINX<=A&B&C;SY(1 DOWNTO 0)<="00"WHEN X="000"ELSE"10"WHEN X="001"ELSE"10"WHEN X="010"ELSE"01"WHEN X="011"ELSE"10"WHEN X="100"ELSE"01"WHEN X="101"ELSE"01"WHEN X="110"ELSE"11"WHEN X="111"ELSE"XX";S0<=SY(0);C0<=SY(1);END ARCHITECTURE ART;d）WITH SELECTLIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY ADDER ISPORT(A,B,C:IN STD_LOGIC;S0,C0:OUT STD_LOGIC);END ENTITY ADDER;ARCHITECTURE ART OF ADDER ISSIGNAL SY:STD_LOGIC_VECTOR(1 DOWNTO 0); SIGNAL X:STD_LOGIC_VECTOR(2 DOWNTO 0); BEGINX<=A&B&C;WITH X SELECTSY<="00" WHEN "000","10" WHEN "001","10" WHEN "010","01" WHEN "011","10" WHEN "100","01" WHEN "101","01" WHEN "110","11" WHEN OTHERS;S0<=SY(0);C0<=SY(1);END ARCHITECTURE ART;（7）分频器（50MHz--->1Hz )LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY JYFP ISPORT(CLK_IN:IN STD_LOGIC;RESET:IN STD_LOGIC;CLK_OUT:OUT STD_LOGIC);END ENTITY JYFP;ARCHITECTURE ART OF JYFP ISCONSTANT DIVIDE_PERIOD:INTEGER:=5E7; BEGINPROCESS(CLK_IN,RESET)ISVARIABLE CNT:INTEGER RANGE 0 TO 49_999_999; BEGINIF(RESET='1')THENCNT:=0;CLK_OUT<='0';ELSIF RISING_EDGE(CLK_IN)THENIF(CNT<(DIVIDE_PERIOD/2))THENCLK_OUT<='1';CNT:=CNT+1;ELSIF(CNT<(DIVIDE_PERIOD-1))THENCLK_OUT<='0';CNT:=CNT+1;ELSECNT:=0;END IF;END IF;END PROCESS DIVIDE_CLK;END ARCHITECTURE ART;（8）计数显示LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY C ISPORT( CLK : IN STD_LOGIC;RESET: IN STD_LOGIC;KEY : IN STD_LOGIC_VECTOR(3 DOWNTO 0);LEDAG : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);DEL : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)); END ENTITY C;ARCHITECTUREART OF C ISSIGNAL CLK1:STD_LOGIC;CONSTANT DIVIDE_PERIOD:INTEGER:=5E7;BEGINPROCESS(CLK,RESET) ISVARIABLE CNT:INTEGER RANGE 0 TO 49_999_999;BEGINIF(RESET='1')THENCNT:=0;CLK1<='0';ELSIF RISING_EDGE(CLK) THENIF(CNT<(DIVIDE_PERIOD/2)) THENCLK1<='1';CNT:=CNT+1;ELSIF(CNT<(DIVIDE_PERIOD-1)) THENCLK1<='0';CNT:=CNT+1;ELSECNT:=0;END IF;END IF;END PROCESS DIVIDE_CLK;PROCESS(CLK)VARIABLE DOUNT : STD_LOGIC_VECTOR(2 DOWNTO 0); BEGINIF CLK'EVENT AND CLK='1' THENDOUNT:=DOUNT+1;END IF;DEL<=DOUNT;END PROCESS;PROCESS(KEY)BEGINCASE KEY ISWHEN "0000" => LEDAG <="0111111";WHEN "0001" => LEDAG <="0000110";WHEN "0010" => LEDAG <="1011011";WHEN "0011" => LEDAG <="1001111";WHEN "0100" => LEDAG <="1100110";WHEN "0101" => LEDAG <="1101101";WHEN "0110" => LEDAG <="1111101";WHEN "0111" => LEDAG <="0000111";WHEN "1000" => LEDAG <="1111111";WHEN "1001" => LEDAG <="1101111";WHEN "1010" => LEDAG <="1110111";WHEN "1011" => LEDAG <="1111100";WHEN "1100" => LEDAG <="0111001";WHEN "1101" => LEDAG <="1011110";WHEN "1110" => LEDAG <="1111001";WHEN "1111" => LEDAG <="1110001";WHEN OTHERS => NULL;END CASE;END PROCESS;END ARCHITECTURE ART;（9）带有异步复位的十进制计数器LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CNT10 ISPORT(RST,CLK:IN STD_LOGIC;QOUT:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);COUT:OUT STD_LOGIC));END ENTITY CNT10;ARCHITECTURE ART OF CNT10 ISSIGNAL Q:STD_LOGIC_VECTOR(3 DOWNTO 0);BEGINPROCESS (CLK,RST) ISBEGINIF RST= ‘0’THENQ<=“0000”;COUT<= ‘0’;ELSIF CLK’EVENT AND CLK= ‘1’ THENIF RST= “1001” THENQ<= “0000”;COUT<= ‘1’;ELSEQ<=Q+1;COUT<= ‘0’;END IF;END IF;END PROCESS;QOUT<=Q;END ARCHITECTURE ART;在以上基础，加同步置数控制LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CNT10 ISPORT(CLK,RST,LD:IN STD_LOGIC;D:IN STD_LOGIC_VECTOR(3 DOWNTO 0);COUT:OUT STD_LOGIC;QOUT:BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0)); END ENTITY CNT10;ARCHITECTURE ART OF CNT10 ISBEGINPROCESS (CLK,RST,LD,D) ISBEGINIF RST= ‘0’ THENQOUT<=“0000”;COUT<= ‘0’;ELSIF CLK’EVENT AND CLK= ‘1’ THENIF LD= ‘0’ THENQOUT<=D；COUT<= ‘0’;ELSIF QOUT=“1001” THENQOUT<=“0000”;COUT<= ‘1’;ELSEQOUT<=QOUT+1;COUT<= ‘0’;END IF;END IF;END PROCESS;END ARCHITECTURE ART;在以上基础，加计数LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CNT10 ISPORT(RST,CLK,LD,EN:IN STD_LOGIC;D:IN STD_LOGIC_VECTOR(3 DOWNTO 0);COUT:OUT STD_LOGIC;QOUT:BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0)); END ENTITY CNT10;ARCHITECTURE ART OF CNT10 ISBEGINPROCESS (CLK,RST,LD,D,EN) ISBEGINIF RST= ‘0’ THENQOUT<=“0000”;COUT<= ‘0’;ELSIF CLK’EVENT AND CLK= ‘1’ THENIF LD= ‘0’ THENQOUT<=D；COUT<= ‘0’;ELSIF EN= ‘0’ THENIF QOUT=9 THENQOUT<= “0000”;COUT<= ‘1’;ELSEQOUT<=QOUT+1;COUT<= ‘0’;END IF;END IF;END PROCESS;END ARCHITECTURE ART;三．书上程序：1. 74LS00的VHDL设计过程P1142. 3选1选择器P1473. 8线-3线优先编码器P147 IF...ELSE4.用IF语句和CASE 语句共同描述4选1选择器P1505.两元素位矢量值比较器6.可预置校验对比值的四位奇偶校验电路P1547.十进制加法计数器P168，P1698.三态缓冲器电路P1709.8线-3线优先编码器P174 WHEN...ELSE10.指令译码器P17511.8位三态锁存器P18012.重载函数（4位二进制加法计数器<=>十六进制）P18413.4位二进制数BCD码译成7段码数码管P18914.带异步复位功能的8位二进制加法计数器P19015.一位全加器的数据流描述P19116.一位全加器的结构体描述P19217.3线-8线译码器（4种方法）P19418.8线-3线优先编码器（3种方法）P19619.比较器P19720.选择器P19821.三态门电路P19922.单向总线驱动器P19923.双向总线缓冲器P20024.D触发器P20125.非同步复位/置位的D触发器P20126.同步复位的D触发器P20227.JK触发器P20228.8位数据寄存（锁存）器P20329.具有左移或右移一位、并行输入和同步复位功能的8位移位寄存器P20430.带时钟使能的十进制同步计数器P20531.具有异步复位、同步置位功能的8421BCD码60进制同步计数器片P20532.由8个D触发器构成的异步计数器P20633.将1KHz的方波信号变为正、负周不等的50Hz信号的非均匀分频电路P20834.将1KHz的方波信号变为正、负周相等的50Hz信号的均匀分频电路P20935.通用的可输出输入信号的2分频信号、4分频信号、8分频信号、16分频信号、2位2分频信号序列、2位4分频信号序列的分频电路P20936.“01111110”序列信号发生器P210（彩灯）37.20位的M序列发生器P21138.“01111110”序列信号检测器P21239.设计一个序列信号检测器，当一串待检测的串行数据进入检测器后，若此数在每一位的连续检测都与预置的密码数相同，则输出“A”,否则仍然输出“B”P213(密码锁）40.只读存储器ROM P21541.双口SRAM P21642.FIFO先进先出栈P217。