PicoBlaze IO & Interrupt Interface

Unsigned Multiplication Subroutine (2)
mult_soft: load s5, 00 ;clear s5 load s2, 08 ;initialize loop index mult_loop: sr0 s4 ;shift lsb to carry jump nc, shift_prod ;lsb is 0 add s5, s3 ;lsb is 1 shift_prod: sra s5 ;shift upper byte right, ;carry to MSB, LSB to carry sra s6 ;shift lower byte right, ;lsb of s5 to MSB of s6 sub s2, 01 ;dec loop index jump nz, mult_loop ;repeat until i=0 return
ECE 448 – FPGA and ASIC Design with VHDL
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Time-Multiplexed Seven Segment Display
ECE 448 – FPGA and ASIC Design with VHDL
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Block Diagram of the Hexadecimal Time-Multiplexing Circuit
ECE 448 – FPGA and ASIC Design with VHDL
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FIFO Interface
clk
rst
clk
rst
FIFO
din
8 full write
dout 8 empty read
ECE 448 – FPGA and ASIC Design with VHDL
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Operation of FIFO
Unsigned Multiplication – Basic Equations
p=ax x = x i 2i
i=0 k-1
k-1
p = a x = a x i 2i =
i=0
= x0a20 + x1a21 + x2a22 + … + xk-1a2k-1
Iterative Algorithm for Unsigned Multiplication Shift/Add Algorithm
Βιβλιοθήκη Baidu
a = s3
x = s4
Unsigned Multiplication Subroutine (1)
;========================================================= ; routine: mult_soft ; function: 8-bit unsigned multiplier using ; shift-and-add algorithm ; input register: ; s3: multiplicand ; s4: multiplier ; output register: ; s5: upper byte of product ; s6: lower byte of product ; temporary register: ; s2: index j ;=========================================================
ECE 448 – FPGA and ASIC Design with VHDL
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Interrupt Flow
ECE 448 – FPGA and ASIC Design with VHDL
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Timing Diagram of an Interrupt Event
ECE 448 – FPGA and ASIC Design with VHDL
ECE 448 – FPGA and ASIC Design with VHDL
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Output Decoding of Four Output Registers
ECE 448 – FPGA and ASIC Design with VHDL
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Timing Diagram of an Output Instruction
ECE 448 – FPGA and ASIC Design with VHDL
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Truth Table of a Decoding Circuit
ECE 448 – FPGA and ASIC Design with VHDL
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Block Diagram of Four Continuous-Access Ports
ak-1ak-2 . . . a1 a0
xk-1xk-2 . . . x1 x0 p2k-1p2k-2 . . . p2 p1 p0
Multiplication of two 4-bit unsigned binary numbers
Partial Product 0 Partial Product 1 Partial Product 2 Partial Product 3
ECE 448 – FPGA and ASIC Design with VHDL
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Timing Diagram of an Input Instruction
ECE 448 – FPGA and ASIC Design with VHDL
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Block Diagram of Four Single-Access Ports
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Example of a function in the PicoBlaze assembly language
ECE 448 – FPGA and ASIC Design with VHDL
Notation
a Multiplicand
x p Multiplier Product (a x)
p = a x = x0a20 + x1a21 + x2a22 + … + xk-1a2k-1 =
= (...((0 + x0a2k)/2 + x1a2k)/2 + ... + xk-1a2k)/2 =
k times
p(0) = 0 p(j+1) = (p(j) + xj a 2k) / 2 j=0..k-1
p = p(k)
Unsigned Multiplication Computations
8 bits pH +
C
8 bits pL p p(j)
xj a pH >> 1
C
+ xj a 28
pL pL pL = s6 2 p(j+1) p(j+1)
pH pH = s5
PicoBlaze Registers
12
ECE 448 – FPGA and ASIC Design with VHDL
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Interrupt Interface with a Single Event
ECE 448 – FPGA and ASIC Design with VHDL
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Interrupt Interface with Two Requests
ECE 448 – FPGA and ASIC Design with VHDL
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Hexadecimal Multiplexing Circuit Based on PicoBlaze and mod-500 Counter
ECE 448 – FPGA and ASIC Design with VHDL
Lecture 13 PicoBlaze I/O & Interrupt Interface
Example of Assembly Language Routine
ECE 448 – FPGA and ASIC Design with VHDL
Required reading
• P. Chu, FPGA Prototyping by VHDL Examples Chapter 16, PicoBlaze I/O Interface Chapter 17, PicoBlaze Interrupt Interface
Edit instructions - Shifts
*All shift instructions affect Zero and Carry flags