基于verilog的fsk调制与解调(呕心沥血,极度精简)
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先上程序（verilog语言编写）
`timescale 1ns/1ns // 测试程序
module test;
reg clk1,rst1,clk2,rst2;
reg din1;
wire dout1,ddout1;
modulator my1(.clk(clk1),.rst(rst1),.din(din1),.dout(dout1)); demodulator my2(.clk(clk2),.rst(rst2),.ddin(dout1),.ddout(ddout1));
initial
begin
clk1=0;
forever #25 clk1=~clk1;
end
initial
begin
clk2=0;
forever #10 clk2=~clk2;
end
initial
begin
rst1=1;
#15 rst1=0;
#50 rst1=1;
end
initial
begin
rst2=1;
#5 rst2=0;
#25 rst2=1;
end
initial
begin
#25 din1=1;
#400 din1=1;
#400 din1=0;
#400 din1=1;
#400 din1=0;
#400 din1=1;
#400 din1=0;
#400 din1=1;
#400 din1=1;
#400 din1=0;
#400 din1=1;
#400 din1=1;
#400 din1=1;
#400 din1=0;
#400 din1=1;
#400 din1=0;
#400 din1=0;
#400 din1=1;
#400 din1=0;
#400 din1=0;
#400 din1=0;
#400 din1=1;
#400 din1=1;
#400 din1=0;
#400 din1=0;
#400 din1=1;
#400 din1=0;
#400 din1=0;
#400 din1=0;
#400 din1=0;
#400 din1=1;
#1000 $stop;
end
endmodule
module demodulator(clk,rst,ddin,ddout); //解调input clk,rst;
input ddin;
output ddout;
reg ddout;
reg [3:0]cnt3;
reg temp;
reg [3:0]cnt4;
reg clk1;
always @(posedge clk or negedge rst)
begin
if(!rst)
cnt3<=4'b0000;
else if(!ddin)
cnt3<=cnt3+1;
else
cnt3<=4'b0000;
end
always @(posedge clk or negedge rst) begin
if(!rst)
temp<=0;
else
if(cnt3>6)
temp<=1;
else
temp<=0;
end
always @(posedge clk or negedge rst) begin
if(!rst)
begin
cnt4<=0;
clk1<=0;
end
else
if (cnt4==4'b1001)
begin
clk1<=~clk1;
cnt4<=0;
end
else
cnt4<=cnt4+1;
end
always @(posedge clk1 or negedge rst) begin
if(!rst)
ddout<=0;
else
ddout<=temp;
end
endmodule
module modulator(clk,rst,din,dout); // 调制input clk,rst;
input din;
output dout;
reg [1:0] cnt1;
reg cnt2;
reg f1;
reg f2;
always @(posedge clk or negedge rst)
begin
if (!rst)
begin
cnt1<=2'b00;
f1<=0;
end
else
if(cnt1==2'b11)
begin
cnt1<=2'b00;
f1<=~f1;
end
else
cnt1<=cnt1+1;
end
always @(posedge clk or negedge rst)
begin
if (!rst)
begin
cnt2<=0;
f2<=0;
end
else
if(cnt2==1)
begin
cnt2<=2'b00;
f2<=~f2;
end
else
cnt2<=cnt2+1;