MEMORY存储芯片MT45W1MW16PAFA-85 WT中文规格书

Table 99: Differential Input Swing Requirements for CK_t, CK_c (Continued)
Notes: ed to define a differential signal slew-rate.
2.For CK_t, CK_c use V IH(AC) and V IL(AC) of ADD/CMD and V REFCA .
3.These values are not defined; however, the differential signals (CK_t, CK_c) need to be within the respective limits, V IH(DC)max and V IL(DC)min for single-ended signals as well as the limitations for overshoot and undershoot.
Table 100: Minimum Time AC Time t DVAC for CK
Note: 1.Below V IL(AC).Single-Ended Requirements for CK Differential Signals
Each individual component of a differential signal (CK_t, CK_c) has to comply with cer-tain requirements for single-ended signals. CK_t and CK_c have to reach approximately V SEHmin /V SEL,max , which are approximately equal to the AC levels V IH(AC) and V IL(AC) for ADD/CMD signals in every half-cycle. The applicable AC levels for ADD/CMD might differ per speed-bin, and so on. For example, if a value other than 100mV is used for ADD/CMD V IH(AC) and V IL(AC) signals, then these AC levels also apply for the single-ended signals CK_t and CK_c.
While ADD/CMD signal requirements are with respect to V REFCA , the single-ended com-ponents of differential signals have a requirement with respect to V DD /2; this is nomi-nally the same. The transition of single-ended signals through the AC levels is used to measure setup time. For single-ended components of differential signals the require-ment to reach V SEL,max /V SEH,min has no bearing on timing, but adds a restriction on the common mode characteristics of these signals.
8Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics – AC and DC Differential Input Meas-urement Levels
Table 156: I DD , I PP , and I DDQ Current Limits; Die Rev. R (-40° ื T C ื 85°C) (Continued)
Notes: 1.Applicable for MR2 settings A7 = 0 and A6 = 0; manual mode with normal temperature
range of operation (-40–85°C).
2.Applicable for MR2 settings A7 = 1 and A6 = 0; manual mode with extended tempera-ture range of operation (-40–95°C).
3.Applicable for MR2 settings A7 = 0 and A6 = 1; manual mode with reduced temperature range of operation (-40–45°C).
4.I DD6E , I DD6R , I DD6A values are verified by design and characterization, and may not be subject to production test.
5.When additive latency is enabled for I DD0, current changes by approximately +1%.
6.When additive latency is enabled for I DD1, current changes by approximately +5%.
7.When additive latency is enabled for I DD2N , current changes by approximately 2%.
8.When DLL is disabled for I DD2N , current changes by approximately +19%.
9.When CAL is enabled for I DD2N , current changes by approximately -20%.
10.When gear-down is enabled for I DD2N , current changes by approximately +2%.
11.When CA parity is enabled for I DD2N , current changes by approximately +10%.
12.When additive latency is enabled for I DD3N , current changes by approximately -2%.
13.When additive latency is enabled for I DD4R , current changes by approximately +4%.
14.When read DBI is enabled for I DD4R , current changes by approximately -14%
15.When additive latency is enabled for I DD4W , current changes by approximately +6%.
16.When write DBI is enabled for I DD4W , current changes by approximately +1%.
17.When write CRC is enabled for I DD4W , current changes by approximately -5%.
8Gb: x4, x8, x16 DDR4 SDRAM Current Specifications – Limits
and the starting column address as shown in the following table. Burst length options include fixed BC4, fixed BL8, and on-the-fly (OTF), which allows BC4 or BL8 to be selec-ted coincidentally with the registration of a READ or WRITE command via A12/BC_n.
Table 8: Burst Type and Burst Order
Notes: 1.0...7 bit number is the value of CA[2:0] that causes this bit to be the first read during a
burst.
2.When setting burst length to BC4 (fixed) in MR0, the internal WRITE operation starts two clock cycles earlier than for the BL8 mode, meaning the starting point for t WR and t WTR will be pulled in by two clocks. When setting burst length to OTF in MR0, the in-ternal WRITE operation starts at the same time as a BL8 (even if BC4 was selected during column time using A12/BC4_n) meaning that if the OTF MR0 setting is used, the starting point for t WR and t WTR will not be pulled in by two clocks as described in the BC4(fixed) case.
3.T = Output driver for data and strobes are in High-Z.
V = Valid logic level (0 or 1), but respective buffer input ignores level on input pins.X = “Don’t Care.”
CAS Latency
The CAS latency (CL) setting is defined in the MR0 Register Definition table. CAS laten-cy is the delay, in clock cycles, between the internal READ command and the availability of the first bit of output data. The device does not support half-clock latencies. The
8Gb: x4, x8, x16 DDR4 SDRAM Mode Register 0。