TRF1121中文资料

FEATURESSPECIFICATIONSDESCRIPTIONLPCC−48 PACKAGE(TOP VIEW)123456789101112CP2OLD2LF2DATACLKVCCD2FRVCCD1FRBPENLF1LD113141516171819221222324CP1OLO1BPALO1TUNLO1BPBVCCLO1GNDGNDGNDBBINBBIPVCCUPCGAIN[]363534333231302928272625EXTLO2IPEXTLO2INTXONIFOPVCCIFIFONGNDGNDGAIN[4]GAIN[3]GAIN[2]GAIN[1]48474645444342414393837LO2ABPBLO2ATUNLO2ABPALO2BBPBLO2BTUNLO2BBPAGNDLO2OPLO2ONGNDVCCLO2GNDTRF1121TRF1221SLWS170A–APRIL2005–REVISED DECEMBER2005 Dual VCO/PLL Synthesizer With IF Up-ConverterThe TRF1121/TRF1221are designed to function aspart of complete2.5-GHz and3.5-GHz radio chipsets,•Low Phase Noiserespectively.In the chipset,the transmit chain •Image Reject Upconverter operates as a double up converter from an IFfrequency input(typically from a baseband modem's •Dual VCO/PLL For Double Up ConversionDAC)to an RF output frequency.The TRF1121/ ArchitectureTRF1221performs the first up conversion from IF •On-Chip VCO,Resonator and PLL Onlysignals in the range of10MHz to60MHz to a Requires Off-Chip Loop Filtersecond IF frequency in the range of300MHz to360•External S-Band VCO Option MHz.The radio chipset features sufficient linearity,phase noise,and dynamic range to work in either •5-Bit Transmit Level Control,32dB in1dBsingle carrier or multi-carrier,line-of-sight or Stepsnon-line-of-sight,standard(IEEE802.16),orproprietary systems.Due to the modular nature of thechipset,it is ideal for use in systems that employ •S-Band LO Frequency Range:transmit or receive diversity.–TRF1121:1500to2500MHz–TRF1221:1700to3600MHz•UHF LO Frequency Range:250to350MHz•Input Frequency Range:10MHz to70MHz•S-Band LO Phase Noise Typical0.5rms(100Hz to1MHz)•Output Power Range From–32dBm to0dBmin1dB Steps(500-mVpp Diff Input)•Minimum UHF LO Step Size of50kHz ForTRF1121and62.5kHz for TRF1221•Image Rejection:–50dBc,Typical(20–40MHzTx IF Input)•LO Leakage:–36dBm,Typical•3rd Order IMD:<–60dBc In Max GainThe TRF1121/TRF1221are VHF-UHF upconverterswith integrated UHF and S-band frequencysynthesizers for radio applications in the2GHz to4GHz range.The IC performs the first up-conversionand generates the local oscillator(LO)for the secondup-conversion.The device uniquely integrates animage reject mixer,IF gain blocks,5-bit gain control,and two complete phase locked loop(PLL)circuitsincluding:VCOs,resonator circuit,varactors,dividers,and phase detectors.Please be aware that an important notice concerning availability,standard warranty,and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.PRODUCTION DATA information is current as of publication date.Copyright©2005,Texas Instruments Incorporated Products conform to specifications per the terms of the TexasInstruments standard warranty.Production processing does notnecessarily include testing of all parameters.TRF1121TRF1221SLWS170A–APRIL2005–REVISED DECEMBER2005This integrated circuit can be damaged by ESD.Texas Instruments recommends that all integrated circuits be handled with appropriate precautions.Failure to observe proper handling and installation procedures can cause damage.ESD damage can range from subtle performance degradation to complete device failure.Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.The detailed block diagram and the pin-out of the ASIC are shown in Figure1and Table1.2TRF1121TRF1221SLWS170A–APRIL2005–REVISED DECEMBER2005 TERMINAL FUNCTIONSTERMINALI/O TYPE DESCRIPTION1CP2O O Analog Synthesizer2charge pump output2LD2O Digital Synthesizer2lock detect output,High is locked.3LF2O Analog Lock detect filter capacitor for LO2,0.01µF typical100kΩpull-up(1)4DATA I Digital Serial interface data input5CLK I Digital Serial interface clock input6VCCD2I Power+5V power for digital7FR I Analog18-MHz reference clock input,HCMOS input.(DC level=2.5V)8VCCD1I Power+5V power for digital9FRBP O Analog Reference frequency bypass.Internally biased to2.5V.10EN I Digital Serial interface load enable(active high)11LF1O Analog Lock detect filter capacitor for LO1,0.01µF typical100kΩ(1)12LD1O Digital Synthesizer1lock detect output,High is locked.13CP1O O Analog Synthesizer1charge pump output14LO1BPA O Analog Not connected for normal operation.DC bias nominal1.8V.Do not ground or connect toany other pin.15LO1TUN I Analog VCO synthesizer1tuning port16LO1BPB O Analog Bypass capacitor for LO10.1µF(min)DCV=1.0V17VCCLO1I Power VCC for LO118,19,20,29,GND Power Ground30,37,39,4221BBIN I Analog Baseband IF input(2kΩdiff)negative,dc-coupled,Internal voltage is4V DC22BBIP I Analog Baseband IF input(2kΩdiff)positive,dc-coupled,Internal voltage is4V DC23VCCUPC I Power+5V power Analog24GAIN[0]I Digital Gain control bit0(LSB)–Logic low induces1-dB attenuation25GAIN[1]I Digital Gain control bit1–Logic low induces2-dB attenuation26GAIN[2]I Digital Gain control bit2–Logic low induces4-dB attenuation27GAIN[3]I Digital Gain control bit3–Logic low induces8-dB attenuation28GAIN[4]I Digital Gain control bit4(MSB)–Logic low induces16-dB attenuation31IFON O Analog IF analog output(100Ωdiff)negative,dc-coupled,Internal voltage is2.1V DC32VCCIF I Power+5V power Analog33IFOP O Analog IF analog output(100Ωdiff)positive,dc-coupled,Internal voltage is2.1V DC34TXON I Digital IF amplifier enable active high35EXTLO2IN I Analog External input for LO2(differential)negative and logic level for VCO select.36EXTLO2IP I Analog External input for LO2(differential)positive and logic level for VCO select.38VCCLO2I Power VCC for LO2A and B40LO2ON O Analog LO2output(differential)Negative and positive VCC bias(+5V)for LO buffer amp.41LO2OP O Analog LO2output(differential)Positive and positive VCC bias(+5V)for LO buffer amp.43LO2BBPA O Analog Not connected for normal operation.DC bias nominal1.8V.Do not ground or connect toany other pin.44LO2BTUN I Analog LO2B Tune Port45LO2BBPB O Analog Bypass cap.for LO2B0.1µF(min)DCV=1V46LO2ABPA O Analog Not connected for normal operation.DC bias nominal1.8V.Do not ground or connect toany other pin.47LO2ATUN I Analog LO2A tune port48LO2ABPB O Analog Bypass capacitor for LO2A0.1µF(min)DCV=1VBack Back side of package has metal base that must be grounded for thermal and RF performance(1)Current leakage on the order of10µA through the capacitor or by any other means from either LF pin can cause false loss of locksignals.The two pullup resistors(R16and R17)in Figure23reduce this sensitivity.3ABSOLUTE MAXIMUM RATINGSELECTRICAL CHARACTERISTICSUPCONVERTER CHARACTERISTICSTRF1121TRF1221SLWS170A–APRIL 2005–REVISED DECEMBER 2005over operating free-air temperature range (unless otherwise noted)VALUEUNIT V CC DC supply voltage 0to 5.5V I CC DC supply current 270mA P in RF input power 20dBm T J Junction temperature 150°C P dissPower dissipation 1.5W Digital input voltage –0.3to V CC +0.3V Analog input voltageV CC V θJC Thermal resistance junction-to-ambien (1)25°C/W T stg Storage temperature –40to 105°C T op Operating temperature –40to 85°C Lead temperature,40Sec Max260°C(1)Thermal resistance is junction-to-ambient assuming thermal pad with nine thermal vias under package metal base.See the recommended PCB layout.The characteristics listed in the following tables are at V CC =5V,T A =25°C(unless otherwise noted)DC CHARACTERISTICSPARAMETERTEST CONDITIONSMIN TYPMAX UNIT V CC DC supply voltage T A =25°C4.85.2V I CC_TxON T A =25°C,TXON enabled 180Supply currentmAI CC_TxOFFT A =25°C,TXON disabled130Input signal 500mVpp,V CC =5V,25°C,IF1=26MHz,IF2=325MHz unless otherwise statedPARAMETERTEST CONDITIONSMINTYP MAXUNIT F IF1Input center frequency See Figure 326MHz F IF2Output frequency range 270400MHz V BB Input signal levelPeak-to-peak differential 5001000mV Z IF1Input IF1differential impedance See Application Note TDB2kW Measured at IF2(IF2OP,IF2ON)With 500-mVpp P outOutput power (maximum gain)differential input to IF1(BBIP,BBIN)and 0dBmGAIN[4:0]=11111Measured at IF2(IF2OP,IF2ON)With 500-mVpp Output power (minimum gain)differential input to IF1(BBIP,BBIN),–32dBm GAIN[4:0]=00000∆G max Gain flatness 300MHz <IF2<330MHz±0.3dB ∆P STEP Gain step size0.71 1.3dB OP1dB Output power a 1-dB gain compression GAIN[4:0]=1111112dBm OIP3Output third order intercept For any gain setting 24dBm IR Image rejection IF1=15to 45MHz–30dBc At GAIN[4:0]=11111decreases dB for dB as gain P LO1LO1leakage –36dBm state is changedAt max gain (GAIN[4:0]=11111),no worse then NF Input noise figure 27dB 1-dB degradation per 1dB of attenuation Z IF2Output RF impedanceDifferential100Ω4SYNTHESIZER#1(UHF-BAND PLL)CHARACTERISTICS SYNTHESIZER#2(S-BAND PLL)CHARACTERISTICSTRF1121TRF1221 SLWS170A–APRIL2005–REVISED DECEMBER2005PARAMETER TEST CONDITIONS MIN TYP MAX UNITf Ref Reference frequency See Table718MHzf VCO1Frequency TRF1121and TRF1221250350MHz £FRVCO1Free running VO1SSB phase noise at100kHz–115dBc/Hz £LD LO1Locked synthesizer1SSB phase noise at10kHz–115dBc/Hz £LD LO1Locked synthesizer1SSB phase noise at100kHz–115dBc/Hz f LD LO1Locked synthesizer1integrated RMS phase noise100Hz to1MHz0.2deg MS LO1Tuning sensitivity For V LO1TUN>2V3060MHz/VTRF1121,18-MHz reference input50∆f LO1Step Size kHzTRF1221,18-MHz reference input62.5R RS LO1Reference spur rejection–70dBcR FS LO1Fractional spurs rejection-60dBcPARAMETER TEST CONDITIONS MIN TYP MAX UNITf Ref Reference frequency See Table718MHzTRF112115002100f LO2A Output frequency,VCO#2A MHzTRF122117002450TRF112117002500f LO2B Output frequency,VCO#2B MHzTRF122124003600TRF1121For VLO1TUN>2V150350MS LO2A Tuning sensitivity,VCO#2A MHz/VTRF1221For VLO1TUN>2V200400TRF1121For VLO1TUN>2V200400MS LO2B Tuning sensitivity,VCO#2B MHz/VTRF1221For VLO1TUN>2V350550∆f LO2Step size For18-MHz ref input1MHzMeasured into a100-Ωdifferential load at theP LO2Output power level-3dBmLO1OP/N portMeasured into a100-Ωdifferential load at the£FR VCO2Free running SSB phase noise at100kHz–100dBc/HzLO1OP/N portLocked synthesizer SSB phase noise–102–97Measured into a100-Ωdifferential load at theat10kHz£LD LO2LO2OP/N port with loop filter set to400kHz dBc/Hz Locked synthesizer SSB phase noise at nominal–100–95 100kHzφLD LO2Integrated RMS phase noise Locked,100Hz to1MHz0.51DegMeasured into a100-Ωdifferential load at theR RS LO2Reference sideband suppression LO1OP/N port.PLL loop bandwidth–65–60dBc~400kHzAt1MHz offset(Loop BW~400kHz)–50–45R FS LO2Fractional spur suppression At2MHz offset(Loop BW~400kHz)–65–60dBcAll others–70–70Measured into a100-Ωdifferential load at theR H LO2Harmonics suppression–20dBcLO1OP/N portMeasured into a100-Ωdifferential load at theRL LO2Output return loss–11–16dBLO1OP/N portP extVCO Ext VCO input power–13dBm RL extVCO Ext VCO port input ret.loss Differential mode–10–15dBZ in extVCO Ext VCO port input impedance Differential mode100Ω5INPUT REFERENCE REQUIREMENTSAC TIMING,SERIAL BUS INTERFACEDIGITAL INTERFACE CHARACTERISTICSAUXILIARY AND CONTROLTRF1121TRF1221SLWS170A–APRIL 2005–REVISED DECEMBER 2005Conditions:Signal BW =6MHz nom,15dB maximum loss IF2SAW filter.See Figure 19PARAMETERTEST CONDITIONSMINTYP MAXUNIT f Ref Reference frequency 18MHz Temperature stability Customer requirements PPM V FR Ref.source input voltage (1)HCMOS Output 4 4.55VppDC fref Reference Input Symmetry Waveform Duty Cycle40%60%t FR Reference source pulse rise time 10%to 90%of maximum voltage transition14nsec f FR Reference Phase Noise at 10k Ωoffset–153–150dBc/Hz(1)Note that for source peak-to-peak voltages of less than 4V and dc-component other than 2.5-V degradation of the close-in phase noise may occur.For oscillators with no dc-component,a dc-voltage may be applied using a voltage divider (see the schematic).PARAMETERTEST CONDITIONSMIN TYPMAXUNIT CD I Clock to data invalid See Figure 710ns D V C Data valid to clock See Figure 710ns C PWH Clock pulse width high See Figure 750ns C PWL Clock pulse width low See Figure 750ns CE L Clock to enable low See Figure 710ns E L C Enable low to clock See Figure 710ns E PWHEnable pulse widthSee Figure 710nsConditions:Signal BW =6MHz nom,15dB maximum loss IF2SAW filter.See Figure 19PARAMETERTEST CONDITIONSMIN TYPMAXUNIT V I H Input high voltage 2.15V V IL Input low voltage 00.8V I IH Input high current 050µA I IL Input low current 0–50µA C I Input capacitance 3pF V OH Output logic 1voltage 0to 100-µA load2.43.6V R OH Output logic 1impedance 18k ΩV OLOutput low voltage0to –100-µA load0.4VPARAMETERTEST CONDITIONSMINTYP MAXUNIT V VCOenb External VCO enable voltage CMOS compatible Input.See Table 9V V LD1Lock detect voltage (PLL1)CMOS compatible output (active high).See Table 9V VLD2Lock Detect Voltage (PLL2)CMOS compatible output (active high).See Table 9VIF Output On High TXON IF Amp EnableIF Output OffLow EXTLO2IP High On-chip VCO2A selection Logic level applied to EXTLOIP and EXTLOIN pins toEXTLO2IN Low select either on chip VCO 2A or 2B.Pullup resistor =200ΩEXTLO2IP Low and pulldown resistor =1k Ω.On-chip VCO2B selection EXTLO2IN High EXTLO2IP Low Logic Level applied to EXTLOIP and EXTLOIN pins to On-chip VCO2selectionselect the external VCO2inputEXTLO2INLow6FREQUENCY PLAN27528529530531532533534535536537538501020304050607080IF1 (MHz)I F 2 (M H z )TRF1121TRF1221SLWS170A–APRIL 2005–REVISED DECEMBER 2005The TRF1121/TRF1221allow a variety of frequency plans.Figure 1illustrates the allowable combinations of first and second IFs.However,due to the fact that the chip features image reject mixers,significant changes in the frequency plan can result in degradation of the image rejection as shown in Figure 2.LO leakage vs LO1frequency is shown in Figure 3.In order to maintain maximum image rejection and LO suppression,a recommended frequency plan is TxIF1=26MHz,TxIF2=325MHz.Figure 1.Potential IF Combinations (TRF1121/1221)7RC1x21 IR515253545556575Input Tx IF1 (MHz)I m a g e R e j e c t i n (d B c )250260270280290300310320330340350LO1 Frequency (MHz)L O 1 L e a k a g e (d B m )TRF1121TRF1221SLWS170A–APRIL 2005–REVISED DECEMBER 2005Figure 2..Image Rejection vs IF1,Transmit ChainFigure 3.LO1Leakage at IF2Port,Maximum Gain8TRANSMIT LEVEL CONTROLRC1x21 Po, P LO , IM3 (G)−3−2−1124681012141618202224262830Gain StateG a i n D e v i a t i o n f r o m I d e a l (d B )P o u t , L O L e a k a g e (d B m ) I M D L e v e l (d B c )−40−30−20−10102030405060708090Temperature (o C)P o u t , L O l e a k a g e (d B m ), I M D L e v e l (d B c )−4−3−2−112P o u t (d B m )TRF1121TRF1221SLWS170A–APRIL 2005–REVISED DECEMBER 2005The TRF1121/TRF1221offer 32dB of gain control through a five wire parallel bus.When driven with a 500-mVpp differential baseband IF signal,the transmit level can be programmed between –32dBm and 0dBm in 1dB steps.Figure 4.Output Power,LO Leakage and IMD Level vs Gain StateFigure 5.Power Level,IMD and LO1Leakage Variation vs Temperature at Maximum Gain Setting9RC1x21 Output Power vs Input Voltage0.002.004.006.008.0010.0012.0014.00100100010000Differential Input Voltage (mVppd)O u t p u t P o w e r (d B m )INTEGRATED SYNTHESIZERSPLL ProgrammingTRF1121TRF1221SLWS170A–APRIL 2005–REVISED DECEMBER 2005Figure 4shows the output power,two-tone imtermodulation level,LO leakage and gain deviation from ideal vs gain state while Figure 5shows the upconverter gain variation vs temperature.NOTE:If left unconnected,the GAIN[0],GAIN[1],GAIN[2],GAIN[3],GAIN[4],and TXEN pins rest on logic Low.Figure 6.Output Power vs Input VoltageSynthesizer #1(UHF)and synthesizer #2(S-band)are both integrated in the TRF1121/TRF1221.These two PLLs can be programmed via a 3-wire serial bus (CLK,DATA,and EN)from the baseband processor.The timing specs are given in the AC Timing table.Synthesizer #2has a step size of 1MHz,while Synthesizer #1offers a step size of 50kHz,both assuming an 18-MHz reference frequency.Different reference frequencies yield different step sizes,many of which may be non-integer.NOTE:If left unconnected,the DATA,CLK and EN pins rest on logic High .EN is level sensitive.10CD D CFout +REFIN ƪ8 (N )3)*S *F 18ƫń[2 M](1)Fout +REFIN ń8 (N )3)*S *F18ƪ(2)TRF1221SLWS170A–APRIL 2005–REVISED DECEMBER 2005Figure 7.Serial Interface Timing DiagramData is written to the PLLs according to the format in Figure 8.MSBByte 1LSBMSBByte 2LSB MSBByte 3LSBAddressData A[7]A[6]A[5]A[4]A[3]A[2]A[1]A[0]D[15]D[14]D[13]D[12]D[11]D[10]D[9]D[8]D[7]D[6]D[5]D[4]D[3]D[2]D[1]D[0]1000000000Synth #1N divider Synth #1S counter Synth #1F counter 1000000100Synth #2N dividerSynth #2S counter Synth #2F counter 11PSall other addresses reserved for future expansionFigure 8.Serial Interface Data FormatThe first eight bits are the appropriate address for the instruction set and the remaining 16bits are the instructions.The data is 24bits long (3bytes).Byte 1is the address with A[7]being the MSB and A[0]being the LSB.Byte 2and 3program the IC with synthesizer information and PS (Polarity Select Bit)information.D[15]is the MSB and D[8]the LSB.The PS bit selects which edge of the reference is used for frequency comparison.Improved spurious and phase noise is achieved by selecting the edge with the fastest rise or fall time.If PS =1the rising edge is used as the reference.If PS =0,the falling edge is used.Figure 7needs to be sent to the TRF1121/TRF1221to fully program the Synthesizers #1and #2and the PS bit.Once the synthesizers and the PS bit are fully programmed,the clock signal should be turned off to eliminate any clock-related spurious signals.The LO1(UHF oscillator)frequency of oscillation is set by Equation 1:where M =10for TRF1121and 8for 1221The TRF1121/TRF1221contains two independent S-band VCOs and resonator circuits to provide additional frequency range from one IC,however only one VCO can be enabled at a time.These two VCOs are referred to as VCO2A and VCO2B (see the block diagram).The S-band PLL (LO2A or LO2B)frequency of oscillation is set by the following equation:where F has a range of 0to 17.Both N and S have ranges that are limited more by the LO range than by their digital count.TRF1221SLWS170A–APRIL 2005–REVISED DECEMBER 2005Both synthesizers have a fractional architecture,which allows a high comparison frequency relative to the step size.The S-band PLL operates at a reference frequency of 18MHz with a minimum phase accumulator frequency of 1MHz.The UHF PLL operates at a 9-MHz reference with a minimum phase accumulator frequency of 0.5MHz.The S-band PLL has a step size of 1MHz and the UHF PLL has a step size of 50kHz (TRF1121)or 62.5kHz (TRF1221),when using an 18-MHz reference frequency.Different reference frequencies yield different step sizes,many of which are non-integer.If a different reference frequency is chosen,the step size is linearly related to the step size for 18MHz.Step size =step size 18MHz x [REF FREQ /18MHz]In addition to the normal reference spurious signals at the comparison frequency,fractional synthesizers have fractional spurs.The fractional spurs occur at an offset from the LO signal that is dependent on the difference between the LO frequency and integer multiples of the reference frequency.They occur on both sides of the LO carrier.The spur locations can be found by the following process:divide the LO frequency by the reference frequency,take the remainder (fraction to the right of the whole number)and multiply it by the reference frequency.This frequency is the difference between the actual LO frequency and an integer-multiple of the reference frequency.Fractional spurs occur at this frequency and the reference frequency minus this frequency.The following example best explains the process:if LO2is set to 2206MHz and we are using an 18MHz reference frequency,then 2206/18is 122.55556.The difference between the LO and 122x 18MHz is:0.55556x 18MHz =10MHz The fractional spurs occur at this frequency offset (10MHz)from LO2and:18–10MHz or 8MHz offset from LO2.The fractional spurious level varies with the offset from the LO since the spurs are attenuated by the loop filter response.The larger the offset from the LO,the lower the spur level.In general,spurs at offsets greater than 3MHz or 4MHz are below -75dBc and are not a concern.The worst fractional spur levels occur when they are located at 1MHz offsets from the LO2.(Note:the fractional spurs are offset from the LO2by 1MHz when the difference between the LO2and an integer multiple of the reference frequency is 1MHz or 17MHz).Although both synthesizers have fractional spurs,for most applications the spurious signals from the UHF synthesizer can be ignored because the LO1spurs are filtered by the IF2filter and attenuated by frequency dividers that are located after the LO1generation.In some frequency plans it is possible to offset LO1and LO2to avoid worst case fractional spurs (at 1-MHz offsets)on LO2.VCO Tuning Characteristics100012501500175020002250250011.522.533.544.55Tuning Voltage (V)F r e q u e n c y (M H z )100200300400500600700M o d S e n s e (M H z /V )125015001750200022502500275011.522.533.544.55Tuning Voltage (V)F r e q u e n c y (M H z )100200300400500600700M o d S e n s e (M H z /V )TRF1221SLWS170A–APRIL 2005–REVISED DECEMBER 2005The TRF1121/TRF1221have internal VCOs with the following frequency vs tuning voltage characteristics.Figure 9.TRF1121LO2A Frequency LO2ATUN VoltageFigure 10.TRF1121LO2B Frequency vs LO2BTUN Voltage15020025030035040011.522.533.544.55Tuning Voltage (V)F r e q u e n c y (M H z )1030507090110M o d S e n s e (M H z /V )125015001750200022502500275011.522.533.544.55Tuning Voltage (V)F r e q u e n c y (M H z )100200300400500600700M o d S e n s e (M H z /V )TRF1221SLWS170A–APRIL 2005–REVISED DECEMBER 2005Figure 11.TRF1121LO1Frequency vs LO1TUN VoltageFigure 12.TRF1221LO2A Frequency vs LO2ATUN Voltage11.522.533.544.55Tuning Voltage (V)F r e q u e n c y (M H z )100200300400500600700800900M o d S e n s e (M H z /V )4001103503002502001509070503010F r e q u e n c y − M H zM o d S e n s e − M H z /VTuning Voltage − V11.522.533.544.55TRF1221SLWS170A–APRIL 2005–REVISED DECEMBER 2005Figure 13.TRF1221LO2B Frequency vs LO2BTUN VoltageFigure 14.TRF1221LO1Frequency vs LO1TUN VoltagePhaseNoiseTRF1221SLWS170A–APRIL 2005–REVISED DECEMBER 2005The TRF1121/TRF1221achieve superior phase noise performance with on-chip resonators and varactors.It is designed to meet the phase noise requirements of both single-carrier and multi-carrier systems.Due to the chip architecture,the phase noise and spurious performance of the LO1PLL is about 15dB better than the LO2PLL.The typical phase noise of the TRF1121and TRF1221S-band PLL (LO2)with the PLL locked is shown in Figure 15and Figure 16respectively.The phase noise plots of the TRF1221S-band PLL at the min and max range are shown in Figure 20and Figure 21respectively.These plots were taken at room temperature and typical voltage conditions.Figure 15.TRF1121Typical Integrated LO1(S-band)Phase Noise is 0.35rms (100Hz to 1MHz)When designing full duplex radios that employ narrow T to R spacing,one must consider impact of wide-band phase noise since it can degrade Rx sensitivity.(See Application Note TDB).Figure 17shows typical wide-band composite phase noise performance of the combination of the two integrated PLLs.At 50-MHz offset typical performance is –145dBc/Hz.TRF1221SLWS170A–APRIL 2005–REVISED DECEMBER 2005Figure 16.TRF1221Typical Integrated LO2(S-band)Phase Noise is 0.65rms (100Hz to 1MHz)Figure 17.TRF1121Typical Wide-Band Composite PLL Phase Noise ProfileTRF1221SLWS170A–APRIL 2005–REVISED DECEMBER 2005Figure 18shows reference spurs of the S-band (LO2)locked synthesizer and Figure 19shows the fractional spurs of the same LO at 2-MHz offset from the carrierFigure 18.TRF1121Reference Spurs on LO2OutputFigure 19.TRF1121Fractional Spurs on LO2(2-MHz Offset)TRF1221 SLWS170A–APRIL2005–REVISED DECEMBER2005Figure20.Phase Noise-2750MHzTRF1221SLWS170A–APRIL 2005–REVISED DECEMBER 2005Figure 21.Phase Noise -3600MHzFor systems that demand tighter phase noise performance than that offered by Texas Instruments internal VCOs,a provision exists for connection of an external VCO.Texas Instruments PLL still locks the VCO to the reference frequency and the ASIC provides an external tuning voltage that drives the VCO.APPLICATIONINFORMATIONTRF1121TRF1221SLWS170A–APRIL 2005–REVISED DECEMBER 2005A typical application schematic is shown in Figure 23,while a mechanical drawing of the package outline (LPCC Quad 7mm ×7mm,48pin)is presented in Figure 24.The recommended PCB layout mask is shown in Figure 25.PCB material recommendations are shown in ,Table 1and Figure 22.Table 1.PCB RecommendationsBoard materialFR4Board material core thickness 10mil Copper thickness (starting)1oz Prepreg thickness8mil Recommended number of layers 4Via plating thickness 0.5ozFinal plateWhite immersion tinFinal board thickness33–37milFigure 22.PCB Construction and Via Cross Section21。