24C08芯片手册
任务：24C08的使用
项目五基于I2C总线协议的存储操作与应用设计任务要求：24C08的使用1．仿真图proteus2程序原代码#include "iom16v.h" //ICC AVR环境下的ATmega16库函数定义了所有的寄存器及其位的标号#include "macros.h"#define TWI_Status_Start 0x08#define TWI_Status_ReStart 0x10#define TWI_Status_MTSlaACK 0x18#define TWI_Status_MTDataACK 0x28#define TWI_Status_MRSlaACK 0x40#define TWI_Status_MRDataNOACK 0x58#define TWI_Status_MRDataACK 0x50#define TWIAddr_24C08_Wr 0xA0 //写命令#define TWIAddr_24C08_Rd 0xA1 //读命令#define TWI_Work_Start() (TWCR=(1<<TWINT)|(1<<TWSTA)|(1<<TWEN))#define TWI_Work_Stop() (TWCR=(1<<TWINT)|(1<<TWSTO)|(1<<TWEN))#define TWI_Work_Wait() {while(!(TWCR&(1<<TWINT)));}#define TWI_Work_TestAck() (TWCR&0xF8)#define TWI_Work_SetAck() (TWCR|=(1<<TWEA))#define TWI_Work_SentNoAck() (TWCR&=~(1<<TWEA))#define TWI_Work_Twi() (TWCR=(1<<TWINT)|(1<<TWEN))#define TWI_Work_WriteByte(x) {TWDR=(x);TWCR=(1<<TWINT)|(1<<TWEN);}#define LCM_RS_1 PORTB|=(1<<0)#define LCM_RS_0 PORTB&=(~(1<<0))#define LCM_RW_1 PORTB|=(1<<1)#define LCM_RW_0 PORTB&=(~(1<<1))#define LCM_E_1 PORTB|=(1<<2)#define LCM_E_0 PORTB&=(~(1<<2))/******************************************************************************函数功能：延时1us（4M晶振，0.25微秒的指令执行周期）入口参数：无函数说明：4*0.25=1(微秒)******************************************************************************/void Delay_1_us(void){NOP();NOP();NOP();NOP();}/************************************************************************************* *函数功能：延时若干微秒入口参数：n_us************************************************************************************** */void Delay_n_us(unsigned int n_us){unsigned int cnt_i;for(cnt_i=0;cnt_i<n_us;cnt_i++){Delay_1_us();}}/************************************************************************************* *函数功能：延时1ms（4M晶振，0.25微秒的指令执行周期）入口参数：无函数说明：(3×cnt_j+2)×cnt_i=(3×33+2)×40*0.25=1010(微秒)，可以近似认为是1毫秒************************************************************************************** */void Delay_1_ms(void){unsigned char cnt_i,cnt_j;for(cnt_i=0;cnt_i<40;cnt_i++){for(cnt_j=0;cnt_j<33;cnt_j++){}}}/************************************************************************************* *函数功能：延时若干毫秒入口参数：n_ms************************************************************************************** */void Delay_n_ms(unsigned int n_ms){unsigned int cnt_i;for(cnt_i=0;cnt_i<n_ms;cnt_i++){Delay_1_ms();}}/************************************************************************************* *函数功能：读取忙标志和AC的值入口参数：无************************************************************************************** */unsigned char LCM_Re_BAC(){unsigned char status;//LCM_Dat为输入DDRA=0x00;//选择命令通道LCM_RS_0;//选择读操作LCM_RW_1;//使能线置1LCM_E_1;//等待信号线稳定Delay_n_us(1);//读入status=PINA;//使能线置0LCM_E_0;return status;}/************************************************************************************* *函数功能：写入命令入口参数：命令代码************************************************************************************** */void LCM_Wr_CMD(unsigned char cmd_dat){//判忙while(LCM_Re_BAC()>=0x80);//LCM_Dat为输出DDRA=0xFF;//选择命令通道LCM_RS_0;//选择写操作LCM_RW_0;//使能线置1LCM_E_1;//设置命令数据PORTA=cmd_dat;//等待信号线稳定Delay_n_us(1);//送命令数据LCM_E_0;}/************************************************************************************* *函数功能：写入数据入口参数：数据代码************************************************************************************** */void LCM_Wr_DAT(unsigned char dis_dat){//判忙while(LCM_Re_BAC()>=0x80);//LCM_Dat为输出DDRA=0xFF;//选择数据通道LCM_RS_1;//选择写操作LCM_RW_0;//使能线置1LCM_E_1;//设置数据数据PORTA=dis_dat;//等待信号线稳定Delay_n_us(1);//送数据数据LCM_E_0;Delay_n_us(40);}/************************************************************************************* *函数功能：初始化入口参数：无************************************************************************************** */void LCM_1602_Init(void){LCM_Wr_CMD(0x38); //显示模式设置：16×2显示，5×7点阵，8位数据接口Delay_n_ms(5); //延时5msLCM_Wr_CMD(0x38);Delay_n_ms(5);LCM_Wr_CMD(0x38);Delay_n_ms(5);LCM_Wr_CMD(0x0f); //显示模式设置：显示开，有光标，光标闪烁Delay_n_ms(5);LCM_Wr_CMD(0x06); //显示模式设置：光标右移，字符不移Delay_n_ms(5);LCM_Wr_CMD(0x01); //清屏幕指令，将以前的显示内容清除Delay_n_ms(5);}/************************************************************************************* *函数功能：读取独立式键盘键值入口参数：无************************************************************************************** */unsigned char Get_Key_Val(){unsigned char key_val;key_val=PIND;switch(key_val){case 0xfe:key_val=1;break;case 0xfd:key_val=2;break;case 0xfb:key_val=3;break;case 0xf7:key_val=4;break;case 0x7f:key_val=8;break;case 0xbf:key_val=7;break;case 0xdf:key_val=6;break;case 0xef:key_val=5;break;default:key_val=0;break;}while(PIND==0xFF);return key_val;}unsigned char TWI_Device_Write(unsigned char wdata,unsigned char address){TWI_Work_Start();TWI_Work_Wait();if(TWSR&0xf8!=TWI_Status_Start) return 1;TWI_Work_WriteByte(TWIAddr_24C08_Wr);TWI_Work_Wait();if(TWSR&0xf8!=TWI_Status_MTSlaACK) return 1;TWI_Work_WriteByte(address);TWI_Work_Wait();if( TWSR&0xf8!=TWI_Status_MTDataACK) return 1;TWI_Work_WriteByte(wdata);TWI_Work_Wait();if( TWSR&0xf8!=TWI_Status_MTDataACK) return 1;TWI_Work_Stop();Delay_n_ms(1);}unsigned char TWI_Device_Read(unsigned char address){unsigned char rtndata;TWI_Work_Start();TWI_Work_Wait();if(TWSR&0xf8!=TWI_Status_Start) return 0;TWI_Work_WriteByte(TWIAddr_24C08_Wr);TWI_Work_Wait();if(TWSR&0xf8!=TWI_Status_MTSlaACK) return 0;TWI_Work_WriteByte(address);TWI_Work_Wait();if(TWSR&0xf8!=TWI_Status_MTDataACK) return 0;TWI_Work_Start();TWI_Work_Wait();if(TWSR&0xf8!=TWI_Status_ReStart) return 0;TWI_Work_WriteByte(TWIAddr_24C08_Rd);TWI_Work_Wait();if(TWSR&0xf8!=TWI_Status_MRSlaACK) return 0;TWI_Work_Twi();TWI_Work_Wait();if(TWSR&0xf8!=TWI_Status_MRDataNOACK) return 0;rtndata=TWDR;TWI_Work_Stop();return rtndata;}/************************************************************************************* *主函数************************************************************************************** */void main(void){unsigned char data[11]={'0','1','2','3','4','5','6','7','8','9','k'};unsigned char x,keyn;unsigned char j;TWBR=64;TWSR=00;DDRB=0xFF;PORTB=0XFF;DDRA=0XFF;PORTA=0XFF;DDRD=0XFF;PORTD=0XFF;LCM_1602_Init();Delay_n_ms(10);while(1){keyn=Get_Key_Val();TWI_Device_Write(keyn,keyn);Delay_n_ms(1);x=TWI_Device_Read(keyn);LCM_Wr_CMD(0x80);LCM_Wr_DAT(data[x]);}}3.Protel图。
掉电存储模块产品使用手册
ATMEL08掉电存储模块简要说明：一、尺寸：全长30mm宽15mm高10mm二、主芯片：ATMEL24C08芯片三、工作电压：直流5V四、特点：电路简单实用，接线简单。
电路支持：ATMEL24C02\ ATMEL24C04\ ATMEL24C08\ ATMEL24C16\ ATMEL24C32.适用场合：单片机学习、电子竞赛、产品开发、毕业设计。
【标注说明】【参考原理图】【PCB尺寸图】【测试程序】#include <reg52.H>#include <stdio.h>#include <absacc.h>unsigned char code table[]={ 0xc0,0xf9,0xa4,0xb0,0x99,0x92,0x82,0xf8,0x80,0x90,0x40}; signed char sec=1; //定义计数值，每过1 秒，sec加1unsigned int tcnt; //定时中断次数unsigned char jd=0;unsigned char gd=0;bit write=0; //写24C08 的标志；sbit gewei=P2^6; //个位选通定义sbit shiwei=P2^5; //十位选通定义sbit baiwei=P2^7; //百位选通定义sbit qianwei=P2^4; //千位选通定义sbit P10=P1^0;sbit P11=P1^1;sbit P12=P1^2;sbit P13=P1^3;sbit P14=P1^4;sbit P15=P1^5;sbit P16=P1^6;sbit P17=P1^7;sbit P30=P3^0;sbit P31=P3^1;sbit P32=P3^2;sbit P35=P3^5;sbit jia=P2^0;sbit jian=P2^1;sbit res=P2^2;/////////24C08 读写驱动程序//////////////////// sbit scl=P3^3; // 24c08 SCLsbit sda=P3^4; // 24c08 SDAvoid delay1(unsigned char x){ unsigned int i;for(i=0;i<x;i++);;}void flash(){ ; ; }void x24c08_init() //24c08 初始化子程序{scl=1; flash(); sda=1; flash();}void start() //启动（I方C）总线{sda=1; flash(); scl=1; flash(); sda=0; flash(); scl=0; flash();} void stop() //停止（I方C）总线{sda=0; flash(); scl=1; flash(); sda=1; flash();}void writex(unsigned char j) //写一个字节{ unsigned char i,temp;temp=j;for (i=0;i<8;i++){temp=temp<<1; scl=0; flash(); sda=CY; flash(); scl=1; flash();} scl=0; flash(); sda=1; flash();}unsigned char readx() //读一个字节{unsigned char i,j,k=0;scl=0; flash(); sda=1;for (i=0;i<8;i++){flash(); scl=1; flash();if (sda==1) j=1;else j=0;k=(k<<1)|j;scl=0;}flash(); return(k);}void clock() //(I方C）线时钟{unsigned char i=0;scl=1; flash();while ((sda==1)&&(i<255))i++;scl=0; flash();}////////从24c02 的地址address 中读取一个字节数据/////unsigned char x24c08_read(unsigned char address){unsigned char i;start(); writex(0xa0);clock(); writex(address);clock(); start();writex(0xa1); clock();i=readx(); stop();delay1(10);return(i);}//////向24c02 的address 地址中写入一字节数据info///// void x24c08_write(unsigned char address,unsigned char info){EA=0;start(); writex(0xa0);clock(); writex(address);clock(); writex(info);clock(); stop();EA=1;delay1(50);}/////////////24C08 读写驱动程序完///////////////////// void Delay(unsigned int tc) //延时程序{while( tc != 0 ){unsigned int i;for(i=0; i<100; i++);tc--;}}void LED() //LED显示函数{qianwei=0; P0=0xc0; Delay(3); qianwei=1; baiwei=0; P0=0xc0; Delay(3); baiwei=1; shiwei=0; P0=table[sec/10]; Delay(3); shiwei=1; gewei=0; P0=table[sec%10]; Delay(3); gewei=1;}void t0(void) interrupt 1 using 0 //定时中断服务函数{TH0=(65536-50000)/256; //对TH0 TL0 赋值TL0=(65536-50000)%256; //重装计数初值tcnt++; //每过250ust tcnt 加一if(tcnt==1) //计满20次（1 秒）时{tcnt=0; //重新再计write=1; //1 秒写一次24C08}}void main(void){TMOD=0x01; //定时器工作在方式1ET0=1; EA=1;x24c08_init(); //初始化24C08sec=x24c08_read(2);//读出保存的数据赋于secTH0=(65536-50000)/256; //对TH0 TL0 赋值TL0=(65536-50000)%256; //使定时器0.05 秒中断一次TR0=1; //开始计时*/while(1){if(jia==0){Delay(8); while(!jia){LED();}; {sec++;if(sec==36){sec=0;}} } if(jian==0){ Delay(8); while(!jian){LED();};{sec--;if(sec<0){sec=35;}} }if(res==0){sec=0;}switch(sec){case 0:P1=0X81;P30=1;P31=1;P32=1;P35=1;break;case 1:P1=0X82;P30=1;P31=1;P32=1;P35=1;break;case 2:P1=0X84;P30=1;P31=1;P32=1;P35=1;break;case 3:P1=0X88;P30=1;P31=1;P32=1;P35=1;break;case 4:P1=0X90;P30=1;P31=1;P32=1;P35=1;break;case 5:P1=0XA0;P30=1;P31=1;P32=1;P35=1;break;case 6:P1=0X41;P30=1;P31=1;P32=1;P35=1;break;case 7:P1=0X42;P30=1;P31=1;P32=1;P35=1;break;case 8:P1=0X44;P30=1;P31=1;P32=1;P35=1;break;case 9:P1=0X48;P30=1;P31=1;P32=1;P35=1;break;case 10:P1=0X50;P30=1;P31=1;P32=1;P35=1;break;case 11:P1=0X60;P30=1;P31=1;P32=1;P35=1;break;case 12:P1=0XC1;P30=0;P31=1;P32=1;P35=1;break;case 13:P1=0XC2;P30=0;P31=1;P32=1;P35=1;break;case 14:P1=0XC4;P30=0;P31=1;P32=1;P35=1;break;case 15:P1=0XC8;P30=0;P31=1;P32=1;P35=1;break;case 16:P1=0XD0;P30=0;P31=1;P32=1;P35=1;break;case 17:P1=0XE0;P30=0;P31=1;P32=1;P35=1;break;case 18:P1=0XC1;P30=1;P31=0;P32=1;P35=1;break;case 19:P1=0XC2;P30=1;P31=0;P32=1;P35=1;break; case 20:P1=0XC4;P30=1;P31=0;P32=1;P35=1;break; case 21:P1=0XC8;P30=1;P31=0;P32=1;P35=1;break; case 22:P1=0XD0;P30=1;P31=0;P32=1;P35=1;break; case 23:P1=0XE0;P30=1;P31=0;P32=1;P35=1;break;case 24:P1=0XC1;P30=1;P31=1;P32=0;P35=1;break; case 25:P1=0XC2;P30=1;P31=1;P32=0;P35=1;break; case 26:P1=0XC4;P30=1;P31=1;P32=0;P35=1;break; case 27:P1=0XC8;P30=1;P31=1;P32=0;P35=1;break; case 28:P1=0XD0;P30=1;P31=1;P32=0;P35=1;break; case 29:P1=0XE0;P30=1;P31=1;P32=0;P35=1;break;case 30:P1=0XC1;P30=1;P31=1;P32=1;P35=0;break; case 31:P1=0XC2;P30=1;P31=1;P32=1;P35=0;break; case 32:P1=0XC4;P30=1;P31=1;P32=1;P35=0;break; case 33:P1=0XC8;P30=1;P31=1;P32=1;P35=0;break; case 34:P1=0XD0;P30=1;P31=1;P32=1;P35=0;break; case 35:P1=0XE0;P30=1;P31=1;P32=1;P35=0;break; default:break;}LED();if(write==1) //判断计时器是否计时一秒{write=0; //清零x24c08_write(2,sec); //在24c08 的地址2 中写入数据sec}}}【实物展示】。
I2C总线24C08(PDF档)
应答信号时序
写操作 • 写操作分为字节写和页面写两种操作，
•
在字节写模式下 主器件发送起始命令和从器件地址信息 R/W位置零 给从器件 在从器件产生 •应答信号后 主器件发送16的字节地址 主器件在收到从器件的另一个应答信号后 再发送数据到被寻址的存 储单元 再次应答 并在主器件产生停止信号后 •开始内部数据的擦写 在内部擦写过程中 从器件不再应答主器件的任何请求
I2C总线的传送格式
I2C总线的传送格式为主从式，对系统中的某一器件来说有 四种工作方式：主发送方式、从发送方式、主接收方式、从接 收方式。 只讲主发送从接收（单片机发送 24C08接收）
主器件产生开始信号以后，发送的第一个字节为控制字节。前 七位为从器件的地址片选信号。最低位为数据传送方向位（高 电平表示读从器件，低电平表示写从器件），然后发送一个选 择从器件片内地址的字节，来决定开始读写数据的起始地址。 接着再发送数据字节，可以是单字节数据，也可以是一组数据， 由主器件来决定。从器件每接收到一个字节以后，都要返回一 个应答信号（ASK=0）。主器件在应答时钟周期高电平期间释 放SDA线，转由从器件控制，从器件在这个时钟周期的高电平 期间必须拉低SDA线，并使之为稳定的低电平，作为有效的应 答信号。
K0110K0101850380055(K24C08)-规格书
Table 1: Pin Configuration
Pin Designation Type Name and Functions
A0 - A2 SDA SCL WP GND VCC NC
I
Address Inputs Serial Data Serial Clock Input Write Protect Ground Power Supply No Connect
At VCC At GND
Normal Read / Write Operations
Memory Organization
K24C02, 2K SERIAL EEPROM: Internally organized with 32 pages of 8 bytes each, the 2K requires an 8-bit data word address for random word addressing. K24C04, 4K SERIAL EEPROM: Internally organized with 32 pages of 16 bytes each, the 4K requires a 9-bit data word address for random word addressing. K24C08, 8K SERIAL EEPROM: Internally organized with 64 pages of 16 bytes each, the 8K requires a 10-bit data word address for random word addressing. K24C16, 16K SERIAL EEPROM: Internally organized with 128 pages of 16 bytes each, the 16K requires an 11-bit data word address for random word addressing.
NM24C08中文资料
Pin Names
A2 VSS SDA SCL NC VCC Device Address Input Ground Serial Data I/O Serial Clock Input No Connection Power Supply
Dual-in-Line Package (N), SO Package (M8) and TSSOP Package (MT8)
NOTE: Pins designated as "NC" are typically unbonded pins. However some of them are bonded for special testing purposes. Hence if a signal is applied to these pins, care should be taken that the voltage applied on these pins does not exceed the VCC applied to the device. This will ensure proper operation.
Connection Diagrams
Dual-in-Line Package (N), SO Package (M8) and TSSOP Package (MT8)
NC NC A2 VSS 1 2 8 7 VCC NC SCL SDA
DS500071-2
NM24C08
3 4 6 5
See Package Number N08E, M08A and MTC08
2
NM24C08/09 Rev. G
元器件交易网
NM24C08/09 – 8K-Bit Standard 2-Wire Bus Interface Serial EEPROM
K24c08
图5：写字节
第7页
K24C08
图6：写页面
图7：读当前地址
图8：自由读
第8页
K24C08
图9：连续读
电气特性
极限参数 直流供电压………………………-0.3V~+6.5V 输入/输出电压……………………GND－0.3V ~Vcc+0.3V 工作环境温度……………………-40℃ ~+85℃ 存储温度……………………………………－65℃ to +150℃ 备注 如果外加条件超过“极限额定参数”的额定值，将会对芯片造成永久性的破坏。这些仅是外加条件的极 限额定参数，本说明书中正常工作条件下的功能和性能参数并不适用于这些极限条件或其它任何超过本 说明书标明的正常工作条件外的情况。长时间牌极限条件下，将影响器件的可靠性。
页写： 8K器件能实现16字节页写。 页写操作与字节写操作的启动方式基本相同，不同的是，在时钟送入第一组数据并得到EEPROM应答后，主控 器件不是发出停止命令，而是继续发送其余十五组数据，每收到一组数据EEPROM都会返回应答信号。主控器 件必须以停止命令来结束页写操作（参见图6）。 每接收一组数据，数据地址的低四位会在内部自动递加。数据地址的高几位不会变化，保持存储器的页地址 不变，当内部产生的数据地址达到页边界时，数据地址将会翻转，接下来的数据的写入地址将被置为同一页 的最小地址。如果有超过16组数据被送入EEPROM，数据地址将回到最先写入的地址，先前写入的数据将被覆 盖。
查询K24C08供应商
K24C08
产品特点
工作电压： Vcc = +1.8V~5.5V 工作环境温度范围: -40℃~+85℃ 内部结构: K24C08, 1024 X 8 (8k Bits) 两线串行接口 输入引脚经施密特触发器滤波抑制噪声 双向数据传输协议 1 MHz (5V), 400 kHz (1.8V, 2.5V, 2.7V) 兼容 支持硬件写保护 16字节页写模式 支持分区页写 写周期内部定时（最大5mS） 高可靠性： 写次数：1，000，000次 数据保存：100年 符合RoHS要求的PDIP8、SOP8、TSSOP8封装
IS24C08中文资料
IS24C01IS24C02IS24C04IS24C08IS24C16ISSI®Copyright © 2002 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.1K-bit/2K-bit/4K-bit/8K-bit/16K-bit 2-WIRE SERIAL CMOS EEPROMAPRIL 2002DESCRIPTIONThe IS24CXX (refers to IS24C01, IS24C02, IS24C04,IS24C08, IS24C16) family is a low-cost and low voltage 2-wire Serial EEPROM. It is fabricated using ISSI’s advanced CMOS EEPROM technology and provides a low power and low voltage operation. The IS24CXX family features a write protection feature, and is available in 8-pin DIP and 8-pin SOIC packages.The IS24C01 is a 1K-bit EEPROM; IS24C02 is a 2K-bit EEPROM; IS24C04 is a 4K-bit EEPROM; IS24C08 is a 8K-bit EEPROM; IS24C16 is a 16K-bit EEPROM.The IS24C01 and IS24C02 are available in 8-pin MSOP package. The IS24C01, IS24C02, IS24C04, and IS24C08are available in 8-Pin TSSOP package.Automotive data is preliminary.FEATURES•Low Power CMOS Technology–Standby Current less than 8 µA (5.5V)–Read Current (typical) less than 1 mA (5.5V)–Write Current (typical) less than 3 mA (5.5V)•Flexible Voltage Operation–Vcc = 1.8V to 5.5V for –2 version –Vcc = 2.5V to 5.5V for –3 version •400 KHz (I 2C Protocol) Compatibility •Hardware Data Protection–Write Protect Pin •Sequential Read Feature•Filtered Inputs for Noise Suppression •8-pin PDIP and 8-pin SOIC packages •8-pin TSSOP (1K,2K, 4K & 8K only)•8-pin MSOP (1K,2K only)•Self time write cycle with auto clear 5 ms @ 2.5V •Organization:–IS24C01128x8(one block of 128 bytes)–IS24C02256x8(one block of 256 bytes)–IS24C04512x8(two blocks of 256 bytes)–IS24C081024x8(four blocks of 256 bytes)–IS24C162048x8(eight blocks of 256 bytes)•Page Write Buffer•Two-Wire Serial Interface–Bi-directional data transfer protocol •High Reliability–Endurance: 1,000,000 Cycles –Data Retention: 100 Years•Commercial, Industrial and Automotive tempera-ture ranges元器件交易网元器件交易网IS24C01IS24C02IS24C04IS24C08 IS24C16ISSI®FUNCTIONAL BLOCK DIAGRAM2Integrated Silicon Solution, Inc. — — 1-800-379-4774Rev.DIS24C01IS24C02IS24C04IS24C08 IS24C16ISSI®PIN DESCRIPTIONSA0-A2Address InputsSDA Serial Address/Data I/O SCL Serial Clock Input WP Write Protect Input Vcc Power Supply GNDGroundSCLThis input clock pin is used to synchronize the data transfer to and from the device.SDAThe SDA is a Bi-directional pin used to transfer addresses and data into and out of the device. The SDA pin is an open drain output and can be wire-Ored with other open drain or open collector outputs.The SDA bus requires a pullup resistor to Vcc.A0, A1, A2The A0, A1 and A2 are the device address inputs. The IS24C01 and IS24C02 use the A0, A1, and A2 for hardware addressing and a total of 8 devices may be used on a single bus system.PIN CONFIGURATION8-Pin DIP and SOIC8 Pin TSSOP (1K, 2K, 4K and 8K)8-Pin MSOP (1K, 2K)12348765A0A1A2GNDVCC WP SCL SDAThe IS24C04 uses A1 and A2 pins for hardwire addressing and a total of four devices may be addressed on a single bus system.The A0 pin is not used by IS24C04. This pin can be left floating or tied to GND or Vcc.The IS24C08 only use A2 input for hardwire addressing and a total of two devices may be addressed on a single bus system.The A0 and A1 pins are not used by IS24C08. They may be left floating or tied to either GND or Vcc.These pins are not used by IS24C16. A0 and A1 may be left floating or tied to either GND or Vcc. A2 should be tied to either GND or Vcc.WPWP is the Write Protect pin. On the 24C01, 24C02, IS24C04and 24C08, if the WP pin is tied to V CC the entire array becomes Write Protected (Read only). On the 24C16, if the WP pin is tied to Vcc the upper half array becomes Write Protected (Read only). When WP is tied to GND or left floating normal read/write operations are allowed to the device.元器件交易网IS24C01IS24C02IS24C04IS24C08 IS24C16ISSI®DEVICE OPERATIONThe IS24CXX family features a serial communication and supports a bi-directional 2-wire bus transmission protocol. 2-WIRE BUSThe two-wire bus is defined as a Serial Data line(SDA), and a Serial Clock Line (SCL). The protocol defines any device that sends data onto the SDA bus as a transmitter, and the receiving devices as a receiver. The bus is controlled by MASTER device which generates the SCL, controls the bus access and generates the STOP and START conditions. The IS24CXX is the SLAVE device on the bus.THE BUS PROTOCOL:--Data transfer may be initiated only when the bus is not busy--During a data transfer, the data line must remain stable whenever the clock line is high. Any changes in the data line while the clock line is high will be interpreted as a START or STOP condition.The state of the data line represents valid data when after a START condition, the data line is stable for the duration of the HIGH period of the clock signal. The data on the line must be changed during the LOW period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a START condition and terminated with a STOP condition.START CONDITIONThe START condition precedes all commands to the devices and is defined as a HIGH to LOW transition of SDA when SCL is HIGH. The IS24CXX monitors the SDA and SCL lines and will not respond until the START condition is met.STOP CONDITIONThe STOP condition is defined as a LOW to HIGH transition of SDA when SCL is HIGH. All operations must end with a STOP condition.ACKNOWLEDGEAfter a successful data transfer, each receiving device is required to generate an acknowledge. The Acknowledging device pulls down the SDA line.DEVICE ADDRESSINGThe MASTER begins a transmission by sending a START condition. The MASTER then sends the address of the particular slave devices it is requesting. The SLAVE address is 8 bytes.The four most significant bytes of the address are fixed as 1010 for the IS24CXX.For the IS24C16, the bytes(B2, B1 and B0) are used for memory page addressing (the IS24C16 is organized as eight blocks of 256 bytes).For the IS24C04 out of the next three bytes, B0 is for Memory Page Addressing (the IS24C04 is organized as two blocks of 256 bytes) and A2 and A1 bytes are used as device address bytes and must compare to its hard-wire inputs pins (A2 and A1). Up to four IS24C04's may be individually addressed by the system. The page addressing bytes for IS24Cxx should be considered the most significant bytes of the data word address which follows.For the IS24C08 out of the next three bytes, B1 and B0 are for memory page addressing (the IS24C08 is organized as four blocks of 256 bytes) and the A2 bit is used as device address bit and must compare to its hard-wired input pin (A2). Up to two IS24C08 may be individually addressed by the system. The page addressing bytes for IS24CXX should be considered the most significant bytes of the data word address which follows.For the IS24C01 and IS24C02, the A0, A1, and A2 are used as device address bytes and must compare to its hard-wired input pins (A0, A1, and A2) Up to Eight IS24C01 and/ or IS24C02's may be individually addressed by the system. The last bit of the slave address specifies whether a Read or Write operation is to be performed. When this bit is set to 1, a Read operation is selected, and when set to 0, a Write operation is selected.After the MASTER sends a START condition and the SLAVE address byte, the IS24CXX monitors the bus and responds with an Acknowledge (on the SDA line) when its address matches the transmitted slave address. The IS24CXX pulls down the SDA line during the ninth clock cycle, signaling that it received the eight bytes of data. The IS24CXX then performs a Read or Write operation depending on the state of the R/W bit.WRITE OPERATIONBYTE WRITEIn the Byte Write mode, the Master device sends the START condition and the slave address information(with the R/W set to Zero) to the Slave device. After the Slave generates an acknowledge, the Master sends the byte address that is to be written into the address pointer of the IS24CXX. After receiving another acknowledge from the Slave, the Master device transmits the data byte to be written into the address memory location. The IS24CXX acknowledges once more and the Master generates the STOP condition, at which time the device begins its internal programming cycle. While this internal cycle is in progress, the device will not respond to any request from the Master device.元器件交易网4Integrated Silicon Solution, Inc. — — 1-800-379-4774Rev.DIS24C01IS24C02IS24C04IS24C08 IS24C16ISSI®condition and the IS24CXX discontinues transmission. If 'n' is the last byte of the memory, then the data from location '0' will be transmitted. (Refer to Current Address Read Diagram.)RANDOM ADDRESS READSelective READ operations allow the Master device to select at random any memory location for a READ operation.The Master device first performs a 'dummy' write operation by sending the START condition, slave address and word address of the location it wishes to read. After the IS24CXX acknowledge the word address, the Master device resends the START condition and the slave address, this time with the R/W bit set to one. The IS24CXX then responds with its acknowledge and sends the data requested. The master device does not send an acknowledge but will generate a STOP condition. (Refer to Random Address Read Diagram.)SEQUENTIAL READSequential Reads can be initiated as either a Current Address Read or Random Address Read. After the IS24CXX sends initial byte sequence, the master device now responds with an ACKnowledge indicating it requires additional data from the IS24CXX. The IS24CXX continues to output data for each ACKnowledge received. The master device terminates the sequential READ operation by pulling SDA HIGH (no ACKnowledge) indicating the last data word to be read, followed by a STOP condition.The data output is sequential, with the data from address n followed by the data from address n+1, ... etc.The address counter increments by one automatically,allowing the entire memory contents to be serially read during sequential read operation. When the memory address boundary (127 for IS24C01; 255 for IS24C02; 511 for IS24C04; 1023 for IS24C08; 2047 for IS24C16) is reached,the address counter “rolls over” to address 0, and the IS24CXX continues to output data for each ACKnowledge received. (Refer to Sequential Read Operation Starting with a Random Address READ Diagram.)PAGE WRITEThe IS24CXX is capable of page-WRITE (8-byte for 24C01/02 and 16-byte for 24C04/08/16) operation. A page-WRITE is initiated in the same manner as a byte write, but instead of terminating the internal write cycle after the first data word is transferred, the master device can transmit up to N more bytes (N=7 for 24C01/02 and N=15 for 24C04/08/16). After the receipt of each data word, the IS24CXX responds immediately with an ACKnowledge on SDA line, and the three lower (24C01/24C02) or four lower (24C04/24C08/24C16) order data word address bits are internally incremented by one, while the higher order bits of the data word address remain constant. If the master device should transmit more than N+1 (N=7 for 24C01/02 and N=15 for 24C04/08/16) words, prior to issuing the STOP condition,the address counter will “roll over,” and the previously written data will be overwritten. Once all N+1 (N=7 for 24C01/02 and N=15 for 24C04/08/16) bytes are received and the STOP condition has been sent by the Master, the internal programming cycle begins. At this point, all received data is written to the IS24CXX in a single write cycle. All inputs are disabled until completion of the internal WRITE cycle.ACKNOWLEDGE POLLINGThe disabling of the inputs can be used to take advantage of the typical write cycle time. Once the stop condition is issued to indicate the end of the host's write operation, the IS24CXX initiates the internal write cycle. ACK polling can be initiated immediately. This involves issuing the start condition followed by the slave address for a write operation.If the IS24CXX is still busy with the write operation, no ACK will be returned. If the IS24CXX has completed the write operation, an ACK will be returned and the host can then proceed with the next read or write operation.READ OPERATIONREAD operations are initiated in the same manner as WRITE operations, except that the read/write bit of the slave address is set to “1”. There are three READ operation options: current address read, random address read and sequential read.CURRENT ADDRESS READThe IS24CXX contains an internal address counter which maintains the address of the last byte accessed, incremented by one. For example, if the previous operation is either a read or write operation addressed to the address location n,the internal address counter would increment to address location n+1. When the IS24CXX receives the Device Addressing Byte with a READ operation (read/write bit set to “1”), it will respond an ACKnowledge and transmit the 8-bit data word stored at address location n+1. The master will not acknowledge the transfer but does generate a STOP元器件交易网元器件交易网IS24C01IS24C02IS24C04IS24C08 IS24C16ISSI®TYPICAL SYSTEM BUS CONFIGURATIONSTART AND STOP CONDITIONS6Integrated Silicon Solution, Inc. — — 1-800-379-4774Rev.D元器件交易网IS24C01IS24C02IS24C04IS24C08 IS24C16ISSI®DATA VALIDITY PROTOCOL元器件交易网IS24C01IS24C02IS24C04IS24C08 IS24C16ISSI®PAGE WRITE8Integrated Silicon Solution, Inc. — — 1-800-379-4774Rev.D元器件交易网IS24C01IS24C02IS24C04IS24C08 IS24C16ISSI®SEQUENTIAL READ元器件交易网IS24C01IS24C02IS24C04IS24C08 IS24C16ISSI®ABSOLUTE MAXIMUM RATINGS(1)Symbol Parameter Value UnitV S Supply Voltage0.5 to +6.25VV P Voltage on Any Pin–0.5 to Vcc + 0.5VT BIAS Temperature Under Bias–40 to +85°CT STG Storage Temperature–65 to +150°CI OUT Output Current5mANotes:1.Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may causepermanent damage to the device. This is a stress rating only and functional operation of thedevice at these or any other conditions above those indicated in the operational sections ofthis specification is not implied. Exposure to absolute maximum rating conditions forextended periods may affect reliability.OPERATING RANGE(IS24C01-2, IS24C02-2, IS24C04-2 IS24C08-2, & IS24C16-2)Range Ambient Temperature V CCCommercial0°C to +70°C 1.8V to 5.5VIndustrial–40°C to +85°C 1.8V to 5.5VOPERATING RANGE(IS24C01-3, IS24C02-3, IS24C04-3, IS24C08-3, & IS24C16-3)Range Ambient Temperature V CCCommercial0°C to +70°C 2.5V to 5.5VIndustrial–40°C to +85°C 2.5V to 5.5VAutomotive–40°C to +125°C 2.7V to 5.5VNote: Automotive data is preliminary.OPERATING RANGE(IS24C01-5, IS24C02-5, IS24C04-5 IS24C08-5, & IS24C16-5)Range Ambient Temperature V CCAuromotive–40°C to +125°C 4.5V to 5.5VNote: Automotive data is preliminary.10Integrated Silicon Solution, Inc. — — 1-800-379-4774Rev.DDC ELECTRICAL CHARACTERISTICSSymbol Parameter Test Conditions Min.Max.Unit V OL1Output LOW Voltage V CC = 1.8V, I OL = 0.15 mA—0.2V V OL2Output LOW Voltage V CC = 2.5V, I OL = 1.0 mA—0.4V V IH Input HIGH Voltage V CC X 0.7V CC + 0.5V V IL Input LOW Voltage–1.0V CC X 0.3VI LI Input Leakage Current V IN = V CC max.—3µAI LO Output Leakage Current—3µA Notes: V IL min and V IH max are reference only and are not tested.POWER SUPPLY CHARACTERISTICSSymbol Parameter Test Conditions Min.Max.UnitI CC1Vcc Operating Current READ at 100 KHz (Vcc = 5V)— 1.0mAI CC2Vcc Operating Current WRITE at 100 KHz (Vcc = 5V)— 3.0mAI SB1Standby Current Vcc = 1.8V— 4.0µAI SB2Standby Current Vcc = 5.5V—8.0µACAPACITANCE(1,2)Symbol Parameter Conditions Max.UnitC IN Input Capacitance V IN = 0V6pFC OUT Output Capacitance V OUT = 0V8pFNotes:1.Tested initially and after any design or process changes that may affect these parameters.2.Test conditions: T A = 25°C, f = 1 MHz, Vcc = 5.0V.12Integrated Silicon Solution, Inc. — — 1-800-379-4774Rev.D AC ELECTRICAL CHARACTERISTICS (Over Operating Range)Automotive (T A = –40°C to +125°C) 2.7V-5.5V 4.5V-5.5V Symbol Parameter Test ConditionsMin.Max.Min.Max.Unit f SCL SCL Clock Frequency 01000400KHz T Noise Suppression Time (1)—100—50ns t LOW Clock LOW Period 4.7— 1.2—µs t HIGH Clock HIGH Period4—0.6—µs t BUF Bus Free Time Before New Transmission 4.7— 1.2—µs t SU:STA Start Condition Setup Time 4.7—0.6—µs t SU:STO Stop Condition Setup Time 4.7—0.6—µs t HD:STA Start Condition Hold Time 4—0.6—µs t HD:STO Stop Condition Hold Time 4—0.6—µs t SU:DAT Data In Setup Time 200—100—ns t HD:DAT Data In Hold Time 0—0—ns t DH Data Out Hold Time SCL LOW to SDA Data Out Change 100—50—ns t AA Clock to Output SCL LOW to SDA Data Out Valid0.1 4.50.10.9µs t R SCL and SDA Rise Time(1)—1000—300ns t F SCL and SDA Fall Time (1)—300—300ns t WRWrite Cycle Time—10—10msNote:1. This parameter is characterized but not 100% tested.2. Automotive data is preliminary.AC ELECTRICAL CHARACTERISTICS (Over Operating Rnage)Commercial (T A = 0°C to +70°C) Industrial (T A = –40°C to +85°C) 1.8V-5.5V 2.5V-5.5V Symbol Parameter Test ConditionsMin.Max.Min.Max.Unit f SCL SCL Clock Frequency 01000400KHz T Noise Suppression Time (1)—100—50ns t LOW Clock LOW Period 4.7— 1.2—µs t HIGH Clock HIGH Period4—0.6—µs t BUF Bus Free Time Before New Transmission (1) 4.7— 1.2—µs t SU:STA Start Condition Setup Time 4.7—0.6—µs t SU:STO Stop Condition Setup Time 4.7—0.6—µs t HD:STA Start Condition Hold Time 4—0.6—µs t HD:STO Stop Condition Hold Time 4—0.6—µs t SU:DAT Data In Setup Time 200—100—ns t HD:DAT Data In Hold Time 0—0—ns t DH Data Out Hold Time SCL LOW to SDA Data Out Change 100—50—ns t AA Clock to Output SCL LOW to SDA Data Out Valid 0.1 4.50.10.9µs t R SCL and SDA Rise Time (1)—1000—300ns t F SCL and SDA Fall Time (1)—300—300ns t WRWrite Cycle Time—10—5msNote:1. This parameter is characterized but not 100% tested.AC WAVEFORMS BUS TIMINGWRITE CYCLE TIMINGORDERING INFORMATIONCommercial Range: 0°C to +70°CVol tageFrequency Range Part Number Package100 KHz 1.8V IS24C01-2P300-mil Plastic DIPto 5.5V IS24C01-2G Small Outline (JEDEC STD)IS24C01-2S MSOPIS24C01-2Z TSSOP100 KHz 1.8V IS24C02-2P300-mil Plastic DIPto 5.5V IS24C02-2G Small Outline (JEDEC STD)IS24C02-2S MSOPIS24C02-2Z TSSOP100 KHz 1.8V IS24C04-2P300-mil Plastic DIPto 5.5V IS24C04-2G Small Outline (JEDEC STD)IS24C04-2Z TSSOP100 KHz 1.8V IS24C08-2P300-mil Plastic DIPto 5.5V IS24C08-2G Small Outline (JEDEC STD)IS24C08-2Z TSSOP100 KHz 1.8V IS24C16-2P300-mil Plastic DIPto 5.5V IS24C16-2G Small Outline (JEDEC STD)400 KHz 2.5V IS24C01-3P300-mil Plastic DIPto 5.5V IS24C01-3G Small Outline (JEDEC STD)IS24C01-3S MSOPIS24C01-3Z TSSOP400 KHz 2.5V IS24C02-3P300-mil Plastic DIPto 5.5V IS24C02-3G Small Outline (JEDEC STD)IS24C02-3S MSOPIS24C02-3Z TSSOP400 KHz 2.5V IS24C04-3P300-mil Plastic DIPto 5.5V IS24C04-3G Small Outline (JEDEC STD)IS24C04-3Z TSSOP400 KHz 2.5V IS24C08-3P300-mil Plastic DIPto 5.5V IS24C08-3G Small Outline (JEDEC STD)IS24C08-3Z TSSOP400 KHz 2.5V IS24C16-3P300-mil Plastic DIPto 5.5V IS24C16-3G Small Outline (JEDEC STD)14Integrated Silicon Solution, Inc. — — 1-800-379-4774Rev.DORDERING INFORMATIONIndustrial Range: –40°C to +85°CVoltageFrequency Range Part Number Package100 KHz 1.8V IS24C01-2PI300-mil Plastic DIPto 5.5V IS24C01-2GI Small Outline (JEDEC STD)IS24C01-2SI MSOPIS24C01-2ZI TSSOP100 KHz 1.8V IS24C02-2PI300-mil Plastic DIPto 5.5V IS24C02-2GI Small Outline (JEDEC STD)IS24C02-2SI MSOPIS24C02-2ZI TSSOP100 KHz 1.8V IS24C04-2PI300-mil Plastic DIPto 5.5V IS24C04-2GI Small Outline (JEDEC STD)IS24C04-2ZI TSSOP100 KHz 1.8V IS24C08-2PI300-mil Plastic DIPto 5.5V IS24C08-2GI Small Outline (JEDEC STD)IS24C08-2ZI TSSOP100 KHz 1.8V IS24C16-2PI300-mil Plastic DIPto 5.5V IS24C16-2GI Small Outline (JEDEC STD) 400 KHz 2.5V IS24C01-3PI300-mil Plastic DIPto 5.5V IS24C01-3GI Small Outline (JEDEC STD)IS24C01-3SI MSOPIS24C01-3ZI TSSOP400 KHz 2.5V IS24C02-3PI300-mil Plastic DIPto 5.5V IS24C02-3GI Small Outline (JEDEC STD)IS24C02-3SI MSOPIS24C02-3ZI TSSOP400 KHz 2.5V IS24C04-3PI300-mil Plastic DIPto 5.5V IS24C04-3GI Small Outline (JEDEC STD)IS24C04-3ZI TSSOP400 KHz 2.5V IS24C08-3PI300-mil Plastic DIPto 5.5V IS24C08-3GI Small Outline (JEDEC STD)IS24C08-3ZI TSSOP400 KHz 2.5V IS24C16-3PI300-mil Plastic DIPto 5.5V IS24C16-3GI Small Outline (JEDEC STD)ORDERING INFORMATIONAutomotive Range: –40°C to +125°CVoltageFrequency Range Part Number Package100 KHz 2.7V IS24C01-3PA300-mil Plastic DIPto 5.5V IS24C01-3GA Small Outline (JEDEC STD)IS24C01-3SA MSOPIS24C01-3ZA TSSOP100 KHz 2.7V IS24C02-3PA300-mil Plastic DIPto 5.5V IS24C02-3GA Small Outline (JEDEC STD)IS24C02-3SA MSOPIS24C02-3ZA TSSOP100 KHz 2.7V IS24C04-3PA300-mil Plastic DIPto 5.5V IS24C04-3GA Small Outline (JEDEC STD)IS24C04-3ZA TSSOP100 KHz 2.7V IS24C08-3PA300-mil Plastic DIPto 5.5V IS24C08-3GA Small Outline (JEDEC STD)IS24C08-3ZA TSSOP100 KHz 2.7V IS24C16-3PA300-mil Plastic DIPto 5.5V IS24C16-3GA Small Outline (JEDEC STD)400 KHz 4.5V IS24C01-5PA300-mil Plastic DIPto 5.5V IS24C01-5GA Small Outline (JEDEC STD)IS24C01-5SA MSOPIS24C01-5ZA TSSOP400 KHz 4.5V IS24C02-5PA300-mil Plastic DIPto 5.5V IS24C02-5GA Small Outline (JEDEC STD)IS24C02-5SA MSOPIS24C02-5ZA TSSOP400 KHz 4.5V IS24C04-5PA300-mil Plastic DIPto 5.5V IS24C04-5GA Small Outline (JEDEC STD)IS24C04-5ZA TSSOP400 KHz 4.5V IS24C08-5PA300-mil Plastic DIPto 5.5V IS24C08-5GA Small Outline (JEDEC STD)IS24C08-5ZA TSSOP400 KHz 4.5V IS24C16-5PA300-mil Plastic DIPto 5.5V IS24C16-5GA Small Outline (JEDEC STD)Note: Automotive data is preliminary.16Integrated Silicon Solution, Inc. — — 1-800-379-4774Rev.D。
I2C总线24C08(PDF档)
I2C总线接口 EEPROM存储器
目前，市场上I2C总线接口器件有多种，例如A/D转换器、D/A转换 器（PCF8591）、时钟芯片和存储器（24C08）等。这里以典型的I2C 总线接口的存储器为例进行介绍。 I2C总线接口EEPROM存储器是一种采用I2C总线接口的串行总线存 储器，这类存储器具有体积小、引脚少、功耗低、工作电压范围宽等 特点。目前，Atmel、MicroChip、National等公司均提供各种型号的 I2C总线接口的串行EEPROM存储器。在单片机系统中使用较多的 EEPROM存储器是24系列串行EEPROM。其具有型号多、容量大、 支持I2C总线协议、占用单片机I/O端口少，芯片扩展方便、读写简单 等优点。
读操作 读操作有三种基本操作：当前地址读、随机读和顺序读。 下图给出的是顺序读的时序图。应当注意的是，为了结束读操 作，主机必须在第9个周期间发出停止条件或者在第9个时钟周 期内保持SDA为高电平，然后发出停止条件。
I2C协议起始信号时序
起始信号用于开始I2C总线通信。其中，起始信号是在时钟线SCL为高电平 期间，数据SDA上高电平向低电平变化的下降沿信号。起始信号出现以后， 才可以进行后续的I2C总线寻址或数据传输等
I2C总线数据操作
在I2C总线上，数据是伴随着时钟脉冲，一位一位地传送的，数据位 由低到高传送，每位数据占一个时钟脉冲。I2C总线上的在时钟线 SCL高电平期间，数据线SDA的状态就表示要传送的数据，高电平为 数据1，低电平为数据0。在数据传送时，SDA上数据的改变在时钟线 为低电平时完成，而SCL为高电平时，SDA必须保持稳定，否则SDA 上的变化会被当作起始或终止信号而致使数据传输停止。
I2C总线工作原理
存储器24C08的串口读取与写入程序
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图１ １６ ２０１０ Ｖ０１．．．１０
万方数据
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方的时钟将不可能做到绝对的统一。总是会有一定差
观图。
异，主要包括中心频率的差异与时钟频率的漂移。电
子振荡器的频率虽然非常非常稳定，但是随环境气温
可以提高程序执行的效率。在连续读取模式下。
不会得到响应．包括单片机发出的标准总线起动
单片机完整读到每一字节数据后必须做出应答，
信号。具体实现方法就是使ＳＤＡ线维持高电平。
由２４Ｃ０８识别后．控制内部地址存储器自动加
使单片机得不到应答进入等待状态，直至２４Ｃ０８
１，下一地址所储存的数据就会自动移位输出。
大的功能就是起到直观显示编缉２４Ｃ０８数据
动同步。这样的做法，将把双方时钟差异限定在十个
的作用。单片机依然使用比较常见的５１系列
时钟周期之内。只要双方时钟误差保持在５％以内。
中的８９Ｓ５１。将编制好的读写程序写入内部
数据传输基本上不会出错。付出的代价是传输速率降
便好了。在电脑一方，需要一种功能全面的 串口调试软件配合，这里使用ＰＯＲＴＴＥＳＴ这 种串口调试工具。单片机与电脑之间的联机 通讯通过ＲＳ２３２串１：３完成。ＲＳ２３２接口芯片 采用ＭＡＸ３２３２，ＭＡＸ３２３２的最大数据传输率 低于１ Ｍｂｐｓ，而２４Ｃ０８的总线最高时钟频率 ４００ＫＨＺ，所以双方的传输速率还是很相称的。 这里采用ＲＳ２３２通讯方式中最简单的发送、接 收、地端三线传输的方式。
循环移位。先期发出的数据将被复写，直至收到
取到两字节数据后，内部相应地址储存的数据将
24C08
DS21081D-page 12© 1996 Microchip Technology Inc.Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. No repre-sentation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not autho-rized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. All rights reserved. All other trademarks mentioned herein are the property of their respective companies.W ORLDWIDE S ALES & S ERVICEASIA/PACIFIC China Microchip Technology Unit 406 of Shanghai Golden Bridge Bldg.2077 Yan’an Road West, Hongiao District Shanghai, Peoples Republic of China Tel: 86 21 6275 5700 Fax: 011 86 21 6275 5060 Hong Kong Microchip Technology RM 3801B, Tower Two Metroplaza 223 Hing Fong Road Kwai Fong, N.T. Hong Kong Tel: 852 2 401 1200 Fax: 852 2 401 3431India Microchip Technology No. 6, Legacy, Convent Road Bangalore 560 025 India Tel: 91 80 526 3148 Fax: 91 80 559 9840Korea Microchip Technology 168-1, Youngbo Bldg. 3 Floor Samsung-Dong, Kangnam-Ku,Seoul, Korea Tel: 82 2 554 7200 Fax: 82 2 558 5934Singapore Microchip Technology 200 Middle Road #10-03 Prime Centre Singapore 188980Tel: 65 334 8870 Fax: 65 334 8850Taiwan, R.O.C Microchip Technology 10F-1C 207Tung Hua North Road Taipei, Taiwan, ROC Tel: 886 2 717 7175 Fax: 886 2 545 0139EUROPE United Kingdom Arizona Microchip Technology Ltd.Unit 6, The Courtyard Meadow Bank, Furlong Road Bourne End, Buckinghamshire SL8 5AJ Tel: 44 1628 850303 Fax: 44 1628 850178France Arizona Microchip Technology SARL Zone Industrielle de la Bonde 2 Rue du Buisson aux Fraises 91300 Massy - France Tel: 33 1 69 53 63 20 Fax: 33 1 69 30 90 79Germany Arizona Microchip Technology GmbH Gustav-Heinemann-Ring 125D-81739 Muenchen, Germany Tel: 49 89 627 144 0 Fax: 49 89 627 144 44Italy Arizona Microchip Technology SRL Centro Direzionale Colleone Pas Taurus 1Viale Colleoni 120041 Agrate Brianza Milan Italy Tel: 39 39 6899939 Fax: 39 39 689 9883JAPAN Microchip Technology Intl. Inc.Benex S-1 6F 3-18-20, Shin Yokohama Kohoku-Ku, Yokohama Kanagawa 222 Japan Tel: 81 45 471 6166 Fax: 81 45 471 61229/3/96AMERICASCorporate OfficeMicrochip Technology Inc.2355 West Chandler Blvd.Chandler, AZ 85224-6199Tel: 602 786-7200 Fax: 602 786-7277Technical Support: 602 786-7627Web: AtlantaMicrochip Technology Inc.500 Sugar Mill Road, Suite 200BAtlanta, GA 30350Tel: 770 640-0034 Fax: 770 640-0307BostonMicrochip Technology Inc.5 Mount Royal AvenueMarlborough, MA 01752Tel: 508 480-9990 Fax: 508 480-8575ChicagoMicrochip Technology Inc.333 Pierce Road, Suite 180Itasca, IL 60143Tel: 708 285-0071 Fax: 708 285-0075DallasMicrochip Technology Inc.14651 Dallas Parkway, Suite 816Dallas, TX 75240-8809Tel: 972 991-7177 Fax: 972 991-8588DaytonMicrochip Technology Inc.Suite 150Two Prestige PlaceMiamisburg, OH 45342Tel: 513 291-1654 Fax: 513 291-9175Los AngelesMicrochip Technology Inc.18201 Von Karman, Suite 1090Irvine, CA 92612Tel: 714 263-1888 Fax: 714 263-1338New YorkMicrochip Technmgy Inc.150 Motor Parkway, Suite 416Hauppauge, NY 11788Tel: 516 273-5305 Fax: 516 273-5335San JoseMicrochip Technology Inc.2107 North First Street, Suite 590San Jose, CA 95131Tel: 408 436-7950 Fax: 408 436-7955TorontoMicrochip Technology Inc.5925 Airport Road, Suite 200Mississauga, Ontario L4V 1W1, CanadaTel: 905 405-6279Fax: 905 405-6253All rights reserved. © 1996, Microchip Technology Incorporated, USA. 9/96Printed on recycled paper.。
BR24C08中文资料
∗3
Storage temperature range
Tstg
−65~+125
°C
Operating temperature range
Topr
−40~+85
°C
Terminal voltage
−
−0.3~VCC+0.3
V
∗1 Reduced by 3.0mW for each increase in Ta of 1°C over 25°C. ∗2 Reduced by 3.5mW for each increase in Ta of 1°C over 25°C. ∗3 Reduced by 5.0mW for each increase in Ta of 1°C over 25°C.
VIL
−
−
0.3VCC
V
VOL
−
−
0.4
V
ILI
−1
−
1
µA
ILO
−1
−
1
µA
ICC
−
−
3.0
mA
andby current
ISB
−
−
3.0
µA
This product is not designed for protection against radioactive rays.
Conditions − −
tWR
−
−
10
−
−
10
ms
Noise erase valid time (SDA/SCL pins)
tI
−
− 0.05 −
− 0.1
µs
元器件交易网
TC24C08两线EEPROM存储芯片
TC24C08A The TC24C04A/08A/16A series are 4,096/8,192/16,384 bits of serial Electrical Erasable and TC24C04A/08A/16A: V page1Two-Wire Serial EEPROM4K, 8K and 16K (8-bit wide)FEATURES❑Low voltage and low power operations:CC = 1.8V to 5.5V❑ Maximum Standby current < 1µA (typically 0.02µA and 0.06µA @ 1.8V and 5.5V respectively). ❑ 16 bytes page write mode.❑ Partial page write operation allowed.❑ Internally organized: 512 x 8 (4K), 1024 x 8 (8K), 2048 x 8 (16K). ❑ Standard 2-wire bi-directional serial interface. ❑ Schmitt trigger, filtered inputs for noise protection. ❑ Self-timed Write Cycle (5ms maximum).❑ 1 MHz (5V), 400 kHz (1.8V, 2.5V, 2.7V) Compatibility. ❑ Automatic erase before write operation.❑ Write protect pin for hardware data protection.❑ High reliability: typically 1, 000,000 cycles endurance. ❑ 100 years data retention.❑ Industrial temperature range (-40o C to 85o C).❑Standard 8-lead DIP/SOP/MSOP/TSSOP/DFN and 5-lead SOT-23/TSOT-23 Pb-free packages.DESCRIPTIONProgrammable Read Only Memory, commonly known as EEPROM. They are organized as 512/1,024/2,048 words of 8 bits (1 byte) each. The devices are fabricated with proprietary advanced CMOS process for low power and low voltage applications. These devices are available in standard 8-lead DIP, 8-lead SOP, 8-lead TSSOP, 8-lead DFN, 8-lead MSOP, and 5-lead SOT-23/TSOT-23 packages. A standard 2-wire serial interface is used to address all read and write functions. Our extended V CC range (1.8V to 5.5V) devices enables wide spectrum of applications.PIN CONFIGURATIONPin Name Pin Function A2, A1, A0 Device Address Inputs SDA Serial Data Input / Open Drain Output SCL Serial Clock Input WP Write Protect NC No-ConnectTC24C08A TC24C04A/08A/16AAll these packaging types come in conventional or Pb-free certified.VCC W P SCL SDAA2A1A0G 8L DIP 8L SOP 8L TSSOP W P VCCG ND5L SOT-23SCL 8L DFN8L M SOP 5L TSO T-23ABSOLUTE MAXIMUM RATINGSIndustrial operating temperature: -40℃ to 85℃ Storage temperature:-50℃ to 125℃Input voltage on any pin relative to ground: -0.3V to V CC + 0.3V Maximum voltage: 8VESD protection on all pins: >2000V* Stresses exceed those listed under “Absolute Maximum Rating” may cause permanent damage to the device. Functional operation of the device at conditions beyond those listed in the specification is not guaranteed. Prolonged exposure to extreme conditions may affect device reliability or functionality . page1TC24C08A A0 pin as no-connect. TC24C08A has both A0 and A1 pins as no-connect. For TC24C16A, all device . TC24C04A has The TC24C04A/08A/16A devices have a WP pin to protect the whole EEPROM array from programming.PIN DESCRIPTIONS(A) SERIAL CLOCK (SCL)The rising edge of this SCL input is to latch data into the EEPROM device while the falling edge of this clock is to clock data out of the EEPROM device. (B) DEVICE / CHIP SELECT ADDRESSES (A2, A1, A0)These are the chip select input signals for the serial EEPROM devices. Typically, these signals are hardwired to either V IH or V IL . If left unconnected, they are internally recognized as V IL address pins (A0-A2) are no-connect. (C) SERIAL DATA LINE (SDA)SDA data line is a bi-directional signal for the serial devices. It is an open drain output signal and can be wired-OR with other open-drain output devices. (D) WRITE PROTECT (WP)Programming operations are allowed if WP pin is left un-connected or input to V IL . Conversely all programming functions are disabled if WP pin is connected to V IH or V CC. Read operations is not affected by the WP pin’s input level.Table A page1random word addressing to TC24C04A/08A/16A will require 9/10/11 bits data word addresses respectively.The TC24C04A/08A/16A devices have 32/64/128 pages respectively. Since each page has 16 bytes,TC24C16A(None)TC24C08A A2, A1, TC24C04A A2, A1 A0Device Chip Select/DeviceAddress Pins UsedNo-Connect Pins Max number of similardevices on the samebus4A0 2 A2, A1, A01MEMORY ORGANIZATIONDEVICE OPERATION(A) SERIAL CLOCK AND DATA TRANSITIONSThe SDA pin is typically pulled to high by an external resistor. Data is allowed to change only when Serial clock SCL is at V IL . Any SDA signal transition may interpret as either a START or STOP condition as described below. (B) START CONDITIONWith SCL V IH , a SDA transition from high to low is interpreted as a START condition. All valid commands must begin with a START condition. page1(C) STOP CONDITIONWith SCL V IH , a SDA transition from low to high is interpreted as a STOP condition. All valid read or write commands end with a STOP condition. The device goes into the STANDBY mode if it is after a read command. A STOP condition after page or byte write command will trigger the chip into the STANDBY mode after the self-timed internal programming finish. (D) ACKNOWLEDGEThe 2-wire protocol transmits address and data to and from the EEPROM in 8 bit words. The EEPROM acknowledges the data or address by outputting a "0" after receiving each word. The ACKNOWLEDGE signal occurs on the 9th serial clock after each word. (E) STANDBY MODEThe EEPROM goes into low power STANDBY mode after a fresh power up, after receiving a STOP bit in read mode, or after completing a self-time internal programming operation.Figure 1: Timing diagram for START and STOP conditionsFigure 2: Timing diagram for output ACKNOWLEDGESCLSDASTART ConditionSTOP ConditionData Data Valid TransitionSCLData inData out START ConditionACK page1TC24C04A/08A/16A are organized to have 16 bytes per TC24C16A does not use any device address bit. Only one TC24C16A device can be used on the on 2-wire ) device address bit. Only two TC24C08A devices can be wired-OR on the ) device address bits. Only four TC24C04A devices can be wired-OR on TC24C08A uses only A2 (5TC24C04A uses A2 (5DEVICE ADDRESSINGThe 2-wire serial bus protocol mandates an 8 bits device address word after a START bit condition to invoke valid read or write command. The first four most significant bits of the device address must be 1010, which is common to all serial EEPROM devices. The next three bits are device address bits. These three device address bits (5th , 6th and 7th ) are to match with the external chip select/address pin states. If a match is made, the EEPROM device outputs an ACKNOWLEDGE signal after the 8th read/write bit, otherwise the chip will go into STANDBY mode. However, matching may not be needed for some or all device address bits (5th , 6th and 7th ) as noted below. The last or 8th bit is a read/write command bit. If the 8th bit is at V IH then the chip goes into read mode. If a “0” is detected, the device enters programming mode.th ) and A1 (6th the same 2-wire bus. Their corresponding chip select address pins A2 and A1 must be hard wired and coded from 00 (b) to 11 (b). Chip select address pin A0 is not used.th same 2-wire bus. Their corresponding chip select address pin A2 must be hard-wired and coded from 0 (b) to 1 (b). Chip select address pins A1 and A0 are not used.bus. Chip Select address pins A2, A1, and A0 are not used.WRITE OPERATIONS(A) BYTE WRITEA byte write operation starts when a micro-controller sends a START bit condition, follows by a proper EEPROM device address and then a write command. If the device address bits match the chip select address, the EEPROM device will acknowledge at the 9th clock cycle. The micro-controller will then send the rest of the lower 8 bits word address. At the 18th cycle, the EEPROM will acknowledge the 8-bit address word. The micro-controller will then transmit the 8 bit data. Following an ACKNOWLDEGE signal from the EEPROM at the 27th clock cycle, the micro-controller will issue a STOP bit. After receiving the STOP bit, the EEPROM will go into a self-timed programming mode during which all external inputs will be disabled. After a programming time of T WC , the byte programming will finish and the EEPROM device will return to the STANDBY mode. (B) PAGE WRITEA page write is similar to a byte write with the exception that one to sixteen bytes can be programmed along the same page or memory row. All memory row or page.With the same write command as the byte write, the micro-controller does not issue a STOP bit after sending the 1st byte data and receiving the ACKNOWLEDGE signal from the EEPROM on the 27th clock cycle. Instead it sends out a second 8-bit data word, with the EEPROM acknowledging at the 36th cycle. This data sending and EEPROM acknowledging cycle repeats until the micro-controller sends a STOP bit after the n 9th clock cycle. After which the EEPROM device will go into a self-timed partial or full page programming mode. After the page programming completes after a time of T WC , the devices will return to the STANDBY mode. page1The least significant 4 bits of the word address (column address) increments internally by one afterreceiving each data word. The rest of the word address bits (row address) do not change internally, butpointing to a specific memory row or page to be programmed. The first page write data word can be ofany column address. Up to 16 data words can be loaded into a page. If more then 16 data words areloaded, the 17th data word will be loaded to the 1st data word column address. The 18th data word willbe loaded to the 2nd data word column address and so on. In other word, data word address (columnaddress) will “roll” over the previously loaded data.(C) ACKNOWLEDGE POLLINGACKNOWLEDGE polling may be used to poll the programming status during a self-timed internalprogramming. By issuing a valid read or write address command, the EEPROM will not acknowledge atthe 9th clock cycle if the device is still in the self-timed programming mode. However, if the programmingcompletes and the chip has returned to the STANDBY mode, the device will return a validACKNOWLEDGE signal at the 9th clock cycle.READ OPERATIONSThe read command is similar to the write command except the 8th read/write bit in address word is set to “1”.The three read operation modes are described as follows:(A) CURRENT ADDRESS READThe EEPROM internal address word counter maintains the last read or write address plus one if thepower supply to the device has not been cut off. To initiate a current address read operation, the micro-controller issues a START bit and a valid device address word with the read/write bit (8th) set to “1”. TheEEPROM will response with an ACKNOWLEDGE signal on the 9th serial clock cycle. An 8-bit data wordwill then be serially clocked out. The internal address word counter will then automatically increase byone. For current address read the micro-controller will not issue an ACKNOWLEDGE signal on the 18thclock cycle. The micro-controller issues a valid STOP bit after the 18th clock cycle to terminate the readoperation. The device then returns to STANDBY mode.(B) SEQUENTIAL READThe sequential read is very similar to current address read. The micro-controller issues a START bitand a valid device address word with read/write bit (8th) set to “1”. The EEPROM will response with anACKNOWLEDGE signal on the 9th serial clock cycle. An 8-bit data word will then be serially clocked out.Meanwhile the internally address word counter will then automatically increase by one. Unlike currentaddress read, the micro-controller sends an ACKNOWLEDGE signal on the 18th clock cycle signalingthe EEPROM device that it wants another byte of data. Upon receiving the ACKNOWLEDGE signal, theEEPROM will serially clocked out an 8-bit data word based on the incremented internal address counter.If the micro-controller needs another data, it sends out an ACKNOWLEDGE signal on the 27th clockcycle. Another 8-bit data word will then be serially clocked out. This sequential read continues as longas the micro-controller sends an ACKNOWLEDGE signal after receiving a new data word. When theinternal address counter reaches its maximum valid address, it rolls over to the beginning of the memoryarray address. Similar to current address read, the micro-controller can terminate the sequential read bynot acknowledging the last data word received, but sending a STOP bit afterwards instead.(C) RANDOM READRandom read is a two-steps process. The first step is to initialize the internal address counter with atarget read address using a “dummy write” instruction. The second step is a current address read.To initialize the internal address counter with a target read address, the micro-controller issues a STARTbit first, follows by a valid device address with the read/write bit (8th) set to “0”. The EEPROM will thenacknowledge. The micro-controller will then send the address word. Again the EEPROM willacknowledge. Instead of sending a valid written data to the EEPROM, the micro-controller performs a current address read page1TC24C08A F MDCo nf i de nt i a linstruction to read the data. Note that once a START bit is issued, the EEPROM will reset the internal programming process and continue to execute the new instruction - which is to read the current address. page1Figure 8: SCL and SDA Bus TimingAC CHARACTERISTICS1.8 V2.5-5.0 V Symbol ParameterMin Max Min Max Unit f SCL Clock frequency, SCL 400 1000 kHz t LOW Clock pulse width low 1.20.7µst HIGH Clock pulse width high0.4 0.3 µst I Noise suppression time (1) 180 120 ns t AA Clock low to data out valid 0.3 0.9 0.2 0.7 µs t BUF Time the bus must be free before a new transmission can start (1)1.3 0.5 µs t HD.STA START hold time 0.6 0.25 µs t SU.STA START set-up time 0.6 0.25 µs t HD.DAT Data in hold time 0 0 µs t SU.DAT Data in set-up time 100100nst R Input rise time (1)0.3 0.3 µs t F Input fall time (1) 300 100 nst SU.STO STOP set-up time 0.6 0.25 µs t DH Date out hold time 50 50 ns WRWrite cycle time55msEndurance(1)25o C, Page Mode, 3.3V1,000,000Write CyclesNotes: 1. This Parameter is expected by characterization but are not fully screened by test.2. AC Measurement conditions: R L (Connects to Vcc): 1.3K ΩInput Pulse Voltages: 0.3Vcc to 0.7VccInput and output timing reference Voltages: 0.5Vcc page1DC CHARACTERISTICSSymbol Parameter TestConditions MinTypicalMaxUnitsV CC124C A supplyV CC1.8 5.5 VI CC Supply read current V CC@ 5.0V SCL = 400 kHz 0.5 1.0 mA I CC Supply write current V CC@ 5.0V SCL = 400 kHz 2.0 3.0 mA I SB1 Supplycurrent V CC@ 1.8V, V IN = V CC or V SS 1.0 µA I SB2 Supplycurrent V CC@ 2.5V, V IN = V CC or V SS 1.0 µA I SB3 Supplycurrent V CC@ 5.0V, V IN = V CC or V SS0.06 1.0 µAI IL Input leakagecurrentV IN = V CC or V SS 3.0 µAI LO Output leakagecurrentV IN = V CC or V SS 3.0 µAV IL Input low level -0.6 V CC x0.3 V V IH Input high level V CC x0.7V CC+0.5 V V OL1 Outputlowlevel V CC@ 1.8V, I OL = 0.15 mA 0.2 V V OL2 Outputlowlevel V CC@ 3.0V, I OL = 2.1 mA 0.4 V page1Tape and Reel TC24C08A-USG-TTube TC24C08A-USG-B Tape and Reel TC24C08A-USR-TTube TC24C08A-USR-B Green Tube TC24C08A-UDG-B RoHS Tube TC24C08A-UDR-B Green Tape and Reel TC24C04A-UNG-TRoHS Tape and Reel TC24C04A-UNR-T Green Tape and Reel TC24C04A-UPG-T RoHS Tape and Reel TC24C04A-UPR-T Green Tape and Reel TC24C04A-ULG-T RoHS Tape and Reel TC24C04A-ULR-T Tape and Reel TC24C04A-UTG-T Tube TC24C04A-UTG-BTape and Reel TC24C04A-UTR-TTube TC24C04A-UTR-B Tape and Reel TC24C04A-UMG-TTube TC24C04A-UMG-B Tape and Reel TC24C04A-UMR-TTube TC24C04A-UMR-B Tape and Reel TC24C04A-USG-TTube TC24C04A-USG-B Tape and Reel TC24C04A-USR-TTube TC24C04A-USR-B Green Tube TC24C04A-UDG-B RoHSTube TC24C04A-UDR-BORDERING INFORMATION:Density PackageTemperatureRangeVcc HSF Packaging Ordering CodeDIP8 -40℃-85℃ 1.8V-5.5VRoHSSOP8 -40℃-85℃ 1.8V-5.5VGreen RoHSMSOP8 -40℃-85℃ 1.8V-5.5VGreenRoHSTSSOP8 -40℃-85℃ 1.8V-5.5VGreenSOT23-5 -40℃-85℃ 1.8V-5.5V TSOT23-5 -40℃-85℃ 1.8V-5.5V 4kbitsDFN8 -40℃-85℃ 1.8V-5.5V DIP8 -40℃-85℃ 1.8V-5.5VRoHS8kbitsSOP8 -40℃-85℃ 1.8V-5.5VGreenD: DIP8 S: SOP8 M: MSOP8 T: TSSOP8 L: SOT23-5 P: TSOT23-5 N: DFN8Packaging B: TubeT: Tape and Reel HSF R: RoHS G: GreenU: page1Tube TC24C16A-UTG-B Tape and Reel TC24C16A-UTG-T RoHS Tape and Reel TC24C16A-ULR-T Green Tape and Reel TC24C16A-ULG-T Tube TC24C08A-UMR-B GreenTape and Reel TC24C16A-UNG-TRoHS Tape and Reel TC24C16A-UNR-T Green Tape and Reel TC24C16A-UPG-T RoHS Tape and Reel TC24C16A-UPR-T Tape and Reel TC24C16A-UTR-TTube TC24C16A-UTR-B Tape and Reel TC24C16A-UMG-TTube TC24C16A-UMG-B Tape and Reel TC24C16A-UMR-TTube TC24C16A-UMR-B Tape and Reel TC24C16A-USG-TTube TC24C16A-USG-B Tape and Reel TC24C16A-USR-TTube TC24C16A-USR-B Green Tube TC24C16A-UDG-B RoHS Tube TC24C16A-UDR-B Green Tape and Reel TC24C08A-UNG-TRoHS Tape and Reel TC24C08A-UNR-T Green Tape and Reel TC24C08A-UPG-T RoHS Tape and Reel TC24C08A-UPR-T Green Tape and Reel TC24C08A-ULG-T RoHSTape and Reel TC24C08A-ULR-T Tape and Reel TC24C08A-UTG-T Tube TC24C08A-UTG-B Tape and Reel TC24C08A-UTR-TTube TC24C08A-UTR-B Tape and Reel TC24C08A-UMG-TTube TC24C08A-UMG-B Tape and Reel TC24C08A-UMR-TDensity PackageTemperatureRangeVcc HSF Packaging Ordering CodeRoHSMSOP8 -40℃-85℃ 1.8V-5.5VGreen RoHSTSSOP8 -40℃-85℃ 1.8V-5.5VGreen SOT23-5 -40℃-85℃ 1.8V-5.5V TSOT23-5 -40℃-85℃ 1.8V-5.5V 8kbitsDFN8 -40℃-85℃ 1.8V-5.5V DIP8 -40℃-85℃ 1.8V-5.5VRoHSSOP8 -40℃-85℃ 1.8V-5.5VGreen RoHSMSOP8 -40℃-85℃ 1.8V-5.5VGreenRoHSTSSOP8 -40℃-85℃ 1.8V-5.5VGreenSOT23-5 -40℃-85℃ 1.8V-5.5V TSOT23-5 -40℃-85℃ 1.8V-5.5V 16kbitsDFN8 -40℃-85℃ 1.8V-5.5V page1DIP8 PACKAGE OUTLINEDIMENSIONSDimensions In Millimeters Dimensions In InchesSymbolMin Max Min MaxA 3.710 4.310 0.146 0.170A1 0.510 0.020A2 3.200 3.600 0.126 0.142B 0.380 0.570 0.015 0.0221.524（BSC） 0.060（BSC）B1C 0.204 0.360 0.008 0.014D 9.000 9.400 0.354 0.370E 6.200 6.600 0.244 0.260E1 7.320 7.920 0.288 0.312(BSC) 0.100（BSC）e 2.540L 3.000 3.600 0.118 0.142E2 8.400 9.000 0.331 0.354 page1SOP8 PACKAGE OUTLINE DIMENSIONSDimensions In Millimeters Dimensions In InchesSymbolMin Max Min MaxA 1.350 1.750 0.053 0.069A1 0.100 0.250 0.004 0.010A2 1.350 1.550 0.053 0.061b 0.330 0.510 0.013 0.020c 0.170 0.250 0.006 0.010D 4.700 5.100 0.185 0.200E 3.800 4.000 0.150 0.157E1 5.800 6.200 0.228 0.244(BSC)(BSC) 0.050e 1.270L 0.400 1.270 0.016 0.050θ0° 8° 0° 8° page1MSOP8 PACKAGE OUTLINE DIMENSIONSDimensions In Millimeters Dimensions In InchesSymbolMin Max Min MaxA 0.820 1.100 0.320 0.043A1 0.020 0.150 0.001 0.006A2 0.750 0.950 0.030 0.037b 0.250 0.380 0.010 0.015c 0.090 0.230 0.004 0.009D 2.900 3.100 0.114 0.122e 0.65 (BSC) 0.026 (BSC)E 2.900 3.100 0.114 0.122E1 4.750 5.050 0.187 0.199L 0.400 0.800 0.016 0.031θ0° 6° 0° 6° page1TSSOP8 PACKAGE OUTLINEDIMENSIONSDimensions In Millimeters Dimensions In InchesSymbolMin Max Min MaxD 2.900 3.100 0.114 0.122E 4.300 4.500 0.169 0.177b 0.190 0.300 0.007 0.012c 0.090 0.200 0.004 0.008E1 6.250 6.550 0.246 0.258A 1.100 0.043A2 0.800 1.000 0.031 0.039A1 0.020 0.150 0.001 0.006e 0.65 (BSC) 0.026 (BSC)L 0.500 0.700 0.020 0.028H 0.25 (TYP) 0.01 (TYP)θ 1° 7° 1° 7° page1SOT-23-5 PACKAGE OUTLINE DIMENSIONSDimensions In Millimeters Dimensions In InchesSymbolMin Max Min MaxA 1.050 1.250 0.041 0.049A1 0.000 0.100 0.000 0.004A2 1.050 1.150 0.041 0.045b 0.300 0.500 0.012 0.020c 0.100 0.200 0.004 0.008D 2.820 3.020 0.111 0.119E 1.500 1.700 0.059 0.067E1 2.650 2.950 0.104 0.116e 0.95 (BSC) 0.037 (BSC)e1 1.800 2.000 0.071 0.079L 0.300 0.600 0.012 0.024θ 0° 8° 0° 6°TSOT-23-5 PACKAGE OUTLINE DIMENSIONSDimensions In Millimeters Dimensions In InchesSymbolMin Max Min MaxA 0.700 0.900 0.028 0.035A1 0.000 0.100 0.000 0.004A2 0.700 0.800 0.028 0.031b 0.350 0.500 0.014 0.020c 0.080 0.200 0.003 0.008D 2.820 3.020 0.111 0.119E 1.600 1.700 0.063 0.067E1 2.650 2.950 0.104 0.116e 0.95 (BSC) 0.037 (BSC)e1 1.90 (BSC) 0.075 (BSC)L 0.300 0.600 0.012 0.024θ 0° 8° 0° 8° page1DFN8 PACKAGE OUTLINE DIMENSIONSDimensions In MillimetersSymbolMin Nom Max0.75 0.80A 0.700.02 0.05A1 -0.25 0.03b 0.180.20 0.25c 0.182.00 2.10D 1.90D2 1.50REFe 0.50BSCNd 1.50BSC3.10E 2.903.00E2 1.60REF0.40 0.50L 0.300.25 0.30h 0.20 page1。
X24C08S8-2.7资料
1© Xicor, 1991 Patents PendingCharacteristics subject to change without noticeSerial E 2PROMTYPICAL FEATURES•2.7V to 5.5V Power Supply•Low Power CMOS—Active Read Current Less Than 1 mA —Active Write Current Less Than 3 mA —Standby Current Less Than 50 µA •Internally Organized 1024 x 8•2 Wire Serial Interface—Bidirectional Data Transfer Protocol •Sixteen Byte Page Write Mode—Minimizes Total Write Time Per Byte •Self Timed Write Cycle—Typical Write Cycle Time of 5 ms •High Reliability—Endurance: 100,000 Cycles —Data Retention: 100 Years•8 Pin Mini-DlP, 8 Pin SOIC and 14 Pin SOIC PackagesDESCRIPTIONThe X24C08 is a CMOS 8,192 bit serial E 2PROM,internally organized 1024 x 8. The X24C08 features a serial interface and software protocol allowing operation on a simple two wire bus.The X24C08 is fabricated with Xicor’s advanced CMOS Textured Poly Floating Gate Technology.The X24C08 utilizes Xicor’s proprietary Direct Write™cell providing a minimum endurance of 100,000 cycles and a minimum data retention of 100 years.8KX24C081024 x 8 BitFUNCTIONAL DIAGRAM3842 FHD F01(8) V CC (4) V SS (5) SDA(6) SCL (3) A 2(2) A 1(1) A 0(7) TEST 3842-1X24C082PIN DESCRIPTIONS Serial Clock (SCL)The SCL input is used to clock all data into and out of the device.Serial Data (SDA)SDA is a bidirectional pin used to transfer data into and out of the device. It is an open drain output and may be wire-ORed with any number of open drain or open collector outputs.An open drain output requires the use of a pull-up resistor. For selecting typical values, refer to the Pull-Up Resistor selection graph at the end of this data sheet.Address (A 0, A 1)A 0 and A 1 are unused by the X24C08; however, they must be tied to V SS to insure proper device operation.Address (A 2)The A 2 input is used to set the appropriate bit of the seven bit slave address. This input can be used static or actively driven. If used statically, it must be tied to V SS or V CC as appropriate. If actively driven, it must be driven to V SS or to V CC .PIN CONFIGURATIONSOICDIP/SOIC3842 FHD F03PIN NAMESSymbol Description A 0–A 2Address Inputs SDA Serial Data SCL Serial Clock TEST Hold at V SS V SS GroundV CC Supply Voltage NCNo Connect3842 PGM T01NC A 0A 1NC A 2V SS NC1234567141312111098NC V CC TEST NC SCL SDA NCX24C08V CC TEST SCL SDAA 0A 1A 2V SS12348765X24C083842 FHD F02X24C083DEVICE OPERATIONThe X24C08 supports a bidirectional bus oriented pro-tocol. The protocol defines any device that sends data onto the bus as a transmitter, and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master will always initiate data transfers, and provide the clock for both transmit and receive operations.Therefore, the X24C08 will be considered a slave in all applications.Clock and Data ConventionsData states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are re-served for indicating start and stop conditions. Refer to Figures 1 and 2.Start ConditionAll commands are preceded by the start condition,which is a HIGH to LOW transition of SDA when SCL is HIGH. The X24C08 continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met.Stop ConditionAll communications must be terminated by a stop con-dition, which is a LOW to HIGH transition of SDA when SCL is HIGH. The stop condition is also used by the X24C08 to place the device into the standby power mode after a read sequence. A stop condition can only be issued after the transmitting device has released the bus.Figure 1. Data ValiditySCLSDADATA STABLEDATA CHANGE3842 FHD F06Figure 2. Definition of Start and StopSCLSDASTART BITSTOP BIT3842 FHD F07X24C084AcknowledgeAcknowledge is a software convention used to indicate successful data transfers. The transmitting device will release the bus after transmitting eight bits. During the ninth clock cycle the receiver will pull the SDA line LOW to acknowledge that it received the eight bits of data.Refer to Figure 3.The X24C08 will respond with an acknowledge after recognition of a start condition and its slave address. If both the device and a write operation have been se-lected, the X24C08 will respond with an acknowledge after the receipt of each subsequent eight bit word.In the read mode the X24C08 will transmit eight bits of data, release the SDA line and monitor the line for an acknowledge. If an acknowledge is detected and no stop condition is generated by the master, the X24C08will continue to transmit data. If an acknowledge is not detected, the X24C08 will terminate further data trans-missions. The master must then issue a stop condition to return the X24C08 to the standby power mode and place the device into a known state.Figure 3. Acknowledge Response From ReceiverSCL FROM MASTERDATA OUTPUT FROMTRANSMITTER189DATA OUTPUT FROM RECEIVERSTARTACKNOWLEDGE3842 FHD F08X24C085The next bit addresses a particular device. A system could have up to two X24C08 devices on the bus (see Figure 10). The two addresses are defined by the state of the A2 input.The next two bits of the slave address field are an extension of the array’s address and are concatenated with the eight bits of address in the word address field,providing direct access to the whole 1024 x 8 array.DEVICE ADDRESSINGFollowing a start condition the master must output the address of the slave it is accessing. The most significant four bits of the slave address are the device type identifier (see Figure 4). For the X24C08 this is fixed as 1010[B].Figure 4. Slave AddressThe last bit of the slave address defines the operation to be performed. When set to one a read operation is selected, when set to zero a write operation is selected.Following the start condition, the X24C08 monitors the SDA bus comparing the slave address being transmit-ted with its slave address (device type and state of A 2input.) Upon a correct compare the X24C08 outputs an acknowledge on the SDA line. Depending on the state of the R/W bit, the X24C08 will execute a read or write operation.WRITE OPERATIONS Byte WriteFor a write operation, the X24C08 requires a second address field. This address field is the word address,comprised of eight bits, providing access to any one of 1024 words in the array. Upon receipt of the word address the X24C08 responds with an acknowledge,and awaits the next eight bits of data, again responding with an acknowledge. The master then terminates the transfer by generating a stop condition, at which time the X24C08 begins the internal write cycle to the nonvolatile memory. While the internal write cycle is in progress the X24C08 inputs are disabled, and the device will not respond to any requests from the master. Refer to Figure 5 for the address, acknowledge and data transfer sequence.3842 FHD F09Figure 5. Byte WriteBUS ACTIVITY:MASTERSDA LINE BUS ACTIVITY:X24C08S T A R T SLAVE ADDRESS SS T O P P A C KA C KA C KWORD ADDRESSDATA3842 FHD F101A2A1A0R/WDEVICE TYPE IDENTIFIER DEVICE ADDRESS1HIGH ORDER WORD ADDRESSX24C086Page WriteThe X24C08 is capable of a sixteen byte page write operation. It is initiated in the same manner as the byte write operation, but instead of terminating the write cycle after the first data word is transferred, the master can transmit up to fifteen more words. After the receipt of each word, the X24C08 will respond with an acknowl-edge.After the receipt of each word, the four low order address bits are internally incremented by one. The high order six bits of the word address remain constant. If the master should transmit more than sixteen words prior to gener-ating the stop condition, the address counter will “roll over” and the previously written data will be overwritten.As with the byte write operation, all inputs are disabled until completion of the internal write cycle. Refer to Figure 6 for the address, acknowledge and data transfer sequence.Acknowledge PollingThe disabling of the inputs can be used to take advan-tage of the typical 5 ms write cycle time. Once the stop condition is issued to indicate the end of the host’s write operation the X24C08 initiates the internal write cycle.ACK polling can be initiated immediately. This involves issuing the start condition followed by the slave address for a write operation. If the X24C08 is still busy with the write operation no ACK will be returned. If the X24C08has completed the write operation an ACK will be returned and the host can then proceed with the next read or write operation. Refer to Flow 1.X24C087READ OPERATIONSRead operations are initiated in the same manner as write operations with the exception that the R/W bit of the slave address is set to a one. There are three basic read operations: current address read, random read and sequential read.It should be noted that the ninth clock cycle of the read operation is not a “don’t care.” To terminate a read operation, the master must either issue a stop condition during the ninth cycle or hold SDA HIGH during the ninth clock cycle and then issue a stop condition.Current Address ReadInternally the X24C08 contains an address counter that maintains the address of the last word accessed,incremented by one. Therefore, if the last access (either a read or write) was to address n, the next read operation would access data from address n + 1. Upon receipt of the slave address with R/W set to one, the X24C08issues an acknowledge and transmits the eight bit word.The read operation is terminated by the master; by not responding with an acknowledge and by issuing a stop condition. Refer to Figure 7 for the sequence of address,acknowledge and data transfer.Random ReadRandom read operations allow the master to access any memory location in a random manner. Prior to issuing the slave address with the R/W bit set to one, the master must first perform a “dummy” write operation. The mas-ter issues the start condition, and the slave address followed by the word address it is to read. After the word address acknowledge, the master immediately reissues the start condition and the slave address with the R/W bit set to one. This will be followed by an acknowledge from the X24C08 and then by the eight bit word. The read operation is terminated by the master; by not responding with an acknowledge and by issuing a stop condition.Refer to Figure 8 for the address, acknowledge and data transfer sequence.Figure 7. Current Address Read3842 FHD F13BUS ACTIVITY:MASTERSDA LINE BUS ACTIVITY:X24C08S TAR T SLAVE ADDRESSSS T O P PA C KDATAFigure 8. Random Read3842 FHD F14BUS ACTIVITY:MASTERSDA LINE BUS ACTIVITY:X24C08S TAR T SLAVE ADDRESS SA C KS T A R T SWORD ADDRESS n A C K SLAVE ADDRESSDATA nA C KS T O P PX24C088Sequential ReadSequential reads can be initiated as either a current address read or random access read. The first word is transmitted as with the other read modes; however, the master now responds with an acknowledge, indicating it requires additional data. The X24C08 continues to out-put data for each acknowledge received. The read operation is terminated by the master; by not responding with an acknowledge and by issuing a stop condition.The data output is sequential, with the data from address n followed by the data from n + 1. The address counter for read operations increments all address bits, allowing the entire memory contents to be serially read during one operation. At the end of the address space (address 1023) the counter “rolls over” to address 0 and the X24C08 continues to output data for each acknowledge received. Refer to Figure 9 for the address, acknowl-edge and data transfer sequence.X24C089D.C. OPERATING CHARACTERISTICS (Over recommneded operating conditions, unless otherwise specified.)LimitsSymbol ParameterMin.Max.UnitsTest Conditionsl CC1V CC Supply Current (Read)1SCL = V CC x 0.1/V CC x 0.9 Levels @ 100KHz, SDA = Open,l CC2V CC Supply Current (Write)3mA All Other Inputs = GND or V CC – 0.3V I SB1(1)V CC Standby Current 150µA SCL = SDA = V CC – 0.3V, All Other Inputs = GND or V CC , V CC = 5.5V I SB2(1)V CC Standby Current 50µA SCL = SDA = V CC – 0.3V, All Other Inputs = GND or V CC , V CC = 3V I LI Input Leakage Current 10µA V IN = GND to V CC I LO Output Leakage Current 10µA V OUT = GND to V CCV lL (2)Input Low Voltage –1.0V CC x 0.3V V IH (2)Input High Voltage V CC x 0.7V CC + 0.5V V OLOutput Low Voltage0.4V I OL = 3 mA3842 PGM T02*COMMENTStresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.This is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating condi-tions for extended periods may affect device reliability.ABSOLUTE MAXIMUM RATINGS*Temperature Under Bias.................–65°C to +135°C Storage Temperature......................–65°C to +150°C Voltage on any Pin withRespect to V SS .................................–1.0V to +7V D.C. Output Current ...........................................5 mA Lead Temperature(Soldering, 10 Seconds)..............................300°C RECOMMENDED OPERATING CONDITIONSTemperature mercial 0°C 70°C Industrial –40°C +85°C Military–55°C+125°CSupply Voltage Limits X24C08 4.5V to 5.5V X24C08-3.5 3.5V to 5.5V X24C08-33V to 5.5V X24C08-2.72.7V to 5.5VCAPACITANCE T A = 25°C, F = 1.0MHZ, V CC = 5VSymbol TestMax.Units Conditions C I/O (3)Input/Output Capacitance (SDA)8pF V I/O = 0V C IN (3)Input Capacitance (A 0, A 1, A 2, SCL)6pFV IN = 0V3842 PGM T04Notes:(1)Must perform a stop command prior to measurement.(2)V IL min and V IH max. are for reference only and are not 100% tested.(3)This parameter is periodically sampled and not 100% tested.X24C0810A.C. CONDITIONS OF TEST Input Pulse Levels V CC x 0.1 to V CC x 0.9Input Rise and Fall Times10ns I/O Timing LevelsV CC x 0.53842 PGM T05A.C. CHARACTERISTICS LIMITS (Over recommended operating conditions, unless otherwise specified.)Read & Write Cycle Limits Symbol ParameterMin.Max.Units t SCL SCL Clock Frequency0100KHz t I Noise Suppression Time Constant at SCL, SDA Inputs 100ns t AA SCL Low to SDA Data Out Valid 0.3 3.5µs t BUF Time the Bus Must Be Free Before a 4.7µs New Transmission Can Start t HD:STA Start Condition Hold Time 4.0µs t LOW Clock Low Period 4.7µs t HIGH Clock High Period4.0µs t SU:STA Start Condition Setup Time 4.7µs t HD:DAT Data In Hold Time 0µs t SU:DAT Data In Setup Time250ns t R SDA and SCL Rise Time 1µs t FSDA and SCL Fall Time 300ns t SU:STO Stop Condition Setup Time 4.7µst DH Data Out Hold Time300ns3842 PGM T06POWER-UP TIMINGSymbol ParameterMax.Units t PUR (4)Power-Up to Read Operation 1ms t PUW (4)Power-Up to Write Operation5ms3842 PGM T07Note: (4)t PUR and t PUW are the delays required from the time V CC is stable until the specified operation can be initiated. These param-eters are periodically sampled and not 100% tested.WRITE CYCLE LIMITSSymbol Parameter Min.Typ.(5)Max.Units t WR (6)Write Cycle Time510ms3842 PGM T08The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. During the write cycle, the X24C08bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address.Notes:(5) Typical values are for T A = 25°C and nominal supply voltage (5V).(6) t WR is the minimum cycle time from the system perspective when polling techniques are not used. It is the maximum time thedevice requires to perform the internal write operation.SYMBOL TABLEMust be steady Will be steady May change from Low to High Will change from Low to High May change from High to Low Will change from High to Low Don’t Care:Changes Allowed Changing:State Not Known N/ACenter Line is High ImpedanceOUTPUTS INPUTS WAVEFORMGuidelines for Calculating Typical Values of BusNOTESPACKAGING INFORMATION8-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE SNOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESIS IN MILLIMETERS)3926 FHD F223926 FHD F01TYP NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)MAX.PACKAGING INFORMATION8-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE PNOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)PACKAGING INFORMATIONPIN 1 INDEX(4X) 73926 FHD F10NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)14-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE SNOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)LIMITED WARRANTYDevices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice.Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are implied.U.S. PATENTSXicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475;4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,883, 976. Foreign patents and additional patents pending.LIFE RELATED POLICYIn situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurence.Xicor's products are not authorized for use in critical components in life support devices or systems.1.Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.2.A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.DeviceORDERING INFORMATIONV CC LimitsBlank = 4.5V to 5.5V 3.5 = 3.5V to 5.5V 3 = 3.0V to 5.5V 2.7 = 2.7V to 5.5VTemperature RangeBlank = Commercial = 0°C to +70°C I = Industrial = –40°C to +85°C M = Military = –55°C to +125°C PackageP = 8-Lead Plastic DIP S8 = 8-Lead SOIC S14 = 14-Lead SOICPart Mark ConventionX24C08 P T-VX24C08 XXP = 8-Lead Plastic DIP S8 = 8-Lead SOIC S = 14-Lead SOICBlank = 4.5V to 5.5V, 0°C to +70°C I = 4.5V to 5.5V, –40°C to +85°C B = 3.5V to 5.5V, 0°C to +70°C C = 3.5V to 5.5V, –40°C to +85°C D = 3.0V to 5.5V, 0°C to +70°C E = 3.0V to 5.5V, –40°C to +85°C F = 2.7V to 5.5V, 0°C to +70°C G = 2.7V to 5.5V, –40°C to +85°C。
M24C08-LDW3T资料
1/25October 2005M24C16, M24C08M24C04, M24C02, M24C0116Kbit, 8Kbit, 4Kbit, 2Kbit and 1Kbit Serial I²C Bus EEPROMFEATURES SUMMARY■Two-Wire I²C Serial Interface Supports 400kHz Protocol ■Single Supply Voltage:– 2.5 to 5.5V for M24Cxx-W – 1.8 to 5.5V for M24Cxx-R ■Write Control Input■BYTE and PAGE WRITE (up to 16 Bytes)■RANDOM and SEQUENTIAL READ Modes ■Self-Timed Programming Cycle ■Automatic Address Incrementing ■Enhanced ESD/Latch-Up Protection ■More than 1 Million Erase/Write Cycles ■More than 40-Year Data Retention ■Packages–ECOPACK® (RoHS compliant)Table 1. Product ListReference Part NumberM24C16M24C16-W M24C16-R M24C08M24C08-W M24C08-R M24C04M24C04-W M24C04-R M24C02M24C02-W M24C02-R M24C01M24C01-W M24C01-RM24C16, M24C08, M24C04, M24C02, M24C01TABLE OF CONTENTSFEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Device internal reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3SIGNAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Serial Clock (SCL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Serial Data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Chip Enable (E0, E1, E2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Write Control (WC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4DEVICE OPERATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6Start Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Stop Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Acknowledge Bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Data Input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Memory Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Write Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Byte Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Minimizing System Delays by Polling On ACK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Random Address Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Current Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Sequential Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Acknowledge in Read Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11INITIAL DELIVERY STATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .242/253/25M24C16, M24C08, M24C04, M24C02, M24C01SUMMARY DESCRIPTIONThese I²C-compatible electrically erasable pro-grammable memory (EEPROM) devices are orga-nized as 2048/1024/512/256/128x 8 (M24C16,M24C08, M24C04, M24C02 and M24C01).In order to meet environmental requirements, ST offers these devices in ECOPACK® packages.ECOPACK® packages are Lead-free and RoHS compliant.ECOPACK is an ST trademark. ECOPACK speci-fications are available at: .I²C uses a two-wire serial interface, comprising a bi-directional data line and a clock line. The devic-es carry a built-in 4-bit Device Type Identifier code (1010) in accordance with the I²C bus definition.The device behaves as a slave in the I²C protocol,with all memory operations synchronized by the serial clock. Read and Write operations are initiat-ed by a Start condition, generated by the bus mas-ter. The Start condition is followed by a Device scribed in Table 3.), terminated by an acknowl-edge bit.When writing data to the memory, the device in-serts an acknowledge bit during the 9th bit time,following the bus master’s 8-bit transmission.When data is read by the bus master, the bus master acknowledges the receipt of the data byte in the same way. Data transfers are terminated by a Stop condition after an Ack for Write, and after a NoAck for Read.Table 2. Signal NamesDevice internal resetIn order to prevent inadvertent Write operations during Power-up, a Power On Reset (POR) circuit is included. At Power-up (continuous rise of V CC ),the device will not respond to any instructions until the V CC has reached the Power On Reset threshold voltage (this threshold is lower than the V CC min. operating voltage defined in DC and AC PARAMETERS ). When V CC has passed over the POR threshold, the device is reset and is in Standby Power mode. At Power-down (continuous decay of V CC ), as soon as V CC drops from the normal operating voltage to below the Power On Reset threshold voltage, the device stops responding to any instruction sent to it.Prior to selecting and issuing instructions to the memory, a valid and stable V CC voltage must be applied. This voltage must remain stable and valid until the end of the transmission of the instruction and, for a Write instruction, until the completion of the internal write cycle (t W ).Note: 1.NC = Not Connected2.See PACKAGE MECHANICAL section for package dimensions, and how to identify pin-1.E0, E1, E2Chip Enable SDA Serial Data SCL Serial Clock WCWrite Control V CC Supply Voltage V SSGroundM24C16, M24C08, M24C04, M24C02, M24C014/25SIGNAL DESCRIPTIONSerial Clock (SCL).This input signal is used to strobe all data in and out of the device. In applica-tions where this signal is used by slave devices to synchronize the bus to a slower clock, the bus master must have an open drain output, and a pull-up resistor can be connected from Serial Clock (SCL) to V CC . (Figure 5. indicates how the value of the pull-up resistor can be calculated). In most applications, though, this method of synchro-nization is not employed, and so the pull-up resis-tor is not necessary, provided that the bus master has a push-pull (rather than open drain) output.Serial Data (SDA).This bi-directional signal is used to transfer data in or out of the device. It is an open drain output that may be wire-OR’ed with other open drain or open collector signals on the bus. A pull up resistor must be connected from Se-rial Data (SDA) to V CC . (Figure 5. indicates how the value of the pull-up resistor can be calculated).Chip Enable (E0, E1, E2).These input signals are used to set the value that is to be looked for on the three least significant bits (b3, b2, b1) of the 7-bit Device Select Code. These inputs must be tied to V CC or V SS , to establish the Device Select Code as shown in Figure 4.for protecting the entire contents of the memory from inadvertent write operations. Write opera-tions are disabled to the entire memory array when nected, the signal is internally read as V IL , and Write operations are allowed.Select and Address bytes are acknowledged,Data bytes are not acknowledged.M24C16, M24C08, M24C04, M24C02, M24C01Table 3. Device Select CodeDevice Type Identifier1Chip Enable2,3RWb7b6b5b4b3b2b1b0M24C01 Select Code1010E2E1E0RWM24C02 Select Code1010E2E1E0RWM24C04 Select Code1010E2E1A8RWM24C08 Select Code1010E2A9A8RWM24C16 Select Code1010A10A9A8RW Note: 1.The most significant bit, b7, is sent first.2.E0, E1 and E2 are compared against the respective external pins on the memory device.3.A10, A9 and A8 represent most significant bits of the address.5/25M24C16, M24C08, M24C04, M24C02, M24C016/25DEVICE OPERATIONThe device supports the I²C protocol. This is sum-marized in Figure 6.. Any device that sends data on to the bus is defined to be a transmitter, and any device that reads the data to be a receiver.The device that controls the data transfer is known as the bus master, and the other as the slave de-vice. A data transfer can only be initiated by the bus master, which will also provide the serial clock for synchronization. The M24Cxx device is always a slave in all communication.Start ConditionStart is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in the High state. A Start condition must precede any data transfer command. The device continuously monitors (except during a Write cycle) Serial Data (SDA) and Serial Clock (SCL) for a Start condition,and will not respond unless one is given.Stop ConditionStop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable and driv-en High. A Stop condition terminates communica-tion between the device and the bus master. A Read command that is followed by NoAck can be followed by a Stop condition to force the device into the Stand-by mode. A Stop condition at the end of a Write command triggers the internal Write cycle.Acknowledge Bit (ACK)The acknowledge bit is used to indicate a success-ful byte transfer. The bus transmitter, whether it be bus master or slave device, releases Serial Data (SDA) after sending eight bits of data. During the 9th clock pulse period, the receiver pulls Serial Data (SDA) Low to acknowledge the receipt of the eight data bits.Data InputDuring data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock (SCL).For correct device operation, Serial Data (SDA)must be stable during the rising edge of Serial Clock (SCL), and the Serial Data (SDA) signal must change only when Serial Clock (SCL) is driv-en Low.Memory AddressingTo start communication between the bus master and the slave device, the bus master must initiate a Start condition. Following this, the bus master sends the Device Select Code, shown in Table 3.(on Serial Data (SDA), most significant bit first).The Device Select Code consists of a 4-bit Device Type Identifier, and a 3-bit Chip Enable “Address”(E2, E1, E0). To address the memory array, the 4-bit Device Type Identifier is 1010b.Each device is given a unique 3-bit code on the Chip Enable (E0, E1, E2) inputs. When the Device Select Code is received, the device only responds if the Chip Enable Address is the same as the val-ue on the Chip Enable (E0, E1, E2) inputs. How-ever, those devices with larger memory capacities (the M24C16, M24C08 and M24C04) need more address bits. E0 is not available for use on devices that need to use address line A8; E1 is not avail-able for devices that need to use address line A9,and E2 is not available for devices that need to use address line A10 (see Figure 3. and Table 3. for details). Using the E0, E1 and E2 inputs, up to eight M24C02 (or M24C01), four M24C04, two M24C08 or one M24C16 devices can be connect-ed to one I²C bus. In each case, and in the hybrid cases, this gives a total memory capacity of 16Kbits, 2KBytes (except where M24C01 devic-es are used).The 8th set to 1 for Read and 0 for Write operations.If a match occurs on the Device Select code, the corresponding device gives an acknowledgment on Serial Data (SDA) during the 9th bit time. If the device does not match the Device Select code, it deselects itself from the bus, and goes into Stand-by mode.Table 4. Operating ModesNote: 1.X = V IH or V IL .ModeRW bit WC 1Bytes Initial SequenceCurrent Address Read 1X 1START , Device Select, RW = 1Random Address Read 0X 1START , Device Select, RW = 0, Address 1X reST ART, Device Select, RW = 1Sequential Read 1X ≥ 1Similar to Current or Random Address Read Byte Write 0V IL 1START , Device Select, RW = 0Page WriteV IL≤ 16START , Device Select, RW = 0M24C16, M24C08, M24C04, M24C02, M24C01Figure 7. Write Mode Sequences with WC=1 (data write inhibited)Following a Start condition the bus master sends a Device Select Code with the Read/Write bit (RW) reset to 0. The device acknowledges this, as shown in Figure 8., and waits for an address byte. The device responds to the address byte with an acknowledge bit, and then waits for the data byte. When the bus master generates a Stop condition immediately after the Ack bit (in the “10th bit” time slot), either at the end of a Byte Write or a Page Write, the internal Write cycle is triggered. A Stop condition at any other time slot does not trigger the internal Write cycle.During the internal Write cycle, Serial Data (SDA) and Serial Clock (SCL) are ignored, and the de-vice does not respond to any requests.Byte WriteAfter the Device Select code and the address byte, the bus master sends one data byte. If the ad-dressed location is Write-protected, by Write Con-trol (WC) being driven High (during the period from byte), the device replies to the data byte with NoAck, as shown in Figure 7., and the location is not modified. If, instead, the addressed location is not Write-protected, the device replies with Ack. The bus master terminates the transfer by gener-ating a Stop condition, as shown in Figure 8.. Page WriteThe Page Write mode allows up to 16 bytes to be written in a single Write cycle, provided that they are all located in the same page in the memory: that is, the most significant memory address bits are the same. If more bytes are sent than will fit up to the end of the page, a condition known as ‘roll-over’ occurs. This should be avoided, as data starts to become overwritten in an implementation dependent way.The bus master sends from 1 to 16 bytes of data, each of which is acknowledged by the device if Write Control (WC) is Low. If the addressed loca-ing driven High (during the period from the Start7/25M24C16, M24C08, M24C04, M24C02, M24C018/25condition until the end of the address byte), the de-vice replies to the data bytes with NoAck, as shown in Figure 7., and the locations are not mod-ified. After each byte is transferred, the internalbyte address counter (the 4 least significant ad-dress bits only) is incremented. The transfer is ter-minated by the bus master generating a Stop condition.M24C16, M24C08, M24C04, M24C02, M24C01During the internal Write cycle, the device discon-nects itself from the bus, and writes a copy of the data from its internal latches to the memory cells. The maximum Write time (t w) is shown in Table 13. and Table 14., but the typical time is shorter. To make use of this, a polling sequence can be used by the bus master.The sequence, as shown in Figure 9., is:–Step 1: the bus master issues a Start condition followed by a Device Select Code (the firstbyte of the new instruction).–Step 2: if the device is busy with the internal Write cycle, no Ack will be returned and thebus master goes back to Step 1. If the device has terminated the internal Write cycle, itresponds with an Ack, indicating that thedevice is ready to receive the second part of the instruction (the first byte of this instruction having been sent during Step 1).9/25M24C16, M24C08, M24C04, M24C02, M24C0110/25Read OperationsRead operations are performed independently of The device has an internal address counter which is incremented each time a byte is read.Random Address ReadA dummy Write is first performed to load the ad-dress into this address counter (as shown in Fig-ure 10.) but without sending a Stop condition.Then, the bus master sends another Start condi-tion, and repeats the Device Select Code, with the Read/Write bit (RW) set to 1. The device acknowl-edges this, and outputs the contents of the ad-dressed byte. The bus master must not acknowledge the byte, and terminates the transfer with a Stop condition.Current Address ReadFor the Current Address Read operation, following a Start condition, the bus master only sends a De-to 1. The device acknowledges this, and outputs the byte addressed by the internal address counter. The counter is then incremented. The bus master terminates the transfer with a Stop condi-tion, as shown in Figure 10., without acknowledg-ing the byte.Sequential ReadThis operation can be used after a Current Ad-dress Read or a Random Address Read. The bus master does acknowledge the data byte output, and sends additional clock pulses so that the de-vice continues to output the next byte in sequence. To terminate the stream of bytes, the bus master must not acknowledge the last byte, and must generate a Stop condition, as shown in Figure 10.. The output data comes from consecutive address-es, with the internal address counter automatically incremented after each byte output. After the last memory address, the address counter ‘rolls-over’, and the device continues to output data from memory address 00h.Acknowledge in Read ModeFor all Read commands, the device waits, aftereach byte read, for an acknowledgment during the 9th bit time. If the bus master does not drive Serial Data (SDA) Low during this time, the device termi-nates the data transfer and switches to its Stand-by mode.INITIAL DELIVERY STATEThe device is delivered with all bits in the memory array set to 1 (each byte contains FFh).11/2512/25MAXIMUM RATINGStressing the device outside the ratings listed in Table 5. may cause permanent damage to the de-vice. These are stress ratings only, and operation of the device at these, or any other conditions out-side those indicated in the Operating sections of this specification, is not implied. Exposure to Ab-solute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.Table 5. Absolute Maximum RatingsNote: pliant with JEDEC Std J-STD-020C (for small body, Sn-Pb or Pb assembly), the ST ECOPACK ® 7191395 specification, andthe European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU2.AEC-Q100-002 (compliant with JEDEC Std JESD22-A114A, C1=100pF, R1=1500Ω, R2=500Ω)Symbol ParameterMin.Max.Unit T A Ambient Operating Temperature –40125°C T STG Storage Temperature–65150°C T LEAD Lead T emperature during Soldering 1°C V IO Input or Output range –0.50 6.5V V CC Supply Voltage–0.50 6.5V V ESDElectrostatic Discharge Voltage (Human Body model) 2–40004000V13/25DC AND AC PARAMETERSThis section summarizes the operating and mea-surement conditions, and the DC and AC charac-teristics of the device. The parameters in the DC and AC Characteristic tables that follow are de-rived from tests performed under the Measure-ment Conditions summarized in the relevant tables. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parame-ters.Table 6. Operating Conditions (M24Cxx-W)Table 7. Operating Conditions (M24Cxx-R)Table 8. DC Characteristics (M24Cxx-W, Device Grade 6)Note: 1.The voltage source driving only E0, E1 and E2 inputs must provide an impedance of less than 1kOhm.Symbol ParameterMin.Max.Unit V CC Supply Voltage2.5 5.5V T AAmbient Operating T emperature (Device Grade 6)–4085°C Ambient Operating T emperature (Device Grade 3)–40125°CSymbol ParameterMin.Max.Unit V CC Supply Voltage1.8 5.5V T AAmbient Operating T emperature–4085°CSymbol ParameterTest Condition(in addition to those in Table 6.)Min.Max.Unit I LI Input Leakage Current(SCL, SDA, E0, E1,and E2)V IN = V SS or V CC± 2µA I LO Output Leakage Current V OUT = V SS or V CC, SDA in Hi-Z ± 2µA I CCSupply CurrentV CC =5V , f c =400kHz (rise/fall time < 30ns)2mA V CC =2.5V , f c =400kHz (rise/fall time < 30ns)1mA I CC1Stand-by Supply Current V IN = V SS or V CC , V CC = 5V 1µA V IN = V SS or V CC , V CC = 2.5V0.5µA V IL Input Low Voltage (1)–0.450.3V CC V V IH Input High Voltage (1)0.7V CCV CC +1V V OLOutput Low VoltageI OL = 2.1mA, V CC = 2.5V0.4V14/25Table 9. DC Characteristics (M24Cxx-W, Device Grade 3)Note: 1.The voltage source driving only E0, E1 and E2 inputs must provide an impedance of less than 1kOhm.Table 10. DC Characteristics (M24Cxx-R)Note: 1.The voltage source driving only E0, E1 and E2 inputs must provide an impedance of less than 1kOhm.Table 11. AC Measurement ConditionsSymbol ParameterTest Condition(in addition to those in Table 6.)Min.Max.Unit I LI Input Leakage Current(SCL, SDA, E0, E1,and E2)V IN = V SS or V CC± 2µA I LO Output Leakage Current V OUT = V SS or V CC, SDA in Hi-Z ± 2µA I CCSupply CurrentV CC =5V , f C =400kHz (rise/fall time < 30ns)3mA V CC =2.5V , f C =400kHz (rise/fall time < 30ns)3mA I CC1Stand-by Supply Current V IN = V SS or V CC , V CC = 5V 5µA V IN = V SS or V CC , V CC = 2.5V2µA V IL Input Low Voltage (1)–0.450.3V CC V V IH Input High Voltage (1)0.7V CCV CC +1V V OLOutput Low VoltageI OL = 2.1mA, V CC = 2.5V0.4VSymbol ParameterTest Condition(in addition to those in Table 7.)Min.Max.Unit I LI Input Leakage Current(SCL, SDA, E0, E1,and E2)V IN = V SS or V CC± 2µA I LO Output Leakage Current V OUT = V SS or V CC, SDA in Hi-Z ± 2µA I CC Supply CurrentV CC =1.8V , f c =400kHz (rise/fall time < 30ns)0.8mA I CC1Stand-by Supply Current V IN = V SS or V CC , V CC = 1.8V0.3µA V IL Input Low Voltage (1) 2.5V ≤ V CC –0.450.3V CC V 1.8V ≤ V CC < 2.5V–0.450.25V CC V V IH Input High Voltage (1)0.7V CC V CC +1V V OLOutput Low VoltageI OL = 0.7mA, V CC = 1.8V 0.2VSymbol ParameterMin.Max.Unit C LLoad Capacitance 100pF Input Rise and Fall Times 50ns Input Levels0.2V CC to 0.8V CC V Input and Output Timing Reference Levels0.3V CC to 0.7V CCV15/25Table 12. Input ParametersNote: 1.T A = 25°C, f = 400kHz2.Sampled only, not 100% tested.Symbol Parameter 1,2Test ConditionMin.Max.Unit C IN Input Capacitance (SDA)8pF C IN Input Capacitance (other pins)6pF Z WCL WC Input Impedance V IN < 0.3V 1570k ΩZ WCH WC Input Impedance V IN > 0.7V CC 500k Ωt NSPulse width ignored(Input Filter on SCL and SDA)Single glitch100nsTable 13. AC Characteristics (M24Cxx-W)Test conditions specified in Table 6. and Table 11.Symbol Alt.Parameter Min.Max.Unitf C f SCL Clock Frequency400kHzt CHCL t HIGH Clock Pulse Width High600ns t CLCH t LOW Clock Pulse Width Low1300nst DL1DL2 2t F SDA Fall Time20300ns t DXCX t SU:DAT Data In Set Up Time100ns t CLDX t HD:DA T Data In Hold Time0ns t CLQX t DH Data Out Hold Time200ns t CLQV 3t AA Clock Low to Next Data Valid (Access Time)200900ns t CHDX 1t SU:ST A Start Condition Set Up Time600ns t DLCL t HD:ST A Start Condition Hold Time600ns t CHDH t SU:STO Stop Condition Set Up Time600ns t DHDL t BUF Time between Stop Condition and Next Start Condition1300ns t W 4t WR Write Time5ms Note: 1.For a reSTART condition, or following a Write cycle.2.Sampled only, not 100% tested.3.To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.4.Previous devices bearing the process letter “L” in the package marking guarantee a maximum write time of 10ms. For more infor-mation about these devices and their device identification, please ask your ST Sales Office for Process Change Notices PCN MPG/ EE/0061 and 0062 (PCEE0061 and PCEE0062).Table 14. AC Characteristics (M24Cxx-R)Test conditions specified in Table 7. and Table 10.Symbol Alt.Parameter Min. 4Max. 4Unitf C f SCL Clock Frequency400kHzt CHCL t HIGH Clock Pulse Width High600ns t CLCH t LOW Clock Pulse Width Low1300nst DL1DL2 2t F SDA Fall Time20300ns t DXCX t SU:DAT Data In Set Up Time100ns t CLDX t HD:DA T Data In Hold Time0ns t CLQX t DH Data Out Hold Time200ns t CLQV 3t AA Clock Low to Next Data Valid (Access Time)200900ns t CHDX 1t SU:ST A Start Condition Set Up Time600ns t DLCL t HD:ST A Start Condition Hold Time600ns t CHDH t SU:STO Stop Condition Set Up Time600ns t DHDL t BUF Time between Stop Condition and Next Start Condition1300ns t W t WR Write Time10ms Note: 1.For a reSTART condition, or following a Write cycle.2.Sampled only, not 100% tested.3.To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.4.This is preliminary information.16/2517/25PACKAGE MECHANICALTable 15. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Mechanical DataSymb.mm inchesTyp.Min.Max.Typ.Min.Max.A 5.330.210A10.380.015A2 3.30 2.92 4.950.1300.1150.195 b0.460.360.560.0180.0140.022 b2 1.52 1.14 1.780.0600.0450.070 c0.250.200.360.0100.0080.014 D9.279.0210.160.3650.3550.400 E7.877.628.260.3100.3000.325 E1 6.35 6.107.110.2500.2400.280e 2.54––0.100––eA7.62––0.300––eB10.920.430 L 3.30 2.92 3.810.1300.1150.15018/25Note:Drawing is not to scale.Table 16. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Mechanical DataSymb.mm inchesTyp.Min.Max.Typ.Min.Max.A 1.35 1.750.0530.069A10.100.250.0040.010B0.330.510.0130.020C0.190.250.0070.010D 4.80 5.000.1890.197E 3.80 4.000.1500.157e 1.27––0.050––H 5.80 6.200.2280.244h0.250.500.0100.020L0.400.900.0160.035α0°8°0°8°N88CP0.100.00419/25Note: 1.Drawing is not to scale.2.The central pad (the area E2 by D2 in the above illustration) is pulled, internally, to V SS. It must not be allowed to be connected toany other voltage or signal line on the PCB, for example during the soldering process.Table 17. UFDFPN8 (MLP8) 8-lead Ultra thin Fine pitch Dual Flat Package No lead 2x3mm², DataSymbolmm inchesTyp.Min.Max.Typ.Min.Max.A0.550.500.600.0220.0200.024 A10.000.050.0000.002 b0.250.200.300.0100.0080.012D 2.000.079D2 1.55 1.650.0610.065 ddd0.050.002E 3.000.118E20.150.250.0060.010 e0.50––0.020––L0.450.400.500.0180.0160.020 L10.150.006 L30.300.012N8820/25。
51单片机 24c08读写并数码管显示
{
write_byte(i, fill_data);
}
}
/**********************************************************/
uchar read_current()
//在当前地址读取
{
uchar read_data;
uchar display[16]={//数码管的段码
0xc0,0xf9,0xa4,0xb0,0x99,0x92,0x82,0xf8,
0x80,0x90,0x88,0x83,0xc6,0xa1,0x86,0x8e},
a[8]={0x20,0x08,0x07,0x31,0xa1,0x08,0x11,0x23};//要显示的数
void write_byte(uchar addr, uchar write_data)
//在指定地址addr处写入数据write_data
{
start();
shout(OP_WRITE);
shout(addr);
shout(write_data);
stop();
delayms(10); //写入周期
uchar k[8],s[8];
sbit SDA = P2^7;
sbit SCL = P2^6;
/**********************************************************/
void delayms(uint ms)
//延时子程序
{
uchar k;
while(ms--)
{
for(k = 0; k < 120; k++);
SLA 24C08资料
Standard EEPROM ICs SLx 24C08/168/16 Kbit (1024/2048 × 8 bit) Serial CMOS-EEPROM withI2C Synchronous 2-Wire BusData Sheet1999-02-02Edition 1999-02-02Published by Siemens AG,Bereich Halbleiter, Marketing-Kommunikation, Balanstraße 73,81541 München© Siemens AG 1999.All Rights Reserved.Attention please!As far as patents or other rights of third par-ties are concerned, liability is only assumed for components, not for applications, pro-cesses and circuits implemented within components or assemblies.The information describes the type of component and shall not be considered as assured characteristics.Terms of delivery and rights to change design reserved.For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies and Representatives worldwide (see address list).Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Siemens Office, Semiconductor Group.Siemens AG is an approved CECC manufacturer.PackingPlease use the recycling operators known to you. We can also help you – get in touch with your nearest sales office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport.For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred.Components used in life-support devices or systems must be expressly authorized for such purpose!Critical components1 of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems2 with the express written approval of the Semiconductor Group of Siemens AG.1 A critical component is a component usedin a life-support device or system whose failure can reasonably be expected tocause the failure of that life-supportdevice or system, or to affect its safety or effectiveness of that device or system.2Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintainand sustain human life. If they fail, it isreasonable to assume that the health of the user may be endangered.Page Protection Mode™ is a trademark of Siemens AG.I 2C BusPurchase of Siemens I 2C components conveys the license under the Philips I 2C patent to use the components inthe I 2C system provided the system conforms to the I 2C specifications defined by Philips.SLx 24C08/16Revision History: Current Version: 1999-02-02Previous Version:06.97Page (in previous Version)Page (in current Version)Subjects (major changes since last revision)Changes in the complete document P-DIP-8-4 changed to P-DIP-8-3, P-DSO-8-3 changed to P-DSO-8-2.34Text changed to “Typical programming time 5 ms for up to 16bytes”.45SLA 24C08-D-3, SLA 24C08-S-3, SLA 24C16-D-3 and SLA 24C16-S-3 deleted.45Voltage changed from 4.5 V...5.5 V to 2.7 V...5.5 V.45Package (TSSOP, die, wafer delivery) added.56WP = V CC protects upper half entire memory.4, 55, 6CS0, CS1 and CS2 replaced by n.c.5–The paragraph “Chip Select (CS0, CS1, CS2)” removed completely.67Text changed to “The device with a voltage range of 2.7…5.5.V is available …”.11, 1212, 13The erase/write cycle is finished latest after 108ms.1314Text added “(see figure 10)”.1516Figure 11: second command byte is a CSR and not CSW.1718Figure 13: “CSW” changed to “CSR”.1819Line “Supply voltage”: Text deleted.1920“Capacitive load …” added.2021Some timings changed.2021The line “erase/write cycle” removed.2021Chapter 8.4 “Erase and Write Characteristics” added.8/16 Kbit (1024/2048 × 8 bit) Serial CMOS EEPROMs, I 2C Synchronous 2-Wire BusSLx 24C08/161Overview 1.1Features•Data EEPROM internally organized as1024/2048 bytes and 64/128 pages × 16 bytes •Low power CMOS•V CC = 2.7 to 5.5 V operation •Two wire serial interface bus,I 2C-Bus compatible•Filtered inputs for noise suppression with Schmitt trigger•Clock frequency up to 400 kHz •High programming flexibility –Internal programming voltage–Self timed programming cycle including erase –Byte-write and page-write programming, between 1 and 16 bytes –Typical programming time 5 ms for up to 16bytes •High reliability–Endurance 106 cycles 1)–Data retention 40 years 1)–ESD protection 4000 V on all pins •8 pin DIP/DSO packages•Available for extended temperature ranges –Industrial:− 40 °C to + 85 °C –Automotive:− 40°C to + 125 °C1)Values are temperature dependent, for further information please refer to your Siemens Sales office.Ordering Information Other types are available on request–Temperature range (– 55 °C … + 150 °C)–Package (TSSOP, die, wafer delivery)2Pin ConfigurationFigure 1Pin Configuration (top view)Type Ordering Code Package Temperature Voltage SLA 24C08-D Q67100-H3572P-DIP-8-3– 40 °C … + 85 °C 2.7 V...5.5 V SLA 24C08-S Q67100-H3518P-DSO-8-2– 40 °C … + 85 °C 2.7 V...5.5 V SLE 24C08-D Q67100-H3226P-DIP-8-3– 40°C … + 125 °C 2.7 V...5.5 V SLE 24C08-S Q67100-H3227P-DSO-8-2– 40°C … + 125 °C 2.7 V...5.5 V SLA 24C16-D Q67100-H3513P-DIP-8-3– 40 °C … + 85 °C 2.7 V...5.5 V SLA 24C16-S Q67100-H3508P-DSO-8-2– 40 °C … + 85 °C 2.7 V...5.5 V SLE 24C16-D Q67100-H3229P-DIP-8-3– 40°C … + 125 °C 2.7 V...5.5 V SLE 24C16-SQ67100-H3230P-DSO-8-2– 40°C … + 125 °C2.7 V...5.5 VPin Definitions and Functions Pin Description Serial Clock (SCL)The SCL input is used to clock data into the device on the rising edge and to clock data out of the device on the falling edge.Serial Data (SDA)SDA is a bidirectional pin used to transfer addresses, data or control information into the device or to transfer data out of the device. The output is open drain, performing a wired AND function with any number of other open drain or open collector devices. The SDA bus requires a pull-up resistor to V CC . Write Protection (WP)WP switched to V SS allows normal read/write operations.WP switched to V CC protects the entire EEPROM against changes (hardware write protection).Table 1Pin No.Symbol Function 1, 2, 3N. C.Not connected 4V SSGround5SDA Serial bidirectional data bus 6SCL Serial clock input 7WPWrite protection input 8V CCSupply voltage3DescriptionThe SLx 24C08/16 device is a serial electrically erasable and programmable read only memory (EEPROM), organized as 1024/2048 × 8 bit. The data memory is divided into 64/128pages. The 16 bytes of a page can be programmed simultaneously.The device conforms to the specification of the 2-wire serial I2C-Bus. Low voltage design permits operation down to 2.7 V with low active and standby currents.The device operates at 5.0V ± 10% with a maximum clock frequency of 400kHz and at 2.7 ... 4.5V with a maximum clock frequency of 100kHz. The device with a voltage range of 2.7…5.5.V is available in two temperature ranges for industrial and automotive applications. The EEPROMs are mounted in eight-pin DIP and DSO packages or are also supplied as chips.Figure 2Block Diagram4I2C-Bus CharacteristicsThe SLx 24C08/16 devices support a master/slave bidirectional bus oriented protocol in which the EEPROM always takes the role of a slave.Figure 3Bus ConfigurationMaster Device that initiates the transfer of data and provides the clock for both transmit and receive operations.Slave Device addressed by the master, capable of receiving and transmitting data.Transmitter The device with the SDA as output is defined as the transmitter. Due to the open drain characteristic of the SDA output the device applying a lowlevel wins.Receiver The device with the SDA as input is defined as the receiver.The conventions for the serial clock line and the bidirectional data line are shown in figure4.Figure 4I2C-Bus Timing Conventions for START Condition, STOP Condition, Data Valida-tion and Transfer of Acknowledge ACKStandby Mode in which the bus is not busy (no serial transmission, noprogramming): both clock (SCL) and data line (SDA) are in highstate. The device enters the standby mode after a STOP conditionor after a programming cycle.START Condition High to low transition of SDA when SCL is high, preceding allcommands.STOP Condition Low to high transition of SDA when SCL is high, terminating allcommunications. A STOP condition initiates an EEPROMprogramming cycle. A STOP condition after reading a data bytefrom the EEPROM initiates the Standby mode.Acknowledge A successful reception of eight data bits is indicated by thereceiver by pulling down the SDA line during the following clockcycle of SCL (ACK). The transmitter on the other hand has torelease the SDA line after the transmission of eight data bits.The EEPROM as the receiving device responds with anacknowledge, when addressed. The master, on the other side,acknowledges each data byte transmitted by the EEPROM andcan at any time end a read operation by releasing the SDA line (noACK) followed by a STOP condition.Data Transfer Data must change only during low SCL state, data remains validon the SDA bus during high SCL state. Nine clock pulses arerequired to transfer one data byte, the most significant bit (MSB)is transmitted first.5Device Addressing and EEPROM AddressingAfter a START condition, the master always transmits a Command Byte CSW or CSR. After the acknowledge of the EEPROM a Control Byte follows, its content and the transmitter depend on the previous Command Byte. The description of the Command and Control Bytes is shown in table 2.Command Byte Selects operation: the least significant bit b0 is low for a write operation (Chip Select Write Command Byte CSW) or set high for aread operation (Chip Select Read Command Byte CSR).Contains address information: in the CSW Command Byte, thebit positions b2 or b3 to b1 are decoded for the two or threeuppermost EEPROM address bits A9 or A10 to A8 (in the CSRCommand Byte, the bit positions b3 to b1 are left undefined). Control Byte Following CSW (b0 = 0): contains the eight lower bits of the EEPROM address (EEA) bit A7 to A0.Following CSR (b0 = 1): contains the data read out, transmitted bythe EEPROM. The EEPROM data are read as long as the masterpulls down SDA after each byte in order to acknowledge thetransfer. The read operation is stopped by the master by releasingSDA (no acknowledge is applied) followed by a STOP condition. Table 2Command and Control Byte for I2C-Bus Addressing of Chip and EEPROMDefinition Functionb7b6b5b4b3b2b1b0CSW1010A10A9A80Chip Select for WriteCSR1010x x x1Chip Select for ReadEEA A7A6A5A4A3A2A1A0EEPROM addressThe device has an internal address counter which points to the current EEPROM address.The address counter is incremented–after a data byte to be written has been acknowledged, during entry of further data byte–during a byte read, thus the address counter points to the following address after reading a data byte.The timing conventions for read and write operations are described in figures5 and 6.Figure 5Timing of the Command Byte CSWFigure 6Timing of the Command Byte CSR6Write OperationsChanging of the EEPROM data is initiated by the master with the command byte CSW. Depending on the state of the Write Protection pin WP either one byte (Byte Write) or up to 16 bytes (Page Write) are modified in one programming procedure.6.1Byte WriteAddress Setting After a START condition the master transmits the Chip SelectWrite byte CSW. The EEPROM acknowledges the CSW byteduring the ninth clock cycle. The following byte with theEEPROM address (A0 to A7) is loaded into the addresscounter of the EEPROM and acknowledged by the EEPROM. Transmission of Data Finally the master transmits the data byte which is alsoacknowledged by the EEPROM into the internal buffer. Programming Cycle Then the master applies a STOP condition which starts theinternal programming procedure. The data bytes are written inthe memory location addressed in the EEA byte (A0 to A7)and the CSW byte (A8 to A9 or A10). The programmingprocedure consists of an internally timed erase/write cycle. Inthe first step, the selected byte is erased to “1”. With the nextinternal step, the addressed byte is written according to thecontents of the buffer.Figure 7Byte Write SequenceThe erase/write cycle is finished latest after 8 ms. Acknowledge polling may be used for speed enhancement in order to indicate the end of the erase/write cycle (refer to chapter6.3 Acknowledge Polling).6.2Page WriteAddress Setting The page write procedure is the same as the byte writeprocedure up to the first data byte. In a page write instructionhowever, entry of the EEPROM address byte EEA is followedby a sequence of one to maximum sixteen data bytes with thenew data to be programmed. These bytes are transferred tothe internal page buffer of the EEPROM.Transmission of Data The first entered data byte will be stored according to theEEPROM address n given by EEA (A0 to A7) and CSW (A8 toA9 or A10). The internal address counter is incrementedautomatically after the entered data byte has beenacknowledged. The next data byte is then stored at the nexthigher EEPROM address. EEPROM addresses within thesame page have common page address bits A4 through A10.Only the respective four least significant address bits A0through A3 are incremented, as all data bytes to beprogrammed simultaneously have to be within the same page. Programming Cycle The master stops data entry by applying a STOP condition,which also starts the internally timed erase/write cycle. In thefirst step, all selected bytes are erased to “1”. With the nextinternal step, the addressed bytes are written according to thecontents of the page buffer.Those bytes of the page that have not been addressed are not included in the programming.Figure 8Page Write SequenceThe erase/write cycle is finished latest after 8 ms. Acknowledge polling may be used for speed enhancement in order to indicate the end of the erase/write cycle (refer to chapter6.3 Acknowledge Polling).6.3Acknowledge PollingDuring the erase/write cycle the EEPROM will not respond to a new command byte until the internal write procedure is completed. At the end of active programming the chip returns to the standby mode and the last entered EEPROM byte remains addressed by the address counter. To determine the end of the internal erase/write cycle acknowledge polling can be initiated by the master by sending a START condition followed by a command byte CSR or CSW (read with b0 = 1 or write with b0 = 0). If the internal erase/ write cycle is not completed, the device will not acknowledge the transmission. If the internal erase/write cycle is completed, the device acknowledges the received command byte and the protocol activities can continue (see figure10).Figure 9Flow Chart “Acknowledge Polling”Figure 10Principle of Acknowledge Polling7Read OperationsReading of the EEPROM data is initiated by the Master with the command byte CSR.7.1Random ReadRandom read operations allow the master to access any memory location.Figure 11Random ReadAddress SettingThe master generates a START condition followed by the command byte CSW. The receipt of the CSW-byte is acknowledged by the EEPROM with a low on the SDA line.Now the master transmits the EEPROM address (EEA) to the EEPROM and the internal address counter is loaded with the desired address.Transmission of CSRAfter the acknowledge for the EEPROM address is received,the master generates a START condition, which terminates the initiated write operation. Then the master transmits the command byte CSR for read, which is acknowledged by the EEPROM.Transmission of EEPROM DataDuring the next eight clock pulses the EEPROM transmits the data byte and increments the internal address counter.STOP Condition from Master During the following clock cycle the masters releases the bus and then transmits the STOP condition.7.2Current Address ReadThe EEPROM content is read without setting an EEPROM address, in this case the current content of the address counter will be used (e.g. to continue a previous read operation after the Master has served an interrupt).Figure 12Current Address ReadTransmission of CSRFor a current address read the master generates a START condition, which is followed by the command byte CSR (chip select read). The receipt of the CSR-byte is acknowledged by the EEPROM with a low on the SDA line.Transmission of EEPROM DataDuring the next eight clock pulses the EEPROM transmits the data byte and increments the internal address counter.STOP Condition from Master During the following clock cycle the masters releases the bus and then transmits the STOP condition.7.3Sequential ReadA sequential read is initiated in the same way as a current read or a random read except that the master acknowledges the data byte transmitted by the EEPROM. The EEPROM then continues the data transmission. The internal address counter is incremented by one during each data byte transmission.A sequential read allows the entire memory to be read during one read operation. After the highest addressable memory location is reached, the internal address pointer “rolls over” to the address 0 and the sequential read continues.The transmission is terminated by the master by releasing the SDA line (no acknowledge) and generating a STOP condition (see figure 13).Figure 13Sequential Read8Electrical CharacteristicsThe listed characteristics are ensured over the operating range of the integrated circuit.Typical characteristics specify mean values expected over the production spread. If not otherwise specified, typical characteristics apply at T A = 25°C and the given supplyvoltage.8.1Absolute Maximum RatingsStresses above those listed here may cause permanent damage to the device. This is astress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this data sheet is not implied.Exposure to absolute maximum ratings for extended periods may affect device reliability.ParameterLimit Values Units Operating temperature range 1 (industrial)range 2 (automotive)– 40 to + 85 – 40 to + 125 °C °C Storage temperature – 65 to + 150 °C Supply voltage– 0.3 to + 7.0 V All inputs and outputs with respect to ground – 0.3 to V CC +0.5V ESD protection (human body model)4000V8.2DC CharacteristicsParameterSymbolLimit ValuesUnits Test Conditionmin.typ.max.Supply voltageV CC2.75.5V Supply current 1) (write)I CC 13mA V CC =5V;f c =100 kHzStandby current 2)I SB 50 µA Inputs at V CC or V SSInput leakage currentI LI0.110µA V IN =V CC or V SS Output leakage current I LO 0.110µAV OUT =V CC or V SSInput low voltage V IL – 0.30.3×V CC VInput high voltageV IH0.7×V CCV CC +0.5VOutput low voltage V OL 0.4V I OL =3 mA; V CC =5 V I OL =2.1 mA; V CC =3V Input/output capacitance (SDA)C I/O 83)pFV IN =0 V; V CC =5 V Inputcapacitance (other pins)C IN63)pFV IN =0 V; V CC =5 VCapacitive load for each bus lineC b 400pF1)The values for I CC are maximum peak values 2)Valid over the whole temperature range 3)This parameter is characterized only8.2DC Characteristics (cont’d)Parameter SymbolLimit ValuesUnits Test Conditionmin.typ.max.8.3AC CharacteristicsParameterSymbolLimit Values V CC = 2.7-5.5 V Limit Values V CC = 4.5-5.5 V Units min.max.min.max.SCL clock frequency f SCL 100400kHz Clock pulse width lowt low 4.7 1.2µs Clock pulse width hight high 4.00.6µsSDA and SCL rise timet R 10001)300ns SDA and SCL fall timet F 3001)300ns Start set-up timet SU.STA 4.70.6µs Start hold timet HD.STA 4.00.6µs Data in set-up timet SU.DAT 200100ns Data in hold timet HD.DAT 00µsSCL low to SDA data out validt AA 0.1 4.50.10.9µs Data out hold timet DH 10050ns Stop set-up timet SU.STO 4.00.6µs Time the bus must be free before a new transmission can start t BUF4.7 1.2µsSDA and SCL spike suppression time at constant inputst l 5010050100ns1)The minimum rise and fall times can be calculated as follows: 20 + (0.1/pF) × C b [ns]Example: C b = 100 pF → t R = 20 + 0.1 × 100 [ns] = 30 ns8.4Erase and Write CharacteristicsParameterSymbolLimit Values V CC = 2.7-5.5 V Limit Values V CC = 4.5-5.5 V Units typ.max.typ.max.Erase + write cycle (per page)t WR5858ms Erase page protection bit 2.54 2.54ms Write page protection bit2.542.54msFigure 14Bus Timing Data。
K24c08
查 询 K24C08供 应 商K24C08品特点Vcc = +1.8V~5.5V境温: -40℃~+85℃构: K24C08, 1024 X 8 (8k Bits) 串行接口 入施密波抑制噪声双向议 1 MHz (5V), 400 kHz (1.8V, 2.5V, 2.7V) 兼容支持硬件写保护1页写模式 支持写写周期内（最大5mS ） 高可靠性：写次数：1，000，000次 数据保存：100年符合RoHS 要求的PDIP8、SOP8、TSSOP8封装 介K 24C 08是8192位的可擦器，124，每8芯片被用压 及低功耗的域。
明 第1页引脚描述 表1: 明 器地址引脚(A2): K 24C 使用A 器件入脚。
在线上址两个8K 器件。
串行出引脚： S D A 引现双向串行输出，可与其它多个出器件或极或连 接。
钟信号引脚： 在S 钟信号的上升沿将数据送入E E P R O M 器件，钟的下降沿将出。
引脚： K 24C 08提供一个硬件脚位数据。
当引脚接G 正写操作，当引脚接V，被区 域如表2所示。
表2: 写保护 脚K24C08 接V c c （8K ） 接G N D /写工作 第2页第3页K24C08, 8k EEPROM: 内部由构成16，8K E E P R O M 需要10位的地址。
器件操作 及: S D A 引脚通常器件拉高。
S D A 引脚数据只在S 变1）；当数据在S 变化，将 下文所述的一个起始或停止命令。
起始条件: 当S ，S D A 由高到为起始命令，任何/写操以起始命开始2）。
停止条件: 当S ，S D A 由低到为停止命令，在操作后，停止命令会使E E P R 入低功 耗模式2）。
应答: 所有的地址和数都是以出的。
每收8位的数据后，EEPROM 都会在第9个时 钟每当主控器件接收8位的数据当在第钟周期向EEPROM 返回一个应 答信号。
应答信号后，E E P R O 出8位的数据。
存储器24C08的串口读取与写入程序
到４００ＫＨＺ，在实际使用中，为了保证２４Ｃ０８
为了提高程序效率。这里对２４Ｃ０８的数据写入
的稳定工作，通常要通过在汇编程序中插入空
也是采用的连续写入方式。连续写入的方式与连
操作这种做法，来降低同步时钟频率，以保证
续读取的方式截然不同。在这种连续写入方式下。
与２４Ｃ０８的时钟频率相匹配。５、６两脚分别为
ａ
ｄ ｛８ ｄ ｛８ 引蛇
ＥＱＵ ｐ２．０ ＥＱＵ ｐ２．１ ＥＱＵ ０８Ｈ ＥＯＵ ０９Ｈ
ｐ３７＝ｐ３‘７
ｉ：＝
ｐ３６＝ｐ３‘６
００００Ｈ
姚蚓删删洲蝴９吣巾帅
ｓｔａｒｔ
：＝＝＝一＝＝总线启动
ｉ２ｃ—ｓｔａｒｔ：
将导致双方ＲＳ２３２接口数据传送不能正常进行
ｓｅｔｂ
ＳＣｌ
和２４Ｃ０８数据写入出错。那选择多少的传输速
的晶振，它的指令周期约为１微秒。然而单片机 在异步接收的同时还要承担将电脑传输的数据写
２４００
１１ ０５９２
０
Ｆ４ｈ
１２００
１１ ０５９２
０
Ｅ８ｈ
２４Ｃ０８的数据连续读取及１０２４字节写入的
入２４Ｃ０８中这个任务。这种简单的三线异步通
完整汇编程序如下：
讯。电脑的数据发送将严格按照约定进行。而不 理会单片机对２４Ｃ０８的数据写入是否已经完成。 芯片内部ＲＳ２３２接口对数据的接收自动完成的。 但不会将接收的数据主动传送给单片机，在实际 读取过程中。程序必须预留适当的时间来完成对 异步接收标志位Ｒｌ的检测与控制。如果写入耗 费的时间太多，则单片机ＲＳ２３２接口收到的数 据将得不到及时处理．而接收控制位ＲＩ不能及 时清零，电脑侧发送的数据也将会丢失。所以异 步传输的速率设置就比较重要了，设置快了。必
M24C08只读存储器
序号
符号
功能
直流电压（V）
序号
符号
功能
直流电压（V）
1
GND
接地
0
5
SDA1
一系列的地址/数据的输入/输出
5.01
2
GND
接地
0
6
SCL1
一系列的时钟输入
5.01
3
GND
接地
0
7
GND
接地
0
4
GND
接地
8
VCC
供电电压
5.02
M24C08只读存储器
概述：M24C08是只读存储器，它是使用组装CMOS EEPROM技术，工作在的电源、低频率的条件。它能接收、存储微处理单元集成电路提供的数据，它既可以作发送器（主控），又可义作接收器。一旦微处理单元需要其中存储的数据信号，可以随时输入或输入。由于该存储器为非挥发型电可擦除只读存储器，所以即使在切断电源的情况下，数据也可永久保存。具有以下特点：低电源CMOS技术，在待机状态时电流为2μA，在读数据时电流为1mA，在写操作时电流为3mA
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A2 3
6 SCL are a device type code signifying an EEPROM device. A2 is
GND 4 5 SDA the device address select bit which has to match the A2 pin
SERIAL CLOCK (SCL) The SCL input synchronizes the data on the SDA bus. It is used in conjunction with SDA to define the start and stop conditions. It is also used in conjunction with SDA to transfer data to and from the Turbo IC 24C08.
For a read operation, the master issues a start condition and a device address byte. The Turbo IC 24C08 acknowledges, and then transmits a data byte, which is accessed from the EEPROM memory.The master acknowledges, indicating that it requires more data bytes. The Turbo IC 24C08 transmits more data bytes, with the memory address counter automatically incrementing for each data byte, until the master does not acknowledge, indicating that it is terminating the transmission. The master then issues a stop condition.
Data Retention : 100 Years
DESCRIPTION: The Turbo IC 24C08 is a serial 8K EEPROM fabricated with Turbo’s proprietary, high reliability, high performance CMOS technology. It’s 8K of memory is organized as 1,024 x 8 bits. The memory is configured as 64 pages with each page containing 16 bytes. This device offers significant advantages in low power and low voltage applications.
each byte is transmitted, the receiver has to provide an ac-
knowledge by pulling the SDA bus low on the ninth clock
cycle. The acknowledge is a handshake signal to the trans-
Turbo IC, Inc.
24C08
CMOS I²C 2-WIRE BUS 8K ELECTRICALLY ERASABLE PROGRAMMABLE ROM
1K X 8 BIT Eended Power Supply Voltage
Single Vcc for Read and Programming (Vcc = 2.7 V to 5.5 V) • Low Power (Isb = 2µa @ 5.5 V) • I²C Bus, 2-Wire Serial Interface • Support Byte Write and Page Write (16 Bytes) • Automatic Page write Operation (maximum 10 ms) Internal Control Timer Internal Data Latches for 16 Bytes • High Reliability CMOS Technology with EEPROM Cell Endurance : 1,000,000 Cycles
The Turbo IC 24C08 uses the I²C addressing protocol and 2-wire serial interface which includes a bidirectional serial data bus synchronized by a clock. It offers a flexible byte write and a faster 16-byte page write.
write operation, the controller (master) issues a start condi-
NC 1 NC 2
8 VCC tion by pulling SDA from high to low while SCL is high. The master then issues the device address byte which consists
SERIAL DATA (SDA) SDA is a bidirectional pin used to transfer data in and out of the Turbo IC 24C08. The pin is an open-drain output. A pullup resistor must be connected from SDA to Vcc.
mitter indicating a successful data transmission.
PIN DESCRIPTION
DEVICE ADDRESS (A2) A2 is a device address input that enables a total of two 24C08 devices to connect on a single bus. When the address input pin is left unconnected, it is interpreted as zero.
input on the 24C08 device. The B[9:8] bits are the 2 most
8 pin PDIP
significant bits of the memory address. The read/write bit determines whether to do a read or write operation. After
The Turbo IC 24C08 is assembled in either a 8-pin PDIP or 8-pin SOIC package. Pin #1, #2 and #7 are not connected (NC). Pin #3 is the A2 device address input for the 24C08, such that a total of two 24C08 devices can be connected on a single bus. Pin #4 is the ground (Vss). Pin #5 is the serial data (SDA) pin used for bidirectional transfer of data. Pin #6 is the serial clock (SCL) input pin. Pin #8 is the power supply (Vcc) pin.
DEVICE OPERATION:
BIDIRECTIONAL BUS PROTOCOL: The Turbo IC 24C08 follows the I²C bus protocol. The protocol defines any device that sends data onto the SDA bus as a transmitter, and the receiving device as a receiver. The device controlling the transfer is the master and the device being controlled is the slave. The master always initiates the data transfers, and provides the clock for both transmit and receive operations. The Turbo IC 24C08 acts as a slave device in all applications. Either the master or the slave can take control of the SDA bus, depending on the requirement of the protocol.
ACKNOWLEDGE: All data is serially transmitted in bytes (8 bits) on the SDA bus. The acknowledge protocol is used as a handshake signal to indicate successful transmission of a byte of data. The bus transmitter, either the master or the slave (Turbo IC 24C08), releases the bus after sending a byte of data on the SDA bus. The receiver pulls the SDA bus low during the ninth clock cycle to acknowledge the successful transmission of a byte of data. If the SDA is not pulled low during the ninth clock cycle, the Turbo IC 24C08 terminates the data transmission and goes into standby mode.